OFFCORE_RSP_1 always gives zero count of uncore events

[Jithin_Parayil_T_]

I'm trying to count uncore events (specifically LLC Hits) on a Nehalem machine but when I use OFFCORE_RSP_1, it always gives a zero count. However, OFFCORE_RSP_0 seems to be working fine.

Here is how I'm trying to read uncore events via OFFCORE_RSP_1:

   PerfEvtSel0 (address: 0x186) -> set this to value 0x04101BB

   OFFCORE_RSP_1 (address: 0x1A7) -> set this to value 0x0700 (to count LLC Hits)

But when I read IA32_PMC0 (address: 0xC1), the count is always 0.

However, if set PerfEvtSel0 to 0x04101B7 (to use OFFCORE_RSP_0 instead) then the count is non-zero.

Am I missing something?

Following is my machine configuration:

Intel(R) Xeon(R) CPU  X5550 system with 2 sockets - each containing 4 cores (Hyperthreading is enabled)

[McCalpinJohn]

Nehalem only supports one offcore response monitoring event --- support for the second offcore response event was added with the Westmere processors.

This is described in Chapter 18 of Volume 3 of the Intel Architectures Software Developer's Guide (document 325384-052, September 2014).  Section 18.7.1.3 describes the offcore response monitoring in Nehalem and section 18.8 notes that the second offcore response monitor event was added with Westmere.

[Jithin_Parayil_T_]

Thanks John.

That should be the reason then.

Just to clarify further, the Nehalem-PMU-Programming Guide (https://software.intel.com/sites/default/files/76/87/30320) mentions about two OFFCORE_RSP_X registers. Is that an error or am I referring to the guide for Westmere processors?

Thanks again,

Jithin

[McCalpinJohn]

The document should clarify that the second offcore response counter is only available in the Westmere generation of processors.  These are still in the Nehalem "family", so there are not many differences, but this feature is definitely different between Nehalem and Westmere.

[Jithin_Parayil_T_]

Ok. Thanks John.

--Jithin