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PCIe ReTrain measurement

Rony_R_Intel
Employee
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Hi,

 

I'm using SocWatch for analyzing the performance of a Wireless NIC. According to the PCIe LPM Report, the device spends its time in L0 (73%), L1(22%) and Retrain (5%). I'm trying to understand if the high Retrain part indicates a problem or maybe the L0/L1 transitions are being counted as retrain. I did not manage to find any documentation regarding the definition of the PCIe link state counters. Any help would be appreciated.

 

This is the platform information from SocWatch:

 

CPU codename: Skylake

Number of packages: 1

Number of cores per package: 2

Number of logical processors per core: 2

GT SKU: GT2 SKL-ULT3

PCH Device: Skylake PCH-LP (SPT-LP)

 

Regards,

 

Rony

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