1.) Many machine code instructions are decoded into multiple micro-ops.Few of them are x87 FPU fsin and fcos also rdtsc is decoded in multiple more primitive instructions.I think that simple mov instructions are decoded into one micro-op.For example push instruction could issue two micro-ops one for moving data and second for decrementing Sp.Also flow control instructions like call and ret are decoded into few micro-ops.Micro-ops at hardware level could be represented as specifically pcm encoded square waveforms which in some cases operate as a trigger or input to some logical units.
2)Interrupt is an asynchronous event which can occure anytime.Think about the NIC card interrupting CPU for frame processing such interrupt can come in the middle of some code execution then CPU will look up specific handler for IV in IDT and transfer an execution to that handler also current context will be saved and restored later.This is at machine code level(assembly level).I only suppose that at microarchitecture level and because of decoupled design part of currently executed microops will be kept in internal buffers when the cpu will be servicing a higher priority code like ISR.
