(1) Does the event set is inherited by newer processor model from older model family (like 3rd generation to 4th generation) , or instead , it is independent event set in each processor model
for example, as Intel SDM said, 3rd generation process could monitor DTLB_LOAD_MISSES.WALK_COMPLETED with event num. 08H and unit mask 82H , does it still work in later generation?
(2) Considering such an following instruction sequence, something like windows Idle thread
when I use the event that BR_MISP_EXEC.TAKEN | BR_MISP_EXEC.RETURN_NEAR , PMI occur in RET every time,
could someone explain to me that what does it imply? the 3---> RET never be executed ??
Many events are carried over from generation to generation. In particular, the "architectural" events carry over, mostly indefinitely (some are added from time-to-time when the architectural perfmon version is incremented).
For the non-architectural events, which make up the vast majority of events, many are carried over from version to version: these are well documented in the software development manual so you can easily see that many events exist for several generations. However many events do change: they might change their definition, their event code or other values, etc. Many events also disappear, e.g., documented on Haswell but not on Skylake: but go ahead and try them: you'll often find that the events that disappear seem to still work on the newer generation. So maybe they just accidentally weren't documented in the new arch, or maybe they have some serious flaw which means they are no longer supported.
For your question (2) it seems obvious to me that out of those three instructions, only the ret will ever "mispredict" or "return", so it makes sense that the PMI is always taken at the ret (apparently there is no skid in your case).