Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
1790 Discussions

Unit mask(umask)

Bo_W_3
Beginner
‎03-04-2013 11:26 AM
810 Views

Hi,

I'm writing a program for computing FLOPS and need now several MSRs, such as FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION. My question is what is the address for it? Ist it 0x1040 or 0x4010 or neither.

And one more question: Does

FP_COMP_OPS_EXE.SSE_FP_SCALAR  +  FP_COMP_OPS_EXE.SSE_FP_PACKED = FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION + FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION  ?

Thanks for your answer

0 Kudos

Link Copied

2 Replies
Bernard
Valued Contributor I
‎03-10-2013 10:43 PM
810 Views

Please read this post

Link ://software.intel.com/en-us/forums/topic/293822

0 Kudos
Copy link
Bernard
Valued Contributor I
‎03-10-2013 10:44 PM
810 Views
Please read this post Link: ://software.intel.com/en-us/forums/topic/293822 P.S I removed a "http" protocol identifier becuse of spam filter activity.
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.