Utilization vs. C0 Residency

[Omer_B_Intel]

Hi,

Core Utilization and Core C0 Residency

Seems pretty basic, but I've heard both terms used in different context, and I wonder why. 

I believe they mean the same - number of Unhalted (C0) Cycles divided by Potential Number of  Cycles, which can be measured by FixedCtr3 / TSC.

Is this true or am I missing something? is there some logical core vs. physical core peculiarity here?

Thanks,

Omer

[McCalpinJohn]

It can be very hard to tell when documentation uses different terms as synonyms or because they are talking about different things.

"Core C0 Residency" seems more amenable to an unambiguous definition...

I usually refer to "reference cycles not halted / TSC" as "core utilization", but that is a bit sloppy.  A software-oriented person might only count "utilization" when the core is doing something useful -- for example, they might exclude time in the kernel "poll_idle()" routine.

The FixedCtr3 definition is not quite right when the system is configured with the FREEZE_WHILE_SMM bit is set in IA32_DEBUG_CTL (bit 14 of MSR 0x1d9).   While servicing system management interrupts, the fixed counters will not increment, even though the processor is in C0.