about J1900 SMI_LOCK SMI_EN

[Liang_Y_]

any one can help for this thread?

https://communities.intel.com/thread/125351

about J1900 SMI_LOCK SMI_EN

    to get a good realtime performance, i want to disablle SMI on my J1900 MasterBoard, i edit the linux kernel, add some line in file [arch/x86/platform/atom/pmc_atom.c]:

    here is what i have done:

    1.clear SMI_EN.GBL_SMI_EN

    2.set GEN_PMCON2.SMI_LOCK (yes,this bit before i set, it'vaule is zero--which mean BIOS doesn't LOCK SMI)

    when the kernel running, use "sudo rdmsr --all 0x34" to check MSR_SMI_COUNT, but MSR_SMI_COUNT increased when time elapsed，WHY？

--1.two functions added in [arch/x86/platform/atom/pmc_atom.c]

static void clr_smi_en(void)

{

    u16    reg_port;

    u32    reg_value;

    pr_info("DNK_clr_smi_en\n");

    reg_port = acpi_base_addr + 0x30;

    reg_value = inl(reg_port);

    printk("DNK_A: SMI_EN:\t0x%08x\n", reg_value);

    reg_port = acpi_base_addr + 0x34;

    reg_value = inl(reg_port);

    printk("SMI_STS:\t0x%08x\n", reg_value);

    reg_port = acpi_base_addr + 0x30;

    outl(0, reg_port);

    reg_value = inl(reg_port);

    printk("DNK_B: SMI_EN:\t0x%08x\n", reg_value);

}

static void pmc_smi_lock(struct pmc_dev *pmc)

{

    u32 gen_pmcon2;

    gen_pmcon2 = pmc_reg_read(pmc, 0x24);

    printk("DNK_A: GEN_PMCON2=0x%08x", gen_pmcon2);

    gen_pmcon2 |= 0x00000010;

    printk("DNK_C: GEN_PMCON2=0x%08x", gen_pmcon2);

    pmc_reg_write(pmc, 0x24, gen_pmcon2);

    gen_pmcon2 = pmc_reg_read(pmc, 0x24);

    printk("DNK_B: GEN_PMCON2=0x%08x", gen_pmcon2);

}

--2.call these functions in function pmc_setup_dev which called by pmc_atom_init .

    clr_smi_en();

    pmc_smi_lock(pmc);

--3.dmesg log:

dnk@dnk-baytrail:~$ dmesg | grep DNK

[    3.548661] DNK:pmc_atom_init

[    3.548765] pmc_atom: DNK_clr_smi_en

[    3.548786] DNK_A: SMI_EN:    0x00000033

[    3.548831] DNK_B: SMI_EN:    0x00000002

[    3.548851] DNK_A: GEN_PMCON2=0x00040400

[    3.548870] DNK_C: GEN_PMCON2=0x00040410

[    3.548892] DNK_B: GEN_PMCON2=0x00040410

Register Reference:

<Intel ® Pentium ® Processor N3500-series, J2850, J2900, and Intel ®Celeron ® Processor N2900-series,N2800-series, J1800-series, J1900,J1750>

Document Number: 329670-004

p997 20.5.6 General PM Configuration 2 (GEN_PMCON2)—Offset 24h

bit4

SMI Lock (SMI_LOCK) (smi_lock): When this bit is set, writes to the GBL_SMI_EN

bit will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will

have no effect (i.e. once set, this bit can only be cleared by PMU_PLTRST).

p1035 20.7.6 SMI_EN - SMI Control and Enable (SMI_EN)—Offset 30h

bit0

Global SMI Enable (GBL_SMI_EN): (gbl_smi_en): When set, this bit enables the

generation of SMIs in the system upon any enabled SMI event. This bit is reset by a

PMU_PLTRST_B reset event. If this bit is not set, no SMI# will be generated. NOTE:

When the SMI_LOCK bit is set, this bit cannot be changed.

<Intel ® 64 and IA-32 Architectures Software Developer’s Manual>

Document Number: 252046-052

p980

Table 35-18. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge

0x34 MSR_SMI_COUNT

this model specific register (MSR), returning the count of SMI since boot.