Software Tuning, Performance Optimization & Platform Monitoring
Discussion around monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform monitoring
Announcements
This community is designed for sharing of public information. Please do not share Intel or third-party confidential information here.

how to manage l3 cache allocate to different cores on 10980xe

Jiangv
Beginner
292 Views

I read many articals on internet about cmt cat, but still no clue about how to allocate l3 cache on my core x CPU, I got this output from my server

root:~>pqos -s -V
NOTE:  Mixed use of MSR and kernel interfaces to manage
       CAT or CMT & MBM may lead to unexpected behavior.
INFO: CACHE: type 1, level 1, max id sharing this cache 2 (1 bits)
DEBUG: CACHE: not inclusive, direct mapped, 8 way(s), 64 set(s), line size 64, 1 partition(s)
INFO: CACHE: type 2, level 1, max id sharing this cache 2 (1 bits)
DEBUG: CACHE: not inclusive, direct mapped, 8 way(s), 64 set(s), line size 64, 1 partition(s)
INFO: CACHE: type 3, level 2, max id sharing this cache 2 (1 bits)
DEBUG: CACHE: not inclusive, direct mapped, 16 way(s), 1024 set(s), line size 64, 1 partition(s)
INFO: CACHE: type 3, level 3, max id sharing this cache 64 (6 bits)
DEBUG: CACHE: not inclusive, complex cache indexing, 11 way(s), 36864 set(s), line size 64, 1 partition(s)
DEBUG: Detected core 0, socket 0, L2 ID 0, L3 ID 0, APICID 0
DEBUG: Detected core 1, socket 0, L2 ID 1, L3 ID 0, APICID 2
DEBUG: Detected core 2, socket 0, L2 ID 2, L3 ID 0, APICID 4
DEBUG: Detected core 3, socket 0, L2 ID 3, L3 ID 0, APICID 6
DEBUG: Detected core 4, socket 0, L2 ID 4, L3 ID 0, APICID 8
DEBUG: Detected core 5, socket 0, L2 ID 8, L3 ID 0, APICID 16
DEBUG: Detected core 6, socket 0, L2 ID 9, L3 ID 0, APICID 18
DEBUG: Detected core 7, socket 0, L2 ID 10, L3 ID 0, APICID 20
DEBUG: Detected core 8, socket 0, L2 ID 11, L3 ID 0, APICID 22
DEBUG: Detected core 9, socket 0, L2 ID 16, L3 ID 0, APICID 32
DEBUG: Detected core 10, socket 0, L2 ID 17, L3 ID 0, APICID 34
DEBUG: Detected core 11, socket 0, L2 ID 18, L3 ID 0, APICID 36
DEBUG: Detected core 12, socket 0, L2 ID 19, L3 ID 0, APICID 38
DEBUG: Detected core 13, socket 0, L2 ID 20, L3 ID 0, APICID 40
DEBUG: Detected core 14, socket 0, L2 ID 24, L3 ID 0, APICID 48
DEBUG: Detected core 15, socket 0, L2 ID 25, L3 ID 0, APICID 50
DEBUG: Detected core 16, socket 0, L2 ID 26, L3 ID 0, APICID 52
DEBUG: Detected core 17, socket 0, L2 ID 27, L3 ID 0, APICID 54
DEBUG: Adding monitoring event: resource ID 1, type 1 to table index 0
DEBUG: Adding monitoring event: resource ID 1, type 4 to table index 1
DEBUG: Adding monitoring event: resource ID 1, type 2 to table index 2
DEBUG: Adding monitoring event: resource ID 1, type 8 to table index 3
DEBUG: Adding monitoring event: resource ID 0, type 32768 to table index 4
DEBUG: Adding monitoring event: resource ID 0, type 16384 to table index 5
INFO: Monitoring capability detected
INFO: CPUID.0x7.0: L3 CAT supported
INFO: L3 CDP is disabled
INFO: L3CA capability detected
INFO: L3 CAT details: CDP support=1, CDP on=0, #COS=16, #ways=11, ways contention bit-mask 0x600
INFO: L3 CAT details: cache size 25952256 bytes, way size 2359296 bytes
INFO: CPUID 0x10.0: L2 CAT not supported!
INFO: L2CA capability not detected
INFO: MBA capability detected
INFO: MBA details: #COS=8, linear, max=90, step=10
DEBUG: allocation init OK
DEBUG: Max RMID per monitoring cluster is 144
DEBUG: monitoring init OK
L3CA/MBA COS definitions for Socket 0:
    L3CA COS0 => MASK 0x7ff
    L3CA COS1 => MASK 0x7ff
    L3CA COS2 => MASK 0x7ff
    L3CA COS3 => MASK 0x7ff
    L3CA COS4 => MASK 0x7ff
    L3CA COS5 => MASK 0x7ff
    L3CA COS6 => MASK 0x7ff
    L3CA COS7 => MASK 0x7ff
    L3CA COS8 => MASK 0x7ff
    L3CA COS9 => MASK 0x7ff
    L3CA COS10 => MASK 0x7ff
    L3CA COS11 => MASK 0x7ff
    L3CA COS12 => MASK 0x7ff
    L3CA COS13 => MASK 0x7ff
    L3CA COS14 => MASK 0x7ff
    L3CA COS15 => MASK 0x7ff

I assume that in default all COS are sharing the same size of L3 cache, size of 0x7ff, so how big is that 0x7ff represent? is 24.75MB/11 ways?

and if I want COS1 only use the minimal cache, how small it can be? some artical says the minimal size that one COS need is 2 ways?

and if I want COS1 can access 2 ways of cache, how should I set it?

pls help me if anybody know this ! really appreciated!

0 Kudos
0 Replies
Reply