i5-8250U 1.6 GHz has a base frequency of 1.8 GHz

[flinc]

I'm measuring the performance of some algorithms and encountered some strange things on my KabyLake i5-8250U CPU.

Windows and Linux detect a (wrong?) base frequency of 1800 MHz. This leads to the effect that the measured performance, e.g. with Cycles/Byte using the TSC, is wrong. LSCPU shows:

Anbieterkennung:     GenuineIntel
Prozessorfamilie:     6
Modell:                    142
Model name:            Intel(R) Core(TM) i5-8250U CPU @ 1.60GHz
Stepping:                 10
CPU MHz:               1800.000
CPU max MHz:        1600,0000
CPU min MHz:         400,0000

I'm wondering if the detected Base Frequency (CPU MHz) of 1800Mhz is a bug or absolutely normal?

[McCalpinJohn]

This processor has a feature called "Configurable TDP-up Frequency", which allows the base frequency (and the corresponding Thermal Design Power) to be shifted up or down (presumably by the BIOS).

You can see these parameters on the product overview page https://ark.intel.com/products/124967/Intel-Core-i5-8250U-Processor-6M-Cache-up-to-3_40-GHz

[TimP]

I don't know about the latest CPUS,  A common situation the past has been that the linux kernel code to find the CPU speed doesn't warm the CPU up sufficiently to avoid inconsistent results due to speed changing during the test.  According to your point of view, you may consider that a bug in the hardware or the kernel, or simply as behavior which you must take into account.

[McCalpinJohn]

It is pretty easy to test the TSC frequency since RDTSC is a user-mode instruction.

On Linux or MacOS, I use a very simple program to see if the TSC is near what I expected:

#include <unistd.h>

unsigned long rdtsc()
{
   unsigned a, d;

   __asm__ volatile("rdtsc" : "=a" (a), "=d" (d));

   return ((unsigned long)a) | (((unsigned long)d) << 32);;
}

int main()
{
	unsigned long tsc_start, tsc_end;

	tsc_start = rdtsc();
	sleep(10);
	tsc_end = rdtsc();
	printf("In approximately 10 seconds, the TSC advanced by %lu\n",tsc_end-tsc_start);
}

[flinc]

Tim, I already added several hundreds iterations of the code before I started the actual measurement.
John, thanks for the code. As expected it shows me a TSC of 18000372612 Hz.

I read that the processor has a "configurable" TDP frequency of 1,8GHz. The problem is that I haven't found a way to configure it so far.
Either setting the TSC down to 1,6 GHz or clocking the CPU up to a fix frequency of 1,8 GHz does not work.

In the end I can live with that fact by multiplying a fix constant to the runtimes.

But am I wrong by concluding that this is not the way it should be? If the base frequency is 1,6 GHz, why should you set the TSC to 1.8?

[McCalpinJohn]

The product description page implies that this processor can be configured as a 10W part at 0.8 GHz, a 15W part at 1.6 GHz, or a 25W part at 1.8 GHz, and your results imply that the invariant TSC ratio is also shifted by this configuration choice.

I am guessing that this is a vendor configuration issue when they design the product, but it is possible that the vendor could allow a user to lower the setting via a BIOS option.  

It would be interesting to see if bits 15:8 of MSR_PLATFORM_INFO (MSR 0xCE) are set to 0x10 (16d = 1.6 GHz) or 0x12 (18d=1.8 GHz), since those bits are supposed to provide the rate at which the TSC increments.   It would be interesting to compare this with the reported frequency from the CPUID brand string and see if Intel has introduced a new inconsistency....

Configurable TDP is not new, and is not particularly confusing, but changing the TSC frequency has the potential for all sorts of confusion -- not least of which is how to describe the !@#&^ processor!   The model name is no longer enough -- you need both the model name and the TDP configuration chosen by the vendor to understand what you are dealing with.

[flinc]

Indeed, the MSR bits are set to 0x12.
The CPUID logfile also states three different TDP Levels (line 90). I attached some files...

Are these MSR bits writeable? Does Intel state somewhere how to change this level? Or is it set by the vendor for once-only until doomsday?

[McCalpinJohn]

The MSR_PLATFORM_INFO register (0xCE) is read-only on every platform that I have checked.

It took some digging, but I finally found the product datasheet at https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-datasheet-vol-1.html

Section 5.1.4 of this document talks about "Configurable TDP" (cTDP) and "Low Power Mode" (LPM).  The important points are:

With cTDP, the processor is now capable of altering the maximum sustained power with an alternate IA core base frequency. [Emphasis mine]

Configurable TDP can be enabled using Intel's DPTF driver or through HW/EC firmware.  Enabling cTDP using the DPTF driver is recommended as Intel does not provide specific application or EC source code.

Either technology [cTDP or LPM] can be triggered by (but are not limited to) changes in OS power policies or hardware events such as docking a system, flipping a switch, or pressing a button.

Bottom line: Intel has just decided to break a ton of software by allowing a processor to change its TSC frequency at will.  I don't know if this processor reports that it has an "invariant" TSC, but whether it claims to have one or not, it seems unlikely that any software that uses the TSC will be prepared for this new behavior.