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Beginner
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Using NVMe-MI command for two P4510 SSDs

1.Reading SN/SMART for Multiple SSDs

Example for NVMe-MI appendix A for read VID and serial number.

Now, I have two P4510 SSD, and try to use SMBus to read some information by NVMe-MI 1.0a Appendix A specification.

 

Following table is data of VID and serial number by NVMe-MI 1.0a Appendix A example 2.

 

only plug SSD1only plug SSD2Plug SSD1&SSD2 on same motherboard

80 86 42 54 4c 4a 37 33 37 32 30 41 50 45 31 50

30 46 47 4e 20 20

80 86 42 54 4c 4a 37 33 37 33 30 30 46 4c 31 50

30 46 47 4e 20 20

80 86 42 54 4c 4a 37 33 37 32 30 00 40 44 31 50

30 46 47 4e 20 20

By SMBus, SSD1 should win bus arbitration at value 0x32 of Byte 0x9.

But in "Plug SSD1+SSD2 on same motherboard" case, the value of Byte 0xb/0xc/0xd are logical and result of SSD1 and SSD2 TX data (that meaning both devices still driving data line).

How can I get correct serial number for two P4510 SSDs?

2. No reaction for NVMe-MI Reset Arbitration

As NVMe-MI 1.0a Appendix A example 3, host sending command to SSD device, SMBus Arbitration bit of Status Flags of Subsystem Management Data Structure should be clear to 0.

And then host send SMBus block read of device's status , but host receive SMBus Arbitration bit is 1 after sending this command.

My platform:

HP F5G73AV Z840

smbus driver:

I2C Tools

訊息由此人編輯:家豪 楊

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11 Replies
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Community Manager
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Hi,

Thank you for posting in the Intel® SSD community.

If I understood you well, you are referring to the examples from the following document (Appendix A | Example 2 & 3): https://nvmexpress.org/wp-content/uploads/NVM_Express_Management_Interface_1_0_gold.pdf https://nvmexpress.org/wp-content/uploads/NVM_Express_Management_Interface_1_0_gold.pdf

Correct me if I'm wrong but if I got it well, you are getting the issue when both SSDs are connected because the output is the result of an AND logical operator between both individual results when each SSD is plug separately, right? Your goal is to read the serial number from both SSDs when both are plugged, correct?

Please let me investigate on this as well as the issue with the reset Arbitration bit.

I'll post an update as soon as possible.

Have a nice day.

Regards,

 

Diego V.
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Beginner
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Thanks for reply!

Correct me if I'm wrong but if I got it well, you are getting the issue when both SSDs are connected because the output is the result of an AND logical operator between both individual results when each SSD is plug separately, right?

Yes. Because SMBus DATA port is wire-and, the device may support SMBus arbitration for connecting multiple devices.

Your goal is to read the serial number from both SSDs when both are plugged, correct?

Yes.Using NVMe-MI 1.0a Appendix A Example 2 method.

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Community Manager
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Hi,

 

 

I've been investigating about what you are trying to accomplish and according to the documentation from the NVMe Technical Note: NVMe Basic Management Command: http://www.nvmexpress.org/wp-content/uploads/NVMe_Management_-_Technical_Note_on_Basic_Management_Co..., it seems that you are following the right path.

 

 

Besides that, our recommendation is to not access the SMBus address within 100msec of device power up as it may experience some glitch on the bus. Please make sure you are following this detail while accessing the bus.

 

 

Regards,

 

Diego V.
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Beginner
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Sure, host acess these SSDs which are stable.

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Community Manager
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Hi,

 

 

As you seem to be using a dual Xeon® processor, one thing that you could try and test is to segment the PCIe lanes in order to connect one SSD on CPU 0 and the other one on CPU 1. Basically, you would be plugging one drive per CPU PCIe lane/slot.

 

 

Additionally, could you please share the exact commands you are using to query the SMBus?

 

 

Regards,

 

Diego V.
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Beginner
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Hi,

Actually, my platform only using one Xeon® processor.

I want to know how can I get any information according to the documentation from the NVMe Technical Note: NVMe Basic Management Command: http://www.nvmexpress.org/wp-content/uploads/NVMe_Management_-_Technical_Note_on_Basic_Management_Co... http://www.nvmexpress.org/wp-content/uploads/NVMe_Management_-_Technical_Note_on_Basic_Management_Co....

The following commands I would use to query the SMBus.

SMBus block read of drive status:

Start D4 00 Start D5

SMBus block read of static data:

Start D4 08 Start D5

SMBus send byte to reset Arbitration bit:

Start D4 FF Stop

I2C read of status and vendor content, I2C allows reading across SMBus block boundaries:

Start D4 00 Start

My question is

1. When I use SMBus block read or I2C read command for pluging two P4510 SSD, I get the output is the result of an AND logical operator.

2. "SMBus send byte to reset Arbitration bit" has no reaction.

I expect that the SMBus Arbitration bit from "Figure 1: Subsystem Management Data Structure" of NVMe Technical Note: NVMe Basic Management Command would be cleared to "0", but in vain.

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Community Manager
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Hi,

Thank you for the clarification.

Please let me investigate on your questions. I'll share here any information I'm able to find about it as soon as possible.

Have a nice day.

Regards,

 

Diego V.

 

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Community Manager
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Hi,

 

 

After investigating about your questions and your platform, we realized that the system you are using (HP Z840 Workstation) doesn't seem to support the Intel® SSD DC P4510 Series. According to the following document, this workstation supports only the Intel® SSD 750 Series: http://www8.hp.com/h20195/v2/GetPDF.aspx/c04400043.pdf

 

 

As we don't see anything wrong with the commands you are using, we recommend you to try and test plugging the drives in different slots to confirm the issue is not because of where the drives are plugged in. However, considering the information from the HP Z840 documentation, we strongly recommend you to contact the OEM (HP in this case) to confirm if these drives are supported or if the only one supported is the Intel® SSD 750 Series: https://support.hp.com/us-en/contact-hp

 

 

I hope you find this information useful.

 

 

Have a nice day.

 

 

Regards,

 

Diego V.
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Beginner
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Hi,

I have used U.2 to PCIE adapter board, and this Workstation can recognize both P4510 SSDs.

I will find another Workstation to try NVMe MI Appendix A.

By the way, does P4510 SSD SMBus interface support device arbitration?

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Community Manager
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Hi,

 

 

The Intel® SSD DC P4510 Series supports the following:
  • NVMe* 1.2b Support
  • Arbitration Mechanism
On the other hand, I'm concerned about the adapter board you are using. Is this some kind of adapter to plug the U.2 drive into a PCIe slot, or is this the U.2 to M.2 hyper kit?

 

 

Regards,

 

Diego V.
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Community Manager
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Hi,

 

 

I would like to know if there is anything else I can help you with.

 

 

I asked you about the adapter because we don't validate these kind of adapters. The only ones that we validate are the Hyper kit and our U.2 to M.2 cable but these options are for U.2 to M.2 only.

 

 

If the one you are using is a U.2 to PCIe adapter, it could be the reason of the issue, although we can't be sure about it as we haven't validated it.

 

 

Regards,

 

Diego V.
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