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03-20-2025
06:23 PM
Hi, all ! I encountered an error while using QUESTA 2024.1 for IP simulation, and I would like to know where the issue lies. Below are the steps I took: 1. generate simulator script set up for i...
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Simulation|Formal Verification
04-09-2025
07:48 AM
I installed Quartus II 24.1 Lite Edition. When using waveform simulator, I found the error: *** Running the ModelSim simulation **** c:/altera_lite/24.1std/questa_fse/win64//vsim -c -do test.do...
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Simulation|Formal Verification
Show results in replies (3)
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...sing the Nativelink simulation flow (only in Quartus Lite/Std edition). You can download the example d...
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Seem like a tool limitation with the Simulation Waveform Editor. Try to run using our Q...
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LM_LICENSE_FILE environment variable is set correctly and I can see the simulation result but the o...
03-20-2025
01:51 AM
A minor bug I think Quartus Prime Pro 24.3 Ran the EDA Simulation Library Compiler for Questa, arria 10 as the selected family Checked both boxes for Verilog and VHDL. Compilation i...
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01-16-2024
11:16 AM
Hello. I'm using this vhdl code to make an 8 bit counter with enable. Quetasim Intel fpga does not increment the counter regularly (defined as variable).
It goes from 'X' to '1' and th...
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Simulation|Formal Verification
Show results in replies (5)
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@GOMEZ_IT, I think you were right, this looks like a simulator problem. I was able to r...
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@GOMEZ_IT wrote: But why if i invert 2 lines of code the simulation works? I'm s...
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...ime the CLK changes so you can only count to 1 with this design, as you see in your original simulation...
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But why if i invert 2 lines of code the simulation works? library IEEE; use IEEE.std_logic_1164...
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...our original simulation. For a counter, you should have a reset mechanism (synchronous or a...
01-18-2024
12:06 AM
Hi, I installed Quartus Prime Lite Edition(23.1) and did synthesis my old design ( By Qualtus II). Synthesis is OK, but I can't start RTL simulation (Questa Intel FPGA) because of following E...
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Simulation|Formal Verification
Show results in replies (7)
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It seem like the quartus complain that they can't find the simulation tool. Have you s...
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...ried to run simulation. I had traced modelsim.tcl file of Quartus-II before, So I noticed "f...
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...standard build 991 Questa Starter: 23.1std.0.991 Could you try to run the quick start simulation...
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...workaround, then you're good to go. Enjoy your simulation! Regards, Richard Tan
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>Could you try to run the quick start simulation flow and see if the issue persist? >h...
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Sorry for my late responce. I tried old (18.1) Quartus version and could do simulation. (a...
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Perhaps this could be a bad installation. Try to uninstall and reinstall both the Quartus and the Q...
02-16-2022
11:42 AM
...m creating a simulation environment based on AN812. AN812 was created for Quartus Pro 17. first I need to upgrade to Quartus 21.3. everything compile smoothly, but the top level module, which is t...
05-04-2023
04:09 AM
Hello i just recently installed the Quartus Prime Lite edition version 22.1.1 and i am trying to use the waveform editor. When i try to run the simulation i get the following error:
&n...
04-24-2024
12:05 AM
...etlists for each partition after performing the Analysis & Synthesis and the Fitter, my goal is to then run a Gate-Level simulation of each of the partitions with the results obtained after c...
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04-25-2024
04:06 AM
Hi all, I'm trying to perform a gate-level functional simulation using a FPGA from the Cyclone V family (I know that gate-level + timing simulations are not suported for this type of FPGA), after c...
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01-11-2025
08:50 AM
...ake any sense, but just to force it to be compiled for now. After creating halfAdder.vhd, I created halfFullAdder.vhd and added it to quartus testbenches list via Assignments->Settings->Simulation...
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Simulation|Formal Verification