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01-16-2024
11:16 AM
Hello. I'm using this vhdl code to make an 8 bit counter with enable. Quetasim Intel fpga does not increment the counter regularly (defined as variable).
It goes from 'X' to '1' and th...
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Simulation|Formal Verification
Show results in replies (5)
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@GOMEZ_IT, I think you were right, this looks like a simulator problem. I was able to r...
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@GOMEZ_IT wrote: But why if i invert 2 lines of code the simulation works? I'm s...
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...ime the CLK changes so you can only count to 1 with this design, as you see in your original simulation...
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But why if i invert 2 lines of code the simulation works? library IEEE; use IEEE.std_logic_1164...
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...our original simulation. For a counter, you should have a reset mechanism (synchronous or a...
01-18-2024
12:06 AM
Hi, I installed Quartus Prime Lite Edition(23.1) and did synthesis my old design ( By Qualtus II). Synthesis is OK, but I can't start RTL simulation (Questa Intel FPGA) because of following E...
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Simulation|Formal Verification
Show results in replies (7)
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It seem like the quartus complain that they can't find the simulation tool. Have you s...
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...ried to run simulation. I had traced modelsim.tcl file of Quartus-II before, So I noticed "f...
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...standard build 991 Questa Starter: 23.1std.0.991 Could you try to run the quick start simulation...
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>Could you try to run the quick start simulation flow and see if the issue persist? >h...
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...workaround, then you're good to go. Enjoy your simulation! Regards, Richard Tan
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Sorry for my late responce. I tried old (18.1) Quartus version and could do simulation. (a...
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Perhaps this could be a bad installation. Try to uninstall and reinstall both the Quartus and the Q...
12-27-2023
07:26 AM
Hello, I am attempting to simulate the Fifo IP using the Questa Starter Edition. I am targeting the Stratix 10 GX. It is imperative that I use Quartus Pro and Questa SE to perform these simulation...
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Simulation|Formal Verification
Show results in replies (3)
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I attached an example simulation with the DCFIFO IP. This is run with different testbench and w...
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The next step in the simulation flow, after you have generated the simulation setup script in Q...
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...unning the simulation for different time intervals so that I wasn’t missing anything but no matter w...
01-01-2024
02:14 PM
I have a problem with simulating schematics in Quartus II 13.1 Web Edition. I've tried to simulate several projects, but every simulation gives me 0s in the outputs. I remember that I accidentally c...
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05-04-2023
04:09 AM
Hello i just recently installed the Quartus Prime Lite edition version 22.1.1 and i am trying to use the waveform editor. When i try to run the simulation i get the following error:
&n...
07-16-2023
11:06 PM
...2 or R3 in their ordering part numbers (OPNs). Does this mean Xcelium is not fully supported for P-Tile or R-Tile Simulations? Will there be a fix in future? Btw. I am running Quartus 23.1 Pro. &n...
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Simulation|Formal Verification
Show results in replies (9)
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...egarding simulation time. My question was regarding simulation time of the provided PIO e...
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Hi Wincent, Finally the simulation exited after almost 14 hours with timeout failure. A...
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Hi Binu, For the PIO design example simulation, by right you shall see "Simulation s...
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.../content/www/us/en/docs/programmable/683544/22-2-6-0-0/simulator-43921.html . Simulation seems t...
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Hi Binu, I check the internal document, by right R-tile with R3 OPN shall able to run simulation...
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Hi Wincent, I was finally able to get the simulation finishing and passing in Quartus 2...
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...ile PCIe IP now. The simulation error is expected. Regards Wincent_Intel
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Hi Wincent, Yes I am aware that I should see "Simulation stopped due to successful c...
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Hi Wincent, Apologies for the delay in responding to your prior follow-up email. ...
02-16-2022
11:42 AM
...m creating a simulation environment based on AN812. AN812 was created for Quartus Pro 17. first I need to upgrade to Quartus 21.3. everything compile smoothly, but the top level module, which is t...
04-27-2023
09:51 PM
Ive been trying to run a simulation on quartus, however I keep getting this error:
I'm not sure what I'm doing that causes this error. My top level compiled without any errors so I d...
04-01-2023
05:33 AM
I am trying to run timing simulation in Questa Sim Intel Starter Edition (Quartus Prime Lite v22.1.1). After fitting, the compilation is correctly done and also the timing simulation is executed w...
12-22-2022
04:13 AM
Hi
I am trying to write and read from on-chip memory using SPI in QSYS. The command goes in correctly by observing MOSI line, but the received values are always 0xXX. My question is that
1. In qu...