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Sethuraman_K_Intel · ‎06-26-2019

Stratix V PCI Express Gen3 x8 PIPE Simulation with Denali Bus Functional Model (BFM) Introduction This article introduces a new solution for the Stratix V PCIe Gen3 x8 32-bit PIPE simulation t...

Altera_Forum · ‎12-03-2009

I use Quartus 9.0 and Arria II GX in my FPGA design. when I generate PCI Express MegaCore function using MegaWizard Plug-In Manager,at the end of the generation there is an i...

Altera_Forum · ‎11-06-2007

Hello, I have a problem to understand how you calculate the DLLPs CRC in the Altera PCI Express Megacore function. I ran the testbench generated and I took the first 4 bytes of some D...

Altera_Forum · ‎08-09-2016

...ew Windows 7 system, it seems to get stuck at "Generating MegaCore function top-level..." as shown in the attachment. Has anyone else run into this issue? Should I be using the SP1 v...

Altera_Forum · ‎07-15-2008

This demo design demonstrates a sample of 2.5Gbps SGMII interface using the Altera Triple Speed Ethernet MegaCore© function with a serial transceiver.

DaeJin · ‎12-19-2024

Dear Manager, I'm using Quartus Prime Lite Editon 18.0.0 version to develop MAX V CPLD. I want set the un-used pin to weak pull-up. Please let me know where can I find the "Quartus...

mitchellr · ‎07-24-2024

Hello, I am looking for junction-to-board and junction-to-case thermal resistance data for the Altera device 5ASXFB3G4F35I3G. Can you provide this? Thank you very much!

ALega1 · ‎02-03-2022

Good morning, I've a design pcie For Arria 10 based on the IP PCIE SRV-IO gen3 x8. I would like to reconfigure the link speed to 5.0g after FPGA configuration. After some research, I've found the r...

Edgar_Gutierrez · ‎02-18-2022

...o make sure they both are exactly the same in the specs or functionality. I have been looking in the datasheet but they do not specify anything related to the "N" suffix. Thank y...

parthb · ‎12-13-2022

Hi Team, We have seen blinking red of D17 (Error LED) in EVM kit, so we don't know what is happening in to working kit. So can you please help us for this? we have already followed step gu...

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Stratix V PCI Express Gen3 x8 PIPE Simulation with Denali Bus Functional Model

Problem generate PCI Express MegaCore function using MegaWizard Plug-In Manager

PCI Express translation

Megawizard stuck at generating MegaCore function...

2.5Gbps of SGMII interface demo using TSE on Stratix II GX PCI Express development ki

Quartus Prime Lite Edition - Setting File Reference Manual && weak pull-up

Altera 5ASXFB3G4F35I3G Thermal Data

PCIE CHANGE SPEED

EP2S60F672C3 (Leaded version) vs EP2S60F672C3N (Lead-Free version)

Arria 10 SX EVM kit Factory Reset

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