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04-17-2024
04:49 AM
Hello, I want to learn how can we reconfigurate my ARRIA10 GX device with external processor. Does ARRIA10 GX supports partial reconfiguration from external processor? Thanks.
- Tags:
- FPGA
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General Usage
Show results in replies (4)
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...-reconfiguration.html
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Yes, @sstrell has helped answered on this. Additional info on Partial Reconfiguration Y...
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...earning.intel.com/Developer/learn/courses/376/partial-reconfiguration-for-intel-fpga-devices-introduction-p...
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...'m trying to achieve the same but I'm a bit confused at following the steps of the Partial Reconfiguration...
06-26-2019
07:05 PM
Stratix V Partial Reconfiguration
Stratix V Partial Reconfiguration Reference Design
This design is targeted at the Stratix V PCIe Development Kit: ( www.altera.com/p...
03-28-2021
04:20 AM
I am interested in PR in Arria 10.
For example, I have 4 same PR regions with 4 same PR personas in each. So can I make 4 PR rbf files somehow, that will i use to reconfig each region separat...
10-03-2024
04:50 PM
...e synthesized into RTL, and placed and routed on the FPGA fabric. If that is the case, can I make VectorAdd a reconfigurable partition, and assign a logic lock region to constraint the PnR of V...
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09-07-2022
02:36 PM
I am comfortable with AMD(Xilinx) Partial Reconfiguration but new to Intel PR. I've found "Static Update Partial Reconfiguration" feature for Intel PR.
But I don't understand how different it is t...
10-08-2021
01:49 PM
I read in the data sheet (https://www.intel.com/content/www/us/en/programmable/documentation/dlq1585950463484.html#version😞 "The Intel ® FPGA PAC N3000-N does not support partial reconfiguration....
04-03-2022
10:06 AM
...ommand "aoc device\vector_add.cl -o bin\vector_add.aocx -board=c5gt -v", the result is:
- Error with partial reconfiguration
- Error: RUn Analysis and synthsis (quartus map) w...
03-10-2024
03:37 PM
Hi, I went over AN 954: Hierarchical Partial Reconfiguration Tutorial. So the example design looks something like below and I understand the flow. What I want to do is s...
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Implementation|Optimization
02-03-2023
07:23 AM
In Partial Reconfiguration flow, I've noticed that when I compile
a Persona Implementation, it generates both the full bitstream(.sof) and
partial bitstreams for all PR partitions(.pmsf a...
03-03-2021
03:30 AM
.....|rx_fifo|auto_generated|wrptr_g1p|counter8a0", in reconfigurable partition "......", is ignored. Initial condition is not guaranteed during partial reconfiguration.
How should I handle this situation?