"FPGA" Posts in "Programmable Devices"

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Delay in SPI-to-Avalon-MM IP Response After MAX10 Reset by chrisssynco Novice in Programmable Devices 08-27-2025 0 1	0	1
PL-USB2-BLASTER Intel FPGA Download Cable II Letter of Volatility (LOV) by ray13 Beginner in Programmable Devices 05-16-2025 0 1	0	1
Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1 by Nicole04 New Contributor I in Programmable Devices 04-17-2025 0 26	0	26
10M04SCU324I7G - Timing files by chris_gonzalez9 Novice in Programmable Devices 03-18-2025 0 5	0	5
Agilex 5 Unused HSIO Banks by Nicole04 New Contributor I in Programmable Devices 03-10-2025 0 3	0	3
Request of Physical Component Dimensions for 5CGXFC7D6F31I7N by ADHISH Beginner in Programmable Devices 01-27-2025 0 3	0	3
Agilex 5 Power Rail LC Filters by Nicole04 New Contributor I in Programmable Devices 01-08-2025 0 6	0	6
Agilex 5 FPGA E-Series Configuration Flash Memory by Nicole04 New Contributor I in Programmable Devices 12-13-2024 0 2	0	2
Agilex 5 HPS UART0 by Nicole04 New Contributor I in Programmable Devices 12-04-2024 0 5	0	5
eMMC version for Agilex 5 FPGA Soc by Nicole04 New Contributor I in Programmable Devices 12-04-2024 0 3	0	3
Maximum external DDR4 memory capacity supported by Agilex 7 M- and I-Series? by RRReed Beginner in Programmable Devices 11-18-2024 0 4	0	4
FPGA/CPLD for military project by Marti3 Beginner in Programmable Devices 10-29-2024 0 3	0	3
Can't boot HPS with Early Release by anonimcs New Contributor III in Programmable Devices 10-13-2024 0 3	0	3
MSL and ESD info by annoyedhuman6969 Novice in Programmable Devices 08-22-2024 0 3	0	3
FPGA Cyclone avaliability by SDatsenko Novice in Programmable Devices 06-06-2024 1 9	1	9
help with signal tap - copy and group by CosmoKramer Employee in Programmable Devices 04-04-2024 0 3	0	3
DE10-Lite LED segment seems broken by asp211 Beginner in Programmable Devices 03-28-2024 0 6	0	6
FPGA Download Cable (1) CE Certificate / Declaration of Conformity by Gertschi Beginner in Programmable Devices 03-04-2024 0 6	0	6
eSPI Agent Core by WFitt Novice in Programmable Devices 02-22-2024 0 8	0	8
Can I synthesize HDL, obtained as a result of DPC++ compilation, in Vivado for Xilinx FPGA? by Vladislav-Butko-bvo New Contributor I in Programmable Devices 01-21-2024 0 6	0	6
Selection a FPGA/CPLD by hexxx Beginner in Programmable Devices 01-08-2024 0 3	0	3
Logic cells vs Byte conversion by anonimcs New Contributor III in Programmable Devices 11-22-2023 0 7	0	7
"Can't recognize silicon ID for device 1" while programming FLASH by CLi19 Beginner in Programmable Devices 11-16-2023 0 4	0	4
FPGA Cyclone10LP by Sooraj Beginner in Programmable Devices 11-15-2023 0 2	0	2
MAX10 UFM Read Operation by SMS Beginner in Programmable Devices 10-26-2023 0 3	0	3