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10M04SCU324I7G - Timing files by chris_gonzalez9 Beginner in Programmable Devices 03-18-2025 0 5	0	5
Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1 by Nicole04 New Contributor I in Programmable Devices 03-18-2025 0 11	0	11
Why my bitstream bring errors by myg Novice in Intel® High Level Design 03-17-2025 0 3	0	3
Agilex 5 Unused HSIO Banks by Nicole04 New Contributor I in Programmable Devices 03-10-2025 0 3	0	3
Agilex 5 E-Series FPGA Triple Speed Ethernet SGMII with PHY Management by Nicole04 New Contributor I in FPGA Intellectual Property 02-28-2025 0 4	0	4
E810CQDA1 - configuration connect to FPGA by kikoss New Contributor II in Ethernet Products 02-27-2025 0 7	0	7
Cyclone 10 GX Nios V: TSE with mSGDMA Not Responding to Ping by Paul36 Beginner in Nios® V/II Embedded Design Suite (EDS) 02-23-2025 0 14	0	14
Error: Can't Open project -- Quartus II 6.0 by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 02-21-2025 1 12	1	12
Signal tap doesnt recognise most of the entities of my bdf file. Compilation doesn't fit too by PedroJServian Novice in Intel® Quartus® Prime Software 02-21-2025 0 5	0	5
Inquiry About Example GTS HDMI IP Block Design by Muratalkan Beginner in FPGA, SoC, And CPLD Boards And Kits 02-13-2025 0 3	0	3
Getting floating license by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 02-12-2025 0 13	0	13
Request of Physical Component Dimensions for 5CGXFC7D6F31I7N by ADHISH Beginner in Programmable Devices 01-27-2025 0 3	0	3
DE2 115 BOOT PROGRAM by Mun1 Beginner in FPGA, SoC, And CPLD Boards And Kits 01-19-2025 0 5	0	5
Error from the tutorial of Generating and Compiling Cyclone V Preloader by SONG Beginner in Nios® V/II Embedded Design Suite (EDS) 01-14-2025 0 6	0	6
Quartus Lite 'No paths found' by Baller Novice in Intel® Quartus® Prime Software 01-13-2025 0 7	0	7
Signal Tap - Instance not found by jlats2 New Contributor I in Intel® Quartus® Prime Software 01-10-2025 0 8	0	8
How to resolve the error 'modelsim (vsim) is not on the path'? by ZikunTan Beginner in Nios® V/II Embedded Design Suite (EDS) 01-09-2025 0 4	0	4
Agilex 5 Power Rail LC Filters by Nicole04 New Contributor I in Programmable Devices 01-08-2025 0 6	0	6
OFS : Data Path of QSFP from HE_HSSI by attdoner Novice in Application Acceleration With FPGAs 12-29-2024 1 44	1	44
Problem with the clock of the 10M08SCE144 by PedroJServian Novice in FPGA, SoC, And CPLD Boards And Kits 12-24-2024 0 5	0	5
Robust Full-Lifecycle Security with Altera FPGAs by SethReinhart Employee in FPGA 12-20-2024 2 0	2	0
Quantus II Programmer Auto Detect Problem with DE1-SoC by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 12-16-2024 0 6	0	6
Agilex 5 FPGA E-Series Configuration Flash Memory by Nicole04 New Contributor I in Programmable Devices 12-13-2024 0 2	0	2
Agilex 5 HPS UART0 by Nicole04 New Contributor I in Programmable Devices 12-04-2024 0 5	0	5
eMMC version for Agilex 5 FPGA Soc by Nicole04 New Contributor I in Programmable Devices 12-04-2024 0 3	0	3