Tag: "Programmable Devices"

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SAP accelerates compression workload in POC with Intel® OFS by Tamara_Lin Employee in FPGA 12-05-2022 0 0	0	0
Need more infomation about intel MAP accelerator card by LilySpark Novice in Programmable Devices 09-01-2022 0 7	0	7
Transfer 2.4 Tbps (or 4.32 Tbps) with One Intel® Agilex™ FPGA by Kevin_Zhang Employee in FPGA 07-22-2022 1 0	1	0
Video Demo: Designing Broadcast Video Equipment Using SDI by Kevin_Zhang Employee in FPGA 07-20-2022 1 0	1	0
ServeTheHome’s Editor in Chief Visits Intel Networking Lab and Groks FPGA-Based IPUs by Sabrina_Gomez Employee in FPGA 06-30-2022 0 0	0	0
descriptors for Ethernet Media Access Controller Initialization by Altera_Forum Honored Contributor II in Ethernet Products 06-14-2022 1 2	1	2
DE2 Ethernet communication by Altera_Forum Honored Contributor II in Ethernet Products 04-23-2022 0 2	0	2
Flash Loader IP not loaded on device 1? by FN0001 Beginner in FPGA, SoC, And CPLD Boards And Kits 07-19-2021 0 7	0	7
Prerequisites for creating 10G BASE-R Transceiver by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 09-22-2020 0 1	0	1
Error when I run vector-add example on FPGA OpenCL. ERROR: Unable to find Intel(R) FPGA OpenCL platform. by anaza3 Novice in Application Acceleration With FPGAs 08-03-2020 0 3	0	3
Letter of Volatility for Altera USB-Blaster by HDavi9 Beginner in Processors 02-18-2020 0 1	0	1
I have recently downloaded the Quartus Prime 18.1 (Lite edition) and the Cyclone devices individually. But when I try to open the 3 individual files with the Cyclone devices they will not open and the software wont let me create a new project. by JStew26 Beginner in Intel® Quartus® Prime Software 01-30-2020 0 2	0	2
QuestaSim and CycloneV PLL:flat output by 明张0002 Beginner in Intel® Quartus® Prime Software 11-22-2019 0 1	0	1
Arria 10 SerialLite II Design Example v19.1std by SengKok_L_Intel Moderator in FPGA Wiki 10-31-2019 0 0	0	0
When I'm in the programming window and trying to pass the pof file to MAX I get the following error "Cannot add target device EPCQL1024 to device chain when in current programming mode" how should I proceed? What would be the other way to programming MAX? by SATC New Contributor I in FPGA, SoC, And CPLD Boards And Kits 10-26-2019 0 5	0	5
Simple NIOS Max 10 ethernet by Altera_Forum Honored Contributor II in Ethernet Products 09-26-2019 0 2	0	2
Understanding Avalon-MM master in HLS generated code. by RBash Novice in Intel® High Level Design 08-23-2019 0 6	0	6
Continuos Data transfer from HPS to QuartusDCFIFO by ASuba Novice in Intel® SoC FPGA Embedded Development Suite 08-22-2019 0 3	0	3
Problem configuring Cyclone 10 LP in Passive Serial mode by Mikel Beginner in FPGA, SoC, And CPLD Boards And Kits 07-23-2019 0 5	0	5
SDI II IP - TX sync Issue by AlexR Beginner in FPGA Intellectual Property 07-22-2019 0 7	0	7
Soft LVDS IP core bitslip by SMS Beginner in FPGA Intellectual Property 07-19-2019 0 3	0	3
Repetitive programming when using .pof file by SMS Beginner in FPGA, SoC, And CPLD Boards And Kits 07-18-2019 0 2	0	2
How do I connect Verilog modules I created with ARM processor (HPS) of Cyclone V SOC ? by NShin5 Beginner in FPGA Intellectual Property 06-28-2019 0 1	0	1
How to convert Cyclone III Verilog files to Cyclone V? by AAjit2 New Contributor I in FPGA, SoC, And CPLD Boards And Kits 05-06-2019 0 1	0	1
Generation of STP file for SignalTap by KAkyo Beginner in Intel® Quartus® Prime Software 12-17-2018 0 2	0	2