Tag: "de1-soc"

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Cannot read/write interval timer register DE1-SoC HPS by Red2503 Beginner in Intel® FPGA University Program 02-10-2021 0 2	0	2
file io with NIOS II by euem789 Novice in Nios® V/II Embedded Design Suite (EDS) 08-07-2020 0 14	0	14
[Cyclone V SoC] Trouble implementing FPGA-to-HPS Bridges Design Example (Intel Design Example) by Altera_Customer Beginner in Programmable Devices 06-27-2020 0 1	0	1
I am trying to modify and compile the De1-SoC Computer System that Intel has created, however I am getting this error when I compile my system. This error appears both on the original Computer System and the one I modified. Any help? by NRoba Beginner in Intel® Quartus® Prime Software 06-02-2020 0 2	0	2
When I try to make file the following error was generated, so I solve it? I attached the screenshot as below. by GTese New Contributor I in Items with no label 05-07-2020 0 0	0	0
Audio Player project using Python and GPIO by jawsh Beginner in Items with no label 02-04-2020 0 0	0	0
De1-SoC: Running bare-metal from SD Card by AJama4 Beginner in FPGA, SoC, And CPLD Boards And Kits 12-13-2019 0 4	0	4
How to write to DDR of a DE1-SoC using the ARM processor? by hcruz1 Beginner in FPGA, SoC, And CPLD Boards And Kits 12-11-2019 0 5	0	5
Clear explaination about system interconnect fabric by Altera_Forum Honored Contributor II in Programmable Devices 06-27-2019 1 2	1	2
I meet some problems with VGA display using DE1SOC by ygao15 Beginner in Programmable Devices 03-29-2019 0 3	0	3
Accessing DDR-Ram from FPGA on DE1-SoC -- without an OS by isonedak Beginner in FPGA, SoC, And CPLD Boards And Kits 03-11-2019 0 1	0	1
DE1-SoC MSEL [00000] or [01110] Unable to program FPGA from HPS by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 12-17-2018 0 4	0	4
Cyclone V, DE1-SOC GPIO Header Pinout Diagram by Altera_Forum Honored Contributor II in Programmable Devices 11-13-2018 0 5	0	5
Where are the altera_up_avalon_adc.h and altera_up_avalon_parallel_port.h header files located? by dpavl2 Beginner in Intel® Quartus® Prime Software 10-10-2018 0 2	0	2
DE1-SoC - Cyclone V HPS fallback boot from FPGA by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 09-24-2018 0 4	0	4
confusing of device tree blob by Altera_Forum Honored Contributor II in Programmable Devices 09-18-2018 0 2	0	2
DE1-SOC ethernet project. (please HELP!) by Altera_Forum Honored Contributor II in Ethernet Products 07-20-2018 0 1	0	1
Any explanation of APPLYCFG bit of SDRAM control register in Cylcone V by Altera_Forum Honored Contributor II in Programmable Devices 07-02-2018 0 1	0	1
DE1-SoC audio playback from SD card by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 05-04-2018 0 1	0	1
How to transfer data array between HSP-FPGA & vice versa in CycloneV Soc (De1Soc)? by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 05-04-2018 0 4	0	4
Rocket Board Yocto Repos Out of Date? by Altera_Forum Honored Contributor II in FPGA, SoC, And CPLD Boards And Kits 03-07-2018 0 0	0	0
GLIBC incompatibility by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 01-04-2018 0 4	0	4
OpenCL directly in DE1-SOC with Linux Ubuntu by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 12-02-2017 0 4	0	4
DE1-SOC power button non-functioning in AS/EPCS mode by Altera_Forum Honored Contributor II in Programmable Devices 08-31-2017 0 0	0	0
D5M not working with DE1-SoC by Altera_Forum Honored Contributor II in Programmable Devices 08-17-2017 0 5	0	5