Tag: "gpio"

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NativeLink RTL-Simulation fails after Fitter-Run if project includes two variations of GPIO Lite IP by ugro Beginner in Intel® Quartus® Prime Software 04-23-2024 0 4	0	4
Inquiries regarding 10M08 Evaluation Kit FPGA by CircuitMaster Novice in FPGA, SoC, And CPLD Boards And Kits 11-21-2023 0 1	0	1
DE10-Lite GPIO by nilsbuc Novice in Programmable Devices 10-29-2023 0 2	0	2
Regarding the Intel Agilex series GPIO Banks IO standards by Maitry Novice in FPGA, SoC, And CPLD Boards And Kits 07-17-2023 0 4	0	4
How to migrate source-synchronous GPIO to Intel PHY Lite IP? by hcom New Contributor II in FPGA Intellectual Property 04-13-2022 0 8	0	8
Intel MAX10 LVCMOS and LVTTL Drive strength limitations by Oyvine Novice in Programmable Devices 03-14-2021 0 5	0	5
Using external clock to drive FPGA DE10-Nano by Syouf Novice in FPGA, SoC, And CPLD Boards And Kits 01-26-2021 0 17	0	17
What is the state of Max 10 GPIO during power-up? by wdecook Beginner in Programmable Devices 08-24-2020 0 1	0	1
MAX II device: outputs turning off by HBaet Beginner in Items with no label 02-26-2020 0 0	0	0
How to add pull-ups on DE10-nano GPIO by jackhab New Contributor I in FPGA, SoC, And CPLD Boards And Kits 12-25-2019 1 25	1	25
I want to access i2c based devices how can I access that device.I am new to X86 on ARM we have device tree to access hardware information like that what is procedure for x86.We can access at UEFI level or we can access at Kernel level. by vvard1 Beginner in Embedded Intel® Core™ Processors 12-27-2018 0 3	0	3
What is ASL files ? Using ASL files we can access Hardware devices ? Give me examples for writing ASL files. by vvard1 Beginner in Embedded Intel Atom® Processors 12-26-2018 0 1	0	1
Include Header not found in the project: Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU by Altera_Forum Honored Contributor II in Programmable Devices 06-13-2018 0 0	0	0
Configuration and initialization of HPS - I/O in Cyclone V by Altera_Forum Honored Contributor II in Programmable Devices 06-12-2018 0 4	0	4
Wrong Timeout Value with ARM A9 private timer. by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 06-04-2018 0 0	0	0
The HPS GPIO registers are unavailable by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 06-04-2018 0 0	0	0
Data transfer using buffer with (HPS--bridge--FPGA) by Altera_Forum Honored Contributor II in FPGA, SoC, And CPLD Boards And Kits 03-13-2018 0 2	0	2
Combining pins to source / sink more current by Altera_Forum Honored Contributor II in Programmable Devices 02-08-2018 0 2	0	2
Can not simulate MAX10 with Differential IO buffers (quartus prime) by Altera_Forum Honored Contributor II in Programmable Devices 01-31-2018 0 2	0	2
Arria 10 SoC GPIO's by Altera_Forum Honored Contributor II in FPGA, SoC, And CPLD Boards And Kits 01-11-2018 0 0	0	0
PID controller implementation help needed by Altera_Forum Honored Contributor II in Intel® FPGA University Program 12-10-2017 0 1	0	1
GPIO voltage frequency does not match PLL clock output by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 07-06-2017 0 0	0	0
Set GPIO pins with multiple voltage levels by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 07-04-2017 0 5	0	5
De0-nano trace length matched by Altera_Forum Honored Contributor II in FPGA, SoC, And CPLD Boards And Kits 07-04-2017 0 1	0	1
ltspice for gpio pin by Altera_Forum Honored Contributor II in FPGA, SoC, And CPLD Boards And Kits 05-27-2017 0 2	0	2