Tag: "qsys"

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Problem with AXI Timeout Bridge by Altera_Forum Honored Contributor II in Programmable Devices 03-27-2024 0 1	0	1
Compile a design from a copy of its qsys by anonimcs New Contributor I in Programmable Devices 10-10-2023 0 1	0	1
Migration Error: Unable to Open data_pattern_generator Service in Quartus Prime Standard Edition by DeadEnd New Contributor I in Intel® Quartus® Prime Software 07-02-2023 0 4	0	4
Problem with parameters when instantiating custom build component by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 03-31-2023 0 8	0	8
Problems using a Dual access on-chip memory module (QSYS) by MartBent Novice in Programmable Devices 10-30-2022 0 11	0	11
SPI-to-Avalon-Bridge answers always IDLE by Jo910 Beginner in FPGA Intellectual Property 07-29-2021 0 3	0	3
IP_Compiler for PCI Express fails to Generate (Cyclone IV GX, Qsys 17.0) by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 04-27-2021 1 4	1	4
Customize DSPBuilder-generated custom component in Qsys/Platform designer by Ghe0rghe New Contributor I in FPGA Intellectual Property 01-12-2021 0 10	0	10
Platform designer interconnect: unexpected behavior by Schroeti New Contributor I in Intel® Quartus® Prime Software 11-17-2020 0 8	0	8
missing files in quartus\libraries\megafunctions by Chris2000 Novice in Programmable Devices 11-16-2020 0 2	0	2
Can the swinfo2header be used to get names of all modules with their master port names? by gyuunyuu New Contributor II in Intel® Quartus® Prime Software 11-10-2020 0 1	0	1
Quartus II Fitter error in connecting the output of IOPLL to refclk of ATX PLL by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 10-27-2020 1 4	1	4
AXI - Avalon Error in Qsys/Platform Designer by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 10-12-2020 0 2	0	2
Custom Neural Network on DE10-Nano by Altera_Forum Honored Contributor II in Programmable Devices 09-17-2020 0 2	0	2
Error in autogenerated files from Qsys by MichaelB New Contributor I in FPGA Intellectual Property 09-08-2020 0 4	0	4
Is there a standard way to extract the base addresses in sopc info file into a VHDL file? by gyuunyuu New Contributor II in Intel® Quartus® Prime Software 08-11-2020 0 5	0	5
Async FIFO size in AVMM interconnect by fvult Beginner in Programmable Devices 08-10-2020 0 8	0	8
Avalon Dual-Master Bus with constant waitrequest on connection point by MKlee2 New Contributor I in FPGA Intellectual Property 07-16-2020 0 3	0	3
MAX10 dual boot, NIOS2 boot from UFM. Not booting. by Altera_Forum Honored Contributor II in Programmable Devices 07-10-2020 0 2	0	2
Avalon-MM Arria V Hard IP for PCI Express Intel FPGA IP: waitrequest high by fvult Beginner in Programmable Devices 06-04-2020 0 7	0	7
Avalon to external bus bridge - Accessing 8Bit with 32Bit commands by SDost Beginner in FPGA Intellectual Property 05-11-2020 0 1	0	1
Deciding where to place/how many avalon-mm pipeline bridges to use? by MKlee2 New Contributor I in Items with no label 03-24-2020 0 0	0	0
Arria 10 HPS: Platform Designer Error: Unsupported Device under Linux (Windows works) by KSchi Beginner in FPGA, SoC, And CPLD Boards And Kits 03-17-2020 0 10	0	10
DDR3 UniPHY master/slave by EBoln New Contributor I in FPGA Intellectual Property 03-06-2020 0 3	0	3
[Qsys] LPDDR2 Controller (UniPHY): HDL generation fails. by Altera_Forum Honored Contributor II in Intel® Quartus® Prime Software 01-22-2020 0 10	0	10