"soc" Posts in "Nios® II Embedded Design Suite (EDS)"

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Nios® II Embedded Design Suite (EDS)
"soc" Posts in "Nios® II Embedded Design Suite (EDS)"

12488 Discussions

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>30% CPU load increase with USB FLash plugged in (lots of SOF interrupts) by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 10-04-2022 0 2	0	2
SPI from HPS through FPGA not working by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 09-28-2022 0 6	0	6
Error: Can't Open project -- Quartus II 6.0 by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 01-06-2022 0 8	0	8
TCP KEEP_ALIVE by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 12-06-2021 0 3	0	3
Fail to generate a boot loader with QSPI Flash by GSite Novice in Nios® II Embedded Design Suite (EDS) 10-05-2021 1 6	1	6
Interrupts using the ARM core and the GIC by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 08-10-2021 0 3	0	3
stand-alone lwip ARP problem by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 06-16-2021 0 1	0	1
Interrupt handling problem using linux with DE1_SoC cyclone V by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 05-12-2021 0 1	0	1
Setting up TrustZone on Cyclone V FPGA board by ADavi10 Beginner in Nios® II Embedded Design Suite (EDS) 04-30-2021 0 2	0	2
ALTPLL Megawizard crashes by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 04-16-2021 0 20	0	20
something wrong with my ALTLVDS_RX, ALTLVDS_TX and DDR3 controller by WMing Beginner in Nios® II Embedded Design Suite (EDS) 04-01-2021 0 2	0	2
Implementing UPnP by jwill24 Beginner in Nios® II Embedded Design Suite (EDS) 03-15-2021 0 2	0	2
cache not enable by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 03-07-2021 0 3	0	3
looking for Multiprocessor_Tutorial.zip for QuartusII 9.1 Download Link by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 02-05-2021 0 1	0	1
Use Qsys subsystem generate bsp error by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 11-10-2020 0 1	0	1
preloader can not be generated by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 09-24-2020 0 1	0	1
Auto-Negotiation FAILED by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 09-16-2020 0 15	0	15
Error from the tutorial of Generating and Compiling Cyclone V Preloader by SONG Beginner in Nios® II Embedded Design Suite (EDS) 09-15-2020 0 5	0	5
Programming FPGA from HPS using QSPI by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 09-03-2020 0 3	0	3
mSGDMA transfer from DDR3 using FPGA2HPS-SDRAM interface by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 08-14-2020 0 4	0	4
file io with NIOS II by euem789 Novice in Nios® II Embedded Design Suite (EDS) 08-07-2020 0 14	0	14
Receive LVDS signals with FPGA by WMing Beginner in Nios® II Embedded Design Suite (EDS) 08-07-2020 0 4	0	4
Cyclone V SPI master releases chip select when TX FIFO runs empty. HOW TO PREVENT??? by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 07-29-2020 0 10	0	10
ARM DS-5 and DE10-Nano by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 07-29-2020 0 11	0	11
Error deleting long path file name. Please help by Altera_Forum Honored Contributor II in Nios® II Embedded Design Suite (EDS) 07-02-2020 0 3	0	3