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XG_Kang
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About XG_Kang
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Posted
Does repeater/retimer be need when Arria10 GX FPGA used in backplane application?
on
FPGA Intellectual Property
.
02-01-2021
07:12 PM
Posted
Does repeater/retimer be need when Arria10 GX FPGA used in backplane application?
on
Programmable Devices
.
02-01-2021
06:37 PM
Kudoed
Re:how do data in rpd file map into configuration flash with arria10
for JohnT_Intel.
12-07-2020
09:41 PM
Posted
回复： Re:how do data in rpd file map into configuration flash with arria10
on
Programmable Devices
.
12-07-2020
07:41 PM
Posted
how do data in rpd file map into configuration flash with arria10
on
Programmable Devices
.
12-06-2020
05:58 PM
Kudoed
Re:why pcie_tx_st_ready keep low for almost 16384 ...
for BoonT_Intel.
12-06-2020
05:44 PM
Posted
why pcie_tx_st_ready keep low for almost 16384 pcie_clk
on
FPGA Intellectual Property
.
08-02-2020
07:53 PM
Posted
Re: how to use GPIOs in ddr3l bank
on
FPGA, SoC, And CPLD Boards And Kits
.
07-20-2020
06:56 PM
Posted
how to use GPIOs in ddr3l bank
on
FPGA, SoC, And CPLD Boards And Kits
.
07-16-2020
11:16 PM
Posted
Re: What would happen if VCCPD and VCCIO were delayed tens of minutes to power up after VCC was powered up already for 5CEA9 device?
on
FPGA, SoC, And CPLD Boards And Kits
.
12-17-2019
06:16 AM
Posted
Re: What would happen if VCCPD and VCCIO were delayed tens of minutes to power up after VCC was powered up already for 5CEA9 device?
on
FPGA, SoC, And CPLD Boards And Kits
.
12-17-2019
06:13 AM
Posted
What would happen if VCCPD and VCCIO were delayed tens of minutes to power up after VCC was powered up already for 5CEA9 device?
on
FPGA, SoC, And CPLD Boards And Kits
.
12-16-2019
10:20 AM
Posted
Can EPCQL256 be used as configuration device for 5CEFA9?
on
FPGA, SoC, And CPLD Boards And Kits
.
12-04-2019
06:27 AM
Posted
Re: How to assign LVDS in 1.8V bank in Cyclone VE
on
FPGA, SoC, And CPLD Boards And Kits
.
11-22-2019
09:59 AM
Posted
How to assign LVDS in 1.8V bank in Cyclone VE
on
FPGA, SoC, And CPLD Boards And Kits
.
11-21-2019
06:49 AM
Posted
Re: Fitter Error
on
Intel® Quartus® Prime Software
.
11-08-2019
01:00 AM
Posted
Re: Quartus Prime 17.1 cann't program the JIC file of 4CE75 correctly when an 10AX057 and an EP4CE75 both in the same JTAG chain. The "Factory default enhanced SFL image" of Quartus Prime 17.1 may have some bugs in this situation.
on
FPGA Intellectual Property
.
11-08-2019
12:51 AM
Posted
Quartus Prime 17.1 cann't program the JIC file of 4CE75 correctly when an 10AX057 and an EP4CE75 both in the same JTAG chain. The "Factory default enhanced SFL image" of Quartus Prime 17.1 may have some bugs in this situation.
on
FPGA Intellectual Property
.
11-06-2019
01:57 AM
Posted
Re: Fitter Error
on
Intel® Quartus® Prime Software
.
10-09-2019
01:04 AM
Posted
Re: Fitter Error
on
Intel® Quartus® Prime Software
.
10-08-2019
02:46 AM
Latest posts by XG_Kang
Subject
Views
Posted
Does repeater/retimer be need when Arria10 GX FPGA used in backplane application?
FPGA Intellectual Property
59
02-01-2021
07:12 PM
Does repeater/retimer be need when Arria10 GX FPGA used in backplane application?
Programmable Devices
71
02-01-2021
06:37 PM
回复： Re:how do data in rpd file map into configuration flash with arria10
Programmable Devices
92
12-07-2020
07:41 PM
how do data in rpd file map into configuration flash with arria10
Programmable Devices
112
12-06-2020
05:58 PM
why pcie_tx_st_ready keep low for almost 16384 pcie_clk
FPGA Intellectual Property
102
08-02-2020
07:53 PM
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Member Since
08-21-2018
