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30-07-2020
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Re: [RSU] Can't establish UART connection to perform remote system update on MAX10
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06-23-2020
01:23 AM
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Re: Niosを用い、EPCS Flash Controller のようにMicronのMT25Q を読み書きすることは可能ですか？ デバイスはCyclone 10 LPです。
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06-23-2020
01:23 AM
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Re: How to run "Convert Programming File" with a TCL file?
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06-23-2020
01:22 AM
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Re: Can I program active serial device other than Altera's one using Quartus (programmer) through cable?
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06-23-2020
01:22 AM
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Re: Can I program active serial device other than Altera's one using Quartus (programmer) through cable?
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06-23-2020
01:22 AM
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Re: From different documents I found that a X710DA2 Adapter with two 10G ports supports 10Gbps of bandwidth per port. But my query is - If I use the two ports simultaneously, would I get 10G+10G bandwidth at a time?
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06-23-2020
01:22 AM
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Re: Using Serial Flash Loader IP and ASMI Parallel II IP (Error (176286): Found 2 SPI blocks in design ...)
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06-23-2020
01:22 AM
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Re: Cyclone IV memory config
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06-23-2020
01:22 AM
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Re: ASMI Parallel II elaboration error
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06-23-2020
01:22 AM
Got a Kudo for
Re: ASMI Parallel II elaboration error
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06-23-2020
01:22 AM
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Re: Remote re-configure a Cyclone IV in Application-mode?
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06-23-2020
01:22 AM
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Re: Altera Generic QUAD SPI controller - alternative flash memory
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06-23-2020
01:22 AM
Posted
Re: FPGA development kit problem
on
FPGA, SoC, And CPLD Boards And Kits
.
02-01-2019
10:20 AM
Posted
Re: PAC Arria 10 GX, reconfiguration not working on 1.2PV
on
Application Acceleration With FPGAs
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01-28-2019
05:57 AM
Posted
Re: lspci while running DMA traffic crashes linux server
on
FPGA Intellectual Property
.
01-28-2019
05:57 AM
Posted
Re: We need to keep the overall latency from FPGA request to memory device and back to FPGA at a minimum. We have come across a situation that a 1SG280HU2F50E2VGS1 device works and a 1SM21BHU2F53E2VGS1 device does not.
on
Programmable Devices
.
01-28-2019
05:55 AM
Posted
Re: "CONF_DONE pin failed to go high in device 1" - Arria 10 FPGA Dev Kit
on
FPGA, SoC, And CPLD Boards And Kits
.
01-28-2019
01:59 AM
Posted
Re: Can I read and write buffers simultaneously with OpenCL.
on
Application Acceleration With FPGAs
.
01-22-2019
01:15 AM
Posted
Re: Can you use the non-volatile key from the FPGA (Cyclone V) in a design?
on
Programmable Devices
.
01-17-2019
03:07 AM
Posted
Re: Can you use the non-volatile key from the FPGA (Cyclone V) in a design?
on
Programmable Devices
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01-16-2019
01:28 PM
Latest posts by Nooraini_Y_Intel
Subject
Views
Posted
Re: FPGA development kit problem
FPGA, SoC, And CPLD Boards And Kits
5
02-01-2019
10:20 AM
Re: PAC Arria 10 GX, reconfiguration not working on 1.2PV
Application Acceleration With FPGAs
9
01-28-2019
05:57 AM
Re: lspci while running DMA traffic crashes linux server
FPGA Intellectual Property
4
01-28-2019
05:57 AM
Re: We need to keep the overall latency from FPGA request to memory device and back to FPGA at a minimum. We have come across a situation that a 1SG28...
Programmable Devices
2
01-28-2019
05:55 AM
Re: "CONF_DONE pin failed to go high in device 1" - Arria 10 FPGA Dev Kit
FPGA, SoC, And CPLD Boards And Kits
15
01-28-2019
01:59 AM
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Member Since
07-27-2018
