/home/admin/otc/ofs-bmc/scripts 2024-04-03 13:38:29 :: Check availability of necessary tools: 2024-04-03 13:38:29 :: Tool: unzip 2024-04-03 13:38:29 :: Tool: zip 2024-04-03 13:38:29 :: Tool: tclsh 2024-04-03 13:38:29 :: Tool: srec_cat 2024-04-03 13:38:29 :: Setting Quartus environment 2024-04-03 13:38:30 :: Printing env on build machine ... : eval ${which_declare} ) | /usr/bin/which --tty-only --read-alias --read-functions --show-tilde --show-dot $@ : ALTERAD_LICENSE_FILE= : AWK_CMD=awk : BASH_FUNC_which%%=() { ( alias; : CMD_NAME=build.sh : COLORTERM=truecolor : DBUS_SESSION_BUS_ADDRESS=unix:path=/run/user/1000/bus,guid=377dc7b557ddba147c0b0e25660c3c3d : DBUS_STARTER_ADDRESS=unix:path=/run/user/1000/bus,guid=377dc7b557ddba147c0b0e25660c3c3d : DBUS_STARTER_BUS_TYPE=session : DESKTOP_SESSION=gnome : DISPLAY=:0 : GDMSESSION=gnome : GDM_LANG=en_IN.UTF-8 : GNOME_DESKTOP_SESSION_ID=this-is-deprecated : GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/3872e9d0_95d3_4cf1_bfb8_2da4f142427a : GNOME_TERMINAL_SERVICE=:1.77 : GUESTFISH_INIT=\e[1;34m : GUESTFISH_OUTPUT=\e[0m : GUESTFISH_PS1=\[\e[1;32m\]>\[\e[0;31m\] : GUESTFISH_RESTORE=\e[0m : HISTCONTROL=ignoredups : HISTSIZE=1000 : HOME=/home/admin : HOSTNAME=localhost.localdomain : INTELFPGAOCLSDKROOT=/home/admin/Complete/hld : INTEL_KEYS_DIR= : INVOCATION_ID=7d4f13ff48c04f8babd2bc6601ac2a0e : JOURNAL_STREAM=9:55731 : LANG=C : LC_CTYPE=en_US : LD_LIBRARY_PATH=/home/admin/Complete/quartus/linux64 : LESSOPEN=||/usr/bin/lesspipe.sh %s : LOGNAME=admin : LS_COLORS=rs=0:di=38;5;33:ln=38;5;51:mh=00:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=01;05;37;41:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;40:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.zst=38;5;9:*.tzst=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.wim=38;5;9:*.swm=38;5;9:*.dwm=38;5;9:*.esd=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.mjpg=38;5;13:*.mjpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.m4a=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.oga=38;5;45:*.opus=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: : MAIL=/var/spool/mail/admin : MANAGERPID=2784 : OLDPWD=/home/admin/otc/ofs-bmc : OUTPUT_DIR_NAME=build : PATCH_CMD= : PATH=/home/admin/Complete/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin:/home/admin/Complete/nios2eds/sdk2/bin:/home/admin/Complete/nios2eds/bin:/home/admin/Complete/quartus/adm:/home/admin/Complete/quartus/linux64:/home/admin/.local/bin:/home/admin/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/var/lib/snapd/snap/bin : PLATFORM=Arrow_Creek : PROJECT_NAME=Arrow_Creek_BMC : PWD=/home/admin/otc/ofs-bmc/scripts : QENV_STATUS=0 : QSYS_ROOTDIR=/home/admin/Complete/quartus/sopc_builder/bin : QT_IM_MODULE=ibus : QUARTUS_BINDIR=/home/admin/Complete/quartus/linux64 : QUARTUS_BIT_TYPE=64 : QUARTUS_HOME=/home/admin/Complete : QUARTUS_ORIG_PATH=/home/admin/.local/bin:/home/admin/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/var/lib/snapd/snap/bin : QUARTUS_PLATFORM=linux : QUARTUS_QENV=1 : QUARTUS_ROOTDIR=/home/admin/Complete/quartus : QUARTUS_VER=23.1std : REVISION_CODES_DIR=/home/admin/otc/ofs-bmc/scripts/revision-codes : SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/2864,unix/unix:/tmp/.ICE-unix/2864 : SHELL=/bin/bash : SHLVL=3 : SOPC_KIT_NIOS2=/home/admin/Complete/nios2eds : SSH_ASKPASS=/usr/libexec/openssh/gnome-ssh-askpass : SSH_AUTH_SOCK=/run/user/1000/keyring/ssh : TERM=xterm-256color : TMP=/tmp : UNAME_REVISION=4.18.0-372.9.1.el8.x86_64 : UNAME_SYSTEM=Linux : UNAME_VERSION=#1 SMP Fri Apr 15 22:12:19 EDT 2022 : USER=admin : USERNAME=admin : VTE_VERSION=5204 : WAYLAND_DISPLAY=wayland-0 : XAUTHORITY=/run/user/1000/.mutter-Xwaylandauth.LPZ8K2 : XDG_CURRENT_DESKTOP=GNOME : XDG_DATA_DIRS=/home/admin/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share/:/usr/share/:/var/lib/snapd/desktop : XDG_MENU_PREFIX=gnome- : XDG_RUNTIME_DIR=/run/user/1000 : XDG_SEAT=seat0 : XDG_SESSION_DESKTOP=gnome : XDG_SESSION_ID=2 : XDG_SESSION_TYPE=wayland : XDG_VTNR=2 : XMODIFIERS=@im=ibus : _=/usr/bin/env : cpumodel=Intel(R) Core(TM) i7-10700 CPU @ 2.90GHz : progress_file=/home/admin/otc/ofs-bmc/scripts/../build/progress.txt : which_declare=declare -f : } 2024-04-03 13:38:30 :: This is supposed to be the project root:/home/admin/otc/ofs-bmc 2024-04-03 13:38:30 :: This is supposed to be the users build dir:/home 2024-04-03 13:38:30 :: - PLATFORM: Arrow_Creek 2024-04-03 13:38:30 :: Seems to be running locale on user PC ~/otc/ofs-bmc/scripts ~/otc/ofs-bmc/scripts ~/otc/ofs-bmc/scripts 2024-04-03 13:38:30 :: Script started on localhost.localdomain 2024-04-03 13:38:30 :: 2024-04-03 13:38:30 :: -- pid:245768, ppid:4784 2024-04-03 13:38:30 :: -- You can terminate this job by following these setps: 2024-04-03 13:38:30 :: -- log in to the server localhost.localdomain and kill the process 245768 2024-04-03 13:38:30 :: -- for that you can use these command(s): 2024-04-03 13:38:30 :: -- kill -9 -- -245768 2024-04-03 13:38:30 :: 2024-04-03 13:38:30 :: List of parameters controlling this build: 2024-04-03 13:38:30 :: Build machine..........: localhost.localdomain 2024-04-03 13:38:30 :: Building project_dir...: /home/admin/otc/ofs-bmc 2024-04-03 13:38:30 :: Building for platform..: Arrow_Creek 2024-04-03 13:38:30 :: 2024-04-03 13:38:30 :: ALTERAD_LICENSE_FILE...: 2024-04-03 13:38:30 :: QUARTUS_ROOTDIR........: /home/admin/Complete/quartus 2024-04-03 13:38:30 :: QUARTUS_VER............: 23.1std 2024-04-03 13:38:30 :: 2024-04-03 13:38:30 :: Make binary............: /usr/bin/make 2024-04-03 13:38:30 :: Make version...........: GNU Make 4.2.1 2024-04-03 13:38:30 :: Bash version...........: 4.4.20(1)-release 2024-04-03 13:38:30 :: tclsh binary...........: /home/admin/Complete/quartus/linux64/tclsh 2024-04-03 13:38:30 :: tclsh version..........: 8.6 2024-04-03 13:38:30 :: 2024-04-03 13:38:30 :: skip_rev...............: 0 2024-04-03 13:38:30 :: skip_initial_backup....: 0 2024-04-03 13:38:30 :: skip_final_backup......: 0 2024-04-03 13:38:30 :: skip_ip_clean..........: 1 2024-04-03 13:38:30 :: skip_final_build.......: 0 2024-04-03 13:38:30 :: skip_rebuild...........: 0 2024-04-03 13:38:30 :: skip_rtl...............: 0 2024-04-03 13:38:30 :: skip_sw................: 0 2024-04-03 13:38:30 :: skip_dse...............: 0 2024-04-03 13:38:30 :: skip_arch..............: 0 2024-04-03 13:38:30 :: fruid..................: 0 2024-04-03 13:38:30 :: debug..................: 0 2024-04-03 13:38:30 :: jtag...................: 0 2024-04-03 13:38:30 :: test_build.............: 0 2024-04-03 13:38:30 :: custom_ver_en..........: 0 2024-04-03 13:38:30 :: custom_ver_str.........: 2024-04-03 13:38:30 :: 2024-04-03 13:38:30 :: INTEL_KEYS_DIR.........: 2024-04-03 13:38:30 :: REVISION_CODES_DIR.....: /home/admin/otc/ofs-bmc/scripts/revision-codes 2024-04-03 13:38:30 :: 2024-04-03 13:38:30 :: Repo is at: : : commit 9104c11292b1cc9eb686d0c8896cc700d2e5126a : : Author: cohensus <65044852+cohensus@users.noreply.github.com> : : Date: Mon Oct 2 10:33:37 2023 -0500 : : : : Update README.md : : On branch max10_bmc_v3_15_0 2024-04-03 13:38:30 :: LOCAL BUILD - SKIPPING SDK REVISION GEN ............................................................................................... 2024-04-03 13:38:30 :: Generated rtl_revision : 3.15.0 2024-04-03 13:38:30 :: fw_rev_hex=0x030f00, fw_rev=3.15.0 ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:38:30 :: Initial backup of src files started ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:38:30 :: Backup dir :/home/admin/otc/ofs-bmc/backup 2024-04-03 13:38:30 :: Backup filename:backup240403-1338_3.15.0_src 2024-04-03 13:39:31 :: Initial backup of src files done ............................................................................................... 2024-04-03 13:39:32 :: Checking for Signal Tap: 2024-04-03 13:39:32 :: - Signal Tap is disabled ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:39:32 :: BUILD_QSYS_AND_BSP: jtag_str= ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:39:32 :: Generating QSYS outputs to /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys 2024.04.03.13:39:44 Info: Saving generation log to /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/max10_qsys_generation.rpt 2024.04.03.13:39:44 Info: Starting: Create simulation model 2024.04.03.13:39:44 Info: qsys-generate /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation --family="MAX 10" --part=10M50DAF256I6G 2024.04.03.13:39:44 Info: Loading max10_qsys/max10_qsys.qsys 2024.04.03.13:39:44 Info: Reading input file 2024.04.03.13:39:44 Info: Adding adc [altera_modular_dual_adc 23.1] 2024.04.03.13:39:44 Info: Parameterizing module adc 2024.04.03.13:39:44 Info: Adding bmc_dma [bmc_dma 1.0] 2024.04.03.13:39:44 Info: Parameterizing module bmc_dma 2024.04.03.13:39:44 Info: Adding clk_100m [clock_source 23.1] 2024.04.03.13:39:44 Info: Parameterizing module clk_100m 2024.04.03.13:39:44 Info: Adding clk_100m_p90 [clock_source 23.1] 2024.04.03.13:39:44 Info: Parameterizing module clk_100m_p90 2024.04.03.13:39:44 Info: Adding clk_10m [clock_source 23.1] 2024.04.03.13:39:44 Info: Parameterizing module clk_10m 2024.04.03.13:39:44 Info: Adding clk_25m [clock_source 23.1] 2024.04.03.13:39:44 Info: Parameterizing module clk_25m 2024.04.03.13:39:44 Info: Adding clk_50m [clock_source 23.1] 2024.04.03.13:39:44 Info: Parameterizing module clk_50m 2024.04.03.13:39:44 Info: Adding crypto_384 [crypto_384 1.0] 2024.04.03.13:39:44 Info: Parameterizing module crypto_384 2024.04.03.13:39:44 Info: Adding dual_boot [altera_dual_boot 23.1] 2024.04.03.13:39:44 Info: Parameterizing module dual_boot 2024.04.03.13:39:44 Info: Adding fpga_flash [intel_generic_serial_flash_interface_top 23.1] 2024.04.03.13:39:44 Info: Parameterizing module fpga_flash 2024.04.03.13:39:44 Info: Adding hyper_ram [hyperram_ctrlr 1.0] 2024.04.03.13:39:44 Info: Parameterizing module hyper_ram 2024.04.03.13:39:44 Info: Adding i2c_0 [altera_avalon_i2c 23.1] 2024.04.03.13:39:44 Info: Parameterizing module i2c_0 2024.04.03.13:39:44 Info: Adding i2c_1 [altera_avalon_i2c 23.1] 2024.04.03.13:39:44 Info: Parameterizing module i2c_1 2024.04.03.13:39:44 Info: Adding i2c_oob_slave [altera_i2cslave_to_avlmm_bridge 23.1] 2024.04.03.13:39:44 Info: Parameterizing module i2c_oob_slave 2024.04.03.13:39:44 Info: Adding irq_bridge [altera_irq_bridge 23.1] 2024.04.03.13:39:44 Info: Parameterizing module irq_bridge 2024.04.03.13:39:44 Info: Adding jtag_ctrlr_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:44 Info: Parameterizing module jtag_ctrlr_bridge 2024.04.03.13:39:44 Info: Adding max10_nios [altera_nios2_gen2 23.1] 2024.04.03.13:39:44 Info: Parameterizing module max10_nios 2024.04.03.13:39:44 Info: Adding mctp_pcievdm_buffer [mctp_pcievdm_buffer 1.0] 2024.04.03.13:39:44 Info: Parameterizing module mctp_pcievdm_buffer 2024.04.03.13:39:44 Info: Adding mctp_smbus_req_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:44 Info: Parameterizing module mctp_smbus_req_bridge 2024.04.03.13:39:44 Info: Adding mctp_smbus_req_ram [altera_avalon_onchip_memory2 23.1] 2024.04.03.13:39:44 Info: Parameterizing module mctp_smbus_req_ram 2024.04.03.13:39:44 Info: Adding mctp_smbus_resp_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:44 Info: Parameterizing module mctp_smbus_resp_bridge 2024.04.03.13:39:44 Info: Adding mctp_smbus_resp_ram [altera_avalon_onchip_memory2 23.1] 2024.04.03.13:39:44 Info: Parameterizing module mctp_smbus_resp_ram 2024.04.03.13:39:44 Info: Adding mlb_csr_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:44 Info: Parameterizing module mlb_csr_bridge 2024.04.03.13:39:44 Info: Adding nios_flash [intel_generic_serial_flash_interface_top 23.1] 2024.04.03.13:39:44 Info: Parameterizing module nios_flash 2024.04.03.13:39:44 Info: Adding onchip_flash [altera_onchip_flash 23.1] 2024.04.03.13:39:44 Info: Parameterizing module onchip_flash 2024.04.03.13:39:44 Info: Adding reboot_ctrl [max10_reboot_ctrl 1.0] 2024.04.03.13:39:44 Info: Parameterizing module reboot_ctrl 2024.04.03.13:39:44 Info: Adding spi_master [avmms_2_spim_bridge 1.0] 2024.04.03.13:39:44 Info: Parameterizing module spi_master 2024.04.03.13:39:44 Info: Adding spi_slave [spi_slave_to_avalon_mm_master_bridge 23.1] 2024.04.03.13:39:44 Info: Parameterizing module spi_slave 2024.04.03.13:39:44 Info: Adding sys_csr_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:44 Info: Parameterizing module sys_csr_bridge 2024.04.03.13:39:44 Info: Adding sys_id [altera_avalon_sysid_qsys 23.1] 2024.04.03.13:39:44 Info: Parameterizing module sys_id 2024.04.03.13:39:44 Info: Adding timer_0 [altera_avalon_timer 23.1] 2024.04.03.13:39:44 Info: Parameterizing module timer_0 2024.04.03.13:39:44 Info: Adding timer_1 [altera_avalon_timer 23.1] 2024.04.03.13:39:44 Info: Parameterizing module timer_1 2024.04.03.13:39:44 Info: Adding uart_console [altera_avalon_uart 23.1] 2024.04.03.13:39:44 Info: Parameterizing module uart_console 2024.04.03.13:39:44 Info: Building connections 2024.04.03.13:39:44 Info: Parameterizing connections 2024.04.03.13:39:44 Info: Validating 2024.04.03.13:39:44 Info: Done reading input file 2024.04.03.13:39:45 Warning: max10_qsys.max10_nios: No Debugger. You will not be able to download or debug programs 2024.04.03.13:39:45 Warning: max10_qsys.max10_nios: Nios II cores are not recommended for new projects and are subject to removal in a future release. Nios V cores are the recommended replacement as applicable. 2024.04.03.13:39:45 Info: max10_qsys.spi_master: 'Base Address of Direct Slave Access' should be more than CSR slave access address range 2024.04.03.13:39:45 Warning: max10_qsys.adc: Interrupt sender adc.sample_store_irq is not connected to an interrupt receiver 2024.04.03.13:39:45 Warning: max10_qsys.i2c_0: Interrupt sender i2c_0.interrupt_sender is not connected to an interrupt receiver 2024.04.03.13:39:45 Warning: max10_qsys.i2c_1: Interrupt sender i2c_1.interrupt_sender is not connected to an interrupt receiver 2024.04.03.13:39:45 Info: max10_qsys: Generating max10_qsys "max10_qsys" for SIM_VERILOG 2024.04.03.13:39:46 Info: Interconnect is inserted between master mctp_pcievdm_buffer.avmm_egrs_mstr and slave spi_master.avmm_dir because the master has address signal 11 bit wide, but the slave is 9 bit wide. 2024.04.03.13:39:46 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:46 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:46 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:46 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has byteenable signal 4 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:46 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:46 Info: Inserting clock-crossing logic between cmd_demux_001.src6 and cmd_mux_006.sink0 2024.04.03.13:39:46 Info: Inserting clock-crossing logic between rsp_demux_006.src0 and rsp_mux_001.sink6 2024.04.03.13:39:49 Info: adc: "max10_qsys" instantiated altera_modular_dual_adc "adc" 2024.04.03.13:39:49 Info: bmc_dma: "max10_qsys" instantiated bmc_dma "bmc_dma" 2024.04.03.13:39:49 Info: crypto_384: "max10_qsys" instantiated crypto_384 "crypto_384" 2024.04.03.13:39:49 Info: dual_boot: "max10_qsys" instantiated altera_dual_boot "dual_boot" 2024.04.03.13:39:49 Info: fpga_flash: "max10_qsys" instantiated intel_generic_serial_flash_interface_top "fpga_flash" 2024.04.03.13:39:49 Info: hyper_ram: "max10_qsys" instantiated hyperram_ctrlr "hyper_ram" 2024.04.03.13:39:49 Info: i2c_0: "max10_qsys" instantiated altera_avalon_i2c "i2c_0" 2024.04.03.13:39:49 Info: i2c_oob_slave: "max10_qsys" instantiated altera_i2cslave_to_avlmm_bridge "i2c_oob_slave" 2024.04.03.13:39:49 Info: irq_bridge: "max10_qsys" instantiated altera_irq_bridge "irq_bridge" 2024.04.03.13:39:49 Info: jtag_ctrlr_bridge: "max10_qsys" instantiated altera_avalon_mm_bridge "jtag_ctrlr_bridge" 2024.04.03.13:39:49 Info: max10_nios: "max10_qsys" instantiated altera_nios2_gen2 "max10_nios" 2024.04.03.13:39:49 Info: mctp_pcievdm_buffer: "max10_qsys" instantiated mctp_pcievdm_buffer "mctp_pcievdm_buffer" 2024.04.03.13:39:50 Info: mctp_smbus_req_ram: Starting RTL generation for module 'max10_qsys_mctp_smbus_req_ram' 2024.04.03.13:39:50 Info: mctp_smbus_req_ram: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64/perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=max10_qsys_mctp_smbus_req_ram --dir=/tmp/alt9816_2366828103330642614.dir/0013_mctp_smbus_req_ram_gen/ --quartus_dir=/home/admin/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt9816_2366828103330642614.dir/0013_mctp_smbus_req_ram_gen//max10_qsys_mctp_smbus_req_ram_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt9816_2366828103330642614.dir/0013_mctp_smbus_req_ram_gen/ ] 2024.04.03.13:39:50 Info: mctp_smbus_req_ram: Done RTL generation for module 'max10_qsys_mctp_smbus_req_ram' 2024.04.03.13:39:50 Info: mctp_smbus_req_ram: "max10_qsys" instantiated altera_avalon_onchip_memory2 "mctp_smbus_req_ram" 2024.04.03.13:39:50 Info: mctp_smbus_resp_ram: Starting RTL generation for module 'max10_qsys_mctp_smbus_resp_ram' 2024.04.03.13:39:50 Info: mctp_smbus_resp_ram: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64/perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=max10_qsys_mctp_smbus_resp_ram --dir=/tmp/alt9816_2366828103330642614.dir/0014_mctp_smbus_resp_ram_gen/ --quartus_dir=/home/admin/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt9816_2366828103330642614.dir/0014_mctp_smbus_resp_ram_gen//max10_qsys_mctp_smbus_resp_ram_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt9816_2366828103330642614.dir/0014_mctp_smbus_resp_ram_gen/ ] 2024.04.03.13:39:50 Info: mctp_smbus_resp_ram: Done RTL generation for module 'max10_qsys_mctp_smbus_resp_ram' 2024.04.03.13:39:50 Info: mctp_smbus_resp_ram: "max10_qsys" instantiated altera_avalon_onchip_memory2 "mctp_smbus_resp_ram" 2024.04.03.13:39:50 Info: nios_flash: "max10_qsys" instantiated intel_generic_serial_flash_interface_top "nios_flash" 2024.04.03.13:39:50 Info: onchip_flash: "max10_qsys" instantiated altera_onchip_flash "onchip_flash" 2024.04.03.13:39:50 Info: reboot_ctrl: "max10_qsys" instantiated max10_reboot_ctrl "reboot_ctrl" 2024.04.03.13:39:50 Info: spi_master: "max10_qsys" instantiated avmms_2_spim_bridge "spi_master" 2024.04.03.13:39:52 Info: spi_slave: "max10_qsys" instantiated spi_slave_to_avalon_mm_master_bridge "spi_slave" 2024.04.03.13:39:52 Warning: Overwriting different file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_avalon_st_bytes_to_packets.v 2024.04.03.13:39:52 Warning: Overwriting different file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_avalon_st_packets_to_bytes.v 2024.04.03.13:39:52 Info: timer_0: Starting RTL generation for module 'max10_qsys_timer_0' 2024.04.03.13:39:52 Info: timer_0: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64//perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64//perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=max10_qsys_timer_0 --dir=/tmp/alt9816_2366828103330642614.dir/0019_timer_0_gen/ --quartus_dir=/home/admin/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt9816_2366828103330642614.dir/0019_timer_0_gen//max10_qsys_timer_0_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt9816_2366828103330642614.dir/0019_timer_0_gen/ ] 2024.04.03.13:39:52 Info: timer_0: Done RTL generation for module 'max10_qsys_timer_0' 2024.04.03.13:39:52 Info: timer_0: "max10_qsys" instantiated altera_avalon_timer "timer_0" 2024.04.03.13:39:52 Info: uart_console: Starting RTL generation for module 'max10_qsys_uart_console' 2024.04.03.13:39:52 Info: uart_console: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64/perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=max10_qsys_uart_console --dir=/tmp/alt9816_2366828103330642614.dir/0020_uart_console_gen/ --quartus_dir=/home/admin/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt9816_2366828103330642614.dir/0020_uart_console_gen//max10_qsys_uart_console_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt9816_2366828103330642614.dir/0020_uart_console_gen/ ] 2024.04.03.13:39:52 Info: uart_console: Done RTL generation for module 'max10_qsys_uart_console' 2024.04.03.13:39:52 Info: uart_console: "max10_qsys" instantiated altera_avalon_uart "uart_console" 2024.04.03.13:39:52 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:52 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:52 Info: mm_interconnect_0: "max10_qsys" instantiated altera_mm_interconnect "mm_interconnect_0" 2024.04.03.13:39:52 Info: mm_interconnect_1: "max10_qsys" instantiated altera_mm_interconnect "mm_interconnect_1" 2024.04.03.13:39:52 Info: mm_interconnect_2: "max10_qsys" instantiated altera_mm_interconnect "mm_interconnect_2" 2024.04.03.13:39:53 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:53 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:53 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:53 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0 2024.04.03.13:39:54 Info: mm_interconnect_3: "max10_qsys" instantiated altera_mm_interconnect "mm_interconnect_3" 2024.04.03.13:39:54 Info: irq_mapper: "max10_qsys" instantiated altera_irq_mapper "irq_mapper" 2024.04.03.13:39:54 Info: rst_controller: "max10_qsys" instantiated altera_reset_controller "rst_controller" 2024.04.03.13:39:54 Info: control_internal: "adc" instantiated altera_modular_adc_control "control_internal" 2024.04.03.13:39:54 Info: sequencer_internal: "adc" instantiated altera_modular_adc_sequencer "sequencer_internal" 2024.04.03.13:39:54 Info: sample_store_internal: "adc" instantiated altera_modular_adc_sample_store "sample_store_internal" 2024.04.03.13:39:54 Info: conduit_splitter_internal: "adc" instantiated altera_modular_adc_conduit_splitter "conduit_splitter_internal" 2024.04.03.13:39:54 Info: dual_sync_internal: "adc" instantiated altera_modular_adc_dual_sync "dual_sync_internal" 2024.04.03.13:39:54 Info: response_merge_internal: "adc" instantiated altera_modular_adc_response_merge "response_merge_internal" 2024.04.03.13:39:54 Info: csr_controller: "fpga_flash" instantiated intel_generic_serial_flash_interface_csr "csr_controller" 2024.04.03.13:39:55 Info: avst_fifo: "Generating: avst_fifo" 2024.04.03.13:39:55 Info: xip_controller: "fpga_flash" instantiated intel_generic_serial_flash_interface_xip "xip_controller" 2024.04.03.13:39:55 Info: xip_addr_adaption: "fpga_flash" instantiated intel_generic_serial_flash_interface_addr "xip_addr_adaption" 2024.04.03.13:39:55 Info: merlin_demultiplexer_0: "fpga_flash" instantiated altera_merlin_demultiplexer "merlin_demultiplexer_0" 2024.04.03.13:39:55 Info: multiplexer: "fpga_flash" instantiated altera_merlin_multiplexer "multiplexer" 2024.04.03.13:39:55 Info: serial_flash_inf_cmd_gen_inst: "fpga_flash" instantiated intel_generic_serial_flash_interface_cmd "serial_flash_inf_cmd_gen_inst" 2024.04.03.13:39:55 Info: qspi_inf_mux: "Generating: qspi_inf_mux" 2024.04.03.13:39:55 Info: inf_sc_fifo_ser_data: "Generating: inf_sc_fifo_ser_data" 2024.04.03.13:39:55 Info: qspi_inf_inst: "fpga_flash" instantiated intel_generic_serial_flash_interface_if_ctrl "qspi_inf_inst" 2024.04.03.13:39:55 Info: cpu: Starting RTL generation for module 'max10_qsys_max10_nios_cpu' 2024.04.03.13:39:55 Info: cpu: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64//perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64//perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=max10_qsys_max10_nios_cpu --dir=/tmp/alt9816_2366828103330642614.dir/0036_cpu_gen/ --quartus_bindir=/home/admin/intelFPGA/23.1std/quartus/linux64/ --verilog --config=/tmp/alt9816_2366828103330642614.dir/0036_cpu_gen//max10_qsys_max10_nios_cpu_processor_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt9816_2366828103330642614.dir/0036_cpu_gen/ ] 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Starting Nios II generation 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Elaborating CPU configuration settings 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Creating all objects for CPU 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Testbench 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Instruction decoding 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Instruction fields 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Instruction decodes 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Signals for RTL simulation waveforms 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:55 (*) Instruction controls 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:56 (*) Pipeline frontend 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:56 (*) Pipeline backend 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:56 (*) Creating '/tmp/alt9816_2366828103330642614.dir/0036_cpu_gen//max10_qsys_max10_nios_cpu_nios2_waves.do' 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:56 (*) Generating RTL from CPU objects 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:56 (*) Creating plain-text RTL 2024.04.03.13:39:57 Info: cpu: # 2024.04.03 13:39:57 (*) Done Nios II generation 2024.04.03.13:39:57 Info: cpu: Done RTL generation for module 'max10_qsys_max10_nios_cpu' 2024.04.03.13:39:57 Info: cpu: "max10_nios" instantiated altera_nios2_gen2_unit "cpu" 2024.04.03.13:39:57 Info: qspi_inf_mux: "Generating: qspi_inf_mux" 2024.04.03.13:39:57 Info: inf_sc_fifo_ser_data: "Generating: inf_sc_fifo_ser_data" 2024.04.03.13:39:57 Info: qspi_inf_inst: "nios_flash" instantiated intel_generic_serial_flash_interface_if_ctrl "qspi_inf_inst" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/intel_generic_serial_flash_interface_asmiblock.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/adapter_8_1.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/adapter_8_2.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/adapter_8_4.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/demultiplexer.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/demultiplexer_7_channel.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/demultiplexer_9_channels.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/demultiplexer_12_channels.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/clk_div.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/clock_devider.sv 2024.04.03.13:39:57 Info: spi_slave_avalon_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "spi_slave_avalon_master_translator" 2024.04.03.13:39:57 Info: mctp_pcievdm_buffer_avmm_ingr_slv_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "mctp_pcievdm_buffer_avmm_ingr_slv_translator" 2024.04.03.13:39:57 Info: spi_slave_avalon_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "spi_slave_avalon_master_agent" 2024.04.03.13:39:57 Info: mctp_pcievdm_buffer_avmm_ingr_slv_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "mctp_pcievdm_buffer_avmm_ingr_slv_agent" 2024.04.03.13:39:57 Info: mctp_pcievdm_buffer_avmm_ingr_slv_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "mctp_pcievdm_buffer_avmm_ingr_slv_agent_rsp_fifo" 2024.04.03.13:39:57 Warning: Overwriting different file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_avalon_sc_fifo.v 2024.04.03.13:39:57 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" 2024.04.03.13:39:57 Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001" 2024.04.03.13:39:57 Info: spi_slave_avalon_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "spi_slave_avalon_master_limiter" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_avalon_sc_fifo.v 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_avalon_sc_fifo.v 2024.04.03.13:39:57 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" 2024.04.03.13:39:57 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" 2024.04.03.13:39:57 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter" 2024.04.03.13:39:57 Info: router: "mm_interconnect_3" instantiated altera_merlin_router "router" 2024.04.03.13:39:57 Info: router_001: "mm_interconnect_3" instantiated altera_merlin_router "router_001" 2024.04.03.13:39:57 Info: router_002: "mm_interconnect_3" instantiated altera_merlin_router "router_002" 2024.04.03.13:39:57 Info: router_003: "mm_interconnect_3" instantiated altera_merlin_router "router_003" 2024.04.03.13:39:57 Info: router_004: "mm_interconnect_3" instantiated altera_merlin_router "router_004" 2024.04.03.13:39:57 Info: router_005: "mm_interconnect_3" instantiated altera_merlin_router "router_005" 2024.04.03.13:39:57 Info: router_006: "mm_interconnect_3" instantiated altera_merlin_router "router_006" 2024.04.03.13:39:57 Info: router_007: "mm_interconnect_3" instantiated altera_merlin_router "router_007" 2024.04.03.13:39:57 Info: router_009: "mm_interconnect_3" instantiated altera_merlin_router "router_009" 2024.04.03.13:39:57 Info: router_023: "mm_interconnect_3" instantiated altera_merlin_router "router_023" 2024.04.03.13:39:57 Info: router_024: "mm_interconnect_3" instantiated altera_merlin_router "router_024" 2024.04.03.13:39:57 Info: nios_flash_avl_mem_burst_adapter: "mm_interconnect_3" instantiated altera_merlin_burst_adapter "nios_flash_avl_mem_burst_adapter" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_avalon_st_pipeline_base.v 2024.04.03.13:39:57 Info: cmd_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux" 2024.04.03.13:39:57 Info: cmd_demux_001: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux_001" 2024.04.03.13:39:57 Info: cmd_demux_002: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux_002" 2024.04.03.13:39:57 Info: cmd_demux_003: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux_003" 2024.04.03.13:39:57 Info: cmd_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: cmd_mux_001: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux_001" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: cmd_mux_004: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux_004" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: cmd_mux_018: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux_018" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: rsp_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux" 2024.04.03.13:39:57 Info: rsp_demux_001: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux_001" 2024.04.03.13:39:57 Info: rsp_demux_004: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux_004" 2024.04.03.13:39:57 Info: rsp_demux_006: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux_006" 2024.04.03.13:39:57 Info: rsp_demux_018: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux_018" 2024.04.03.13:39:57 Info: rsp_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: rsp_mux_001: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux_001" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: rsp_mux_002: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux_002" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: rsp_mux_003: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux_003" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: max10_nios_data_master_to_mctp_smbus_req_ram_s1_cmd_width_adapter: "mm_interconnect_3" instantiated altera_merlin_width_adapter "max10_nios_data_master_to_mctp_smbus_req_ram_s1_cmd_width_adapter" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_address_alignment.sv 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_burst_uncompressor.sv 2024.04.03.13:39:57 Info: crosser: "mm_interconnect_3" instantiated altera_avalon_st_handshake_clock_crosser "crosser" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_avalon_st_pipeline_base.v 2024.04.03.13:39:57 Info: avalon_st_adapter_018: "mm_interconnect_3" instantiated altera_avalon_st_adapter "avalon_st_adapter_018" 2024.04.03.13:39:57 Info: avst_fifo: "xip_controller" instantiated intel_generic_serial_flash_interface_xip "avst_fifo" 2024.04.03.13:39:57 Info: qspi_inf_mux: "qspi_inf_inst" instantiated intel_generic_serial_flash_interface_if_ctrl "qspi_inf_mux" 2024.04.03.13:39:57 Info: inf_sc_fifo_ser_data: "qspi_inf_inst" instantiated intel_generic_serial_flash_interface_if_ctrl "inf_sc_fifo_ser_data" 2024.04.03.13:39:57 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" 2024.04.03.13:39:57 Info: error_adapter_0: "avalon_st_adapter_018" instantiated error_adapter "error_adapter_0" 2024.04.03.13:39:57 Info: qspi_inf_mux: "qspi_inf_mux" instantiated altera_merlin_multiplexer "qspi_inf_mux" 2024.04.03.13:39:57 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:39:57 Info: max10_qsys: Done "max10_qsys" with 94 modules, 229 files 2024.04.03.13:39:57 Info: qsys-generate succeeded. 2024.04.03.13:39:57 Info: Finished: Create simulation model 2024.04.03.13:39:57 Info: Starting: Create Modelsim Project. 2024.04.03.13:39:57 Info: sim-script-gen --spd=/home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/max10_qsys.spd --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/ --use-relative-paths=true 2024.04.03.13:39:57 Info: Doing: ip-make-simscript --spd=/home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/max10_qsys.spd --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/ --use-relative-paths=true 2024.04.03.13:39:58 Info: Generating the following file(s) for MODELSIM simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/ directory: 2024.04.03.13:39:58 Info: mentor/msim_setup.tcl 2024.04.03.13:39:58 Info: Generating the following file(s) for VCSMX simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/ directory: 2024.04.03.13:39:58 Info: synopsys/vcsmx/synopsys_sim.setup 2024.04.03.13:39:58 Info: synopsys/vcsmx/vcsmx_setup.sh 2024.04.03.13:39:58 Info: Generating the following file(s) for XCELIUM simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/ directory: 2024.04.03.13:39:58 Info: xcelium/cds.lib 2024.04.03.13:39:58 Info: xcelium/hdl.var 2024.04.03.13:39:58 Info: xcelium/xcelium_setup.sh 2024.04.03.13:39:58 Info: 84 .cds.lib files in xcelium/cds_libs/ directory 2024.04.03.13:39:58 Info: Generating the following file(s) for VCS simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/ directory: 2024.04.03.13:39:58 Info: synopsys/vcs/vcs_setup.sh 2024.04.03.13:39:58 Info: Generating the following file(s) for RIVIERA simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/ directory: 2024.04.03.13:39:58 Info: aldec/rivierapro_setup.tcl 2024.04.03.13:39:58 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/simulation/. 2024.04.03.13:39:58 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. 2024.04.03.13:39:58 Info: Finished: Create Modelsim Project. 2024.04.03.13:39:58 Info: 2024.04.03.13:39:58 Info: Starting: Create HDL design files for synthesis 2024.04.03.13:39:58 Info: qsys-generate /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys.qsys --synthesis=VERILOG --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis --family="MAX 10" --part=10M50DAF256I6G 2024.04.03.13:39:58 Info: Loading max10_qsys/max10_qsys.qsys 2024.04.03.13:39:58 Info: Reading input file 2024.04.03.13:39:58 Info: Adding adc [altera_modular_dual_adc 23.1] 2024.04.03.13:39:58 Info: Parameterizing module adc 2024.04.03.13:39:58 Info: Adding bmc_dma [bmc_dma 1.0] 2024.04.03.13:39:58 Info: Parameterizing module bmc_dma 2024.04.03.13:39:58 Info: Adding clk_100m [clock_source 23.1] 2024.04.03.13:39:58 Info: Parameterizing module clk_100m 2024.04.03.13:39:58 Info: Adding clk_100m_p90 [clock_source 23.1] 2024.04.03.13:39:58 Info: Parameterizing module clk_100m_p90 2024.04.03.13:39:58 Info: Adding clk_10m [clock_source 23.1] 2024.04.03.13:39:58 Info: Parameterizing module clk_10m 2024.04.03.13:39:58 Info: Adding clk_25m [clock_source 23.1] 2024.04.03.13:39:58 Info: Parameterizing module clk_25m 2024.04.03.13:39:58 Info: Adding clk_50m [clock_source 23.1] 2024.04.03.13:39:58 Info: Parameterizing module clk_50m 2024.04.03.13:39:58 Info: Adding crypto_384 [crypto_384 1.0] 2024.04.03.13:39:58 Info: Parameterizing module crypto_384 2024.04.03.13:39:58 Info: Adding dual_boot [altera_dual_boot 23.1] 2024.04.03.13:39:58 Info: Parameterizing module dual_boot 2024.04.03.13:39:58 Info: Adding fpga_flash [intel_generic_serial_flash_interface_top 23.1] 2024.04.03.13:39:58 Info: Parameterizing module fpga_flash 2024.04.03.13:39:58 Info: Adding hyper_ram [hyperram_ctrlr 1.0] 2024.04.03.13:39:58 Info: Parameterizing module hyper_ram 2024.04.03.13:39:58 Info: Adding i2c_0 [altera_avalon_i2c 23.1] 2024.04.03.13:39:58 Info: Parameterizing module i2c_0 2024.04.03.13:39:58 Info: Adding i2c_1 [altera_avalon_i2c 23.1] 2024.04.03.13:39:58 Info: Parameterizing module i2c_1 2024.04.03.13:39:58 Info: Adding i2c_oob_slave [altera_i2cslave_to_avlmm_bridge 23.1] 2024.04.03.13:39:58 Info: Parameterizing module i2c_oob_slave 2024.04.03.13:39:58 Info: Adding irq_bridge [altera_irq_bridge 23.1] 2024.04.03.13:39:58 Info: Parameterizing module irq_bridge 2024.04.03.13:39:58 Info: Adding jtag_ctrlr_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:58 Info: Parameterizing module jtag_ctrlr_bridge 2024.04.03.13:39:58 Info: Adding max10_nios [altera_nios2_gen2 23.1] 2024.04.03.13:39:58 Info: Parameterizing module max10_nios 2024.04.03.13:39:58 Info: Adding mctp_pcievdm_buffer [mctp_pcievdm_buffer 1.0] 2024.04.03.13:39:58 Info: Parameterizing module mctp_pcievdm_buffer 2024.04.03.13:39:58 Info: Adding mctp_smbus_req_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:58 Info: Parameterizing module mctp_smbus_req_bridge 2024.04.03.13:39:58 Info: Adding mctp_smbus_req_ram [altera_avalon_onchip_memory2 23.1] 2024.04.03.13:39:58 Info: Parameterizing module mctp_smbus_req_ram 2024.04.03.13:39:58 Info: Adding mctp_smbus_resp_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:58 Info: Parameterizing module mctp_smbus_resp_bridge 2024.04.03.13:39:58 Info: Adding mctp_smbus_resp_ram [altera_avalon_onchip_memory2 23.1] 2024.04.03.13:39:58 Info: Parameterizing module mctp_smbus_resp_ram 2024.04.03.13:39:58 Info: Adding mlb_csr_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:58 Info: Parameterizing module mlb_csr_bridge 2024.04.03.13:39:58 Info: Adding nios_flash [intel_generic_serial_flash_interface_top 23.1] 2024.04.03.13:39:58 Info: Parameterizing module nios_flash 2024.04.03.13:39:58 Info: Adding onchip_flash [altera_onchip_flash 23.1] 2024.04.03.13:39:58 Info: Parameterizing module onchip_flash 2024.04.03.13:39:58 Info: Adding reboot_ctrl [max10_reboot_ctrl 1.0] 2024.04.03.13:39:58 Info: Parameterizing module reboot_ctrl 2024.04.03.13:39:58 Info: Adding spi_master [avmms_2_spim_bridge 1.0] 2024.04.03.13:39:58 Info: Parameterizing module spi_master 2024.04.03.13:39:58 Info: Adding spi_slave [spi_slave_to_avalon_mm_master_bridge 23.1] 2024.04.03.13:39:58 Info: Parameterizing module spi_slave 2024.04.03.13:39:58 Info: Adding sys_csr_bridge [altera_avalon_mm_bridge 23.1] 2024.04.03.13:39:58 Info: Parameterizing module sys_csr_bridge 2024.04.03.13:39:58 Info: Adding sys_id [altera_avalon_sysid_qsys 23.1] 2024.04.03.13:39:58 Info: Parameterizing module sys_id 2024.04.03.13:39:58 Info: Adding timer_0 [altera_avalon_timer 23.1] 2024.04.03.13:39:58 Info: Parameterizing module timer_0 2024.04.03.13:39:58 Info: Adding timer_1 [altera_avalon_timer 23.1] 2024.04.03.13:39:58 Info: Parameterizing module timer_1 2024.04.03.13:39:58 Info: Adding uart_console [altera_avalon_uart 23.1] 2024.04.03.13:39:58 Info: Parameterizing module uart_console 2024.04.03.13:39:58 Info: Building connections 2024.04.03.13:39:58 Info: Parameterizing connections 2024.04.03.13:39:58 Info: Validating 2024.04.03.13:39:58 Info: Done reading input file 2024.04.03.13:39:58 Warning: max10_qsys.max10_nios: No Debugger. You will not be able to download or debug programs 2024.04.03.13:39:58 Warning: max10_qsys.max10_nios: Nios II cores are not recommended for new projects and are subject to removal in a future release. Nios V cores are the recommended replacement as applicable. 2024.04.03.13:39:58 Info: max10_qsys.spi_master: 'Base Address of Direct Slave Access' should be more than CSR slave access address range 2024.04.03.13:39:58 Warning: max10_qsys.adc: Interrupt sender adc.sample_store_irq is not connected to an interrupt receiver 2024.04.03.13:39:58 Warning: max10_qsys.i2c_0: Interrupt sender i2c_0.interrupt_sender is not connected to an interrupt receiver 2024.04.03.13:39:58 Warning: max10_qsys.i2c_1: Interrupt sender i2c_1.interrupt_sender is not connected to an interrupt receiver 2024.04.03.13:39:59 Info: max10_qsys: Generating max10_qsys "max10_qsys" for QUARTUS_SYNTH 2024.04.03.13:39:59 Info: Interconnect is inserted between master mctp_pcievdm_buffer.avmm_egrs_mstr and slave spi_master.avmm_dir because the master has address signal 11 bit wide, but the slave is 9 bit wide. 2024.04.03.13:39:59 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:59 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:59 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:59 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has byteenable signal 4 bit wide, but the slave is 0 bit wide. 2024.04.03.13:39:59 Info: Interconnect is inserted between master reboot_ctrl.avmm_master and slave dual_boot.avalon because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide. 2024.04.03.13:40:00 Info: Inserting clock-crossing logic between cmd_demux_001.src6 and cmd_mux_006.sink0 2024.04.03.13:40:00 Info: Inserting clock-crossing logic between rsp_demux_006.src0 and rsp_mux_001.sink6 2024.04.03.13:40:02 Info: adc: "max10_qsys" instantiated altera_modular_dual_adc "adc" 2024.04.03.13:40:02 Info: bmc_dma: "max10_qsys" instantiated bmc_dma "bmc_dma" 2024.04.03.13:40:02 Info: crypto_384: "max10_qsys" instantiated crypto_384 "crypto_384" 2024.04.03.13:40:02 Info: dual_boot: generating top-level entity altera_dual_boot 2024.04.03.13:40:02 Info: dual_boot: "max10_qsys" instantiated altera_dual_boot "dual_boot" 2024.04.03.13:40:02 Info: fpga_flash: "max10_qsys" instantiated intel_generic_serial_flash_interface_top "fpga_flash" 2024.04.03.13:40:02 Info: hyper_ram: "max10_qsys" instantiated hyperram_ctrlr "hyper_ram" 2024.04.03.13:40:02 Info: i2c_0: "max10_qsys" instantiated altera_avalon_i2c "i2c_0" 2024.04.03.13:40:02 Info: i2c_oob_slave: "max10_qsys" instantiated altera_i2cslave_to_avlmm_bridge "i2c_oob_slave" 2024.04.03.13:40:02 Info: irq_bridge: "max10_qsys" instantiated altera_irq_bridge "irq_bridge" 2024.04.03.13:40:02 Info: jtag_ctrlr_bridge: "max10_qsys" instantiated altera_avalon_mm_bridge "jtag_ctrlr_bridge" 2024.04.03.13:40:02 Info: max10_nios: "max10_qsys" instantiated altera_nios2_gen2 "max10_nios" 2024.04.03.13:40:02 Info: mctp_pcievdm_buffer: "max10_qsys" instantiated mctp_pcievdm_buffer "mctp_pcievdm_buffer" 2024.04.03.13:40:02 Info: mctp_smbus_req_ram: Starting RTL generation for module 'max10_qsys_mctp_smbus_req_ram' 2024.04.03.13:40:02 Info: mctp_smbus_req_ram: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64/perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=max10_qsys_mctp_smbus_req_ram --dir=/tmp/alt9816_2366828103330642614.dir/0094_mctp_smbus_req_ram_gen/ --quartus_dir=/home/admin/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt9816_2366828103330642614.dir/0094_mctp_smbus_req_ram_gen//max10_qsys_mctp_smbus_req_ram_component_configuration.pl --do_build_sim=0 ] 2024.04.03.13:40:02 Info: mctp_smbus_req_ram: Done RTL generation for module 'max10_qsys_mctp_smbus_req_ram' 2024.04.03.13:40:02 Info: mctp_smbus_req_ram: "max10_qsys" instantiated altera_avalon_onchip_memory2 "mctp_smbus_req_ram" 2024.04.03.13:40:02 Info: mctp_smbus_resp_ram: Starting RTL generation for module 'max10_qsys_mctp_smbus_resp_ram' 2024.04.03.13:40:02 Info: mctp_smbus_resp_ram: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64/perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=max10_qsys_mctp_smbus_resp_ram --dir=/tmp/alt9816_2366828103330642614.dir/0095_mctp_smbus_resp_ram_gen/ --quartus_dir=/home/admin/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt9816_2366828103330642614.dir/0095_mctp_smbus_resp_ram_gen//max10_qsys_mctp_smbus_resp_ram_component_configuration.pl --do_build_sim=0 ] 2024.04.03.13:40:02 Info: mctp_smbus_resp_ram: Done RTL generation for module 'max10_qsys_mctp_smbus_resp_ram' 2024.04.03.13:40:02 Info: mctp_smbus_resp_ram: "max10_qsys" instantiated altera_avalon_onchip_memory2 "mctp_smbus_resp_ram" 2024.04.03.13:40:02 Info: nios_flash: "max10_qsys" instantiated intel_generic_serial_flash_interface_top "nios_flash" 2024.04.03.13:40:02 Info: onchip_flash: Generating top-level entity altera_onchip_flash 2024.04.03.13:40:02 Info: onchip_flash: "max10_qsys" instantiated altera_onchip_flash "onchip_flash" 2024.04.03.13:40:02 Info: reboot_ctrl: "max10_qsys" instantiated max10_reboot_ctrl "reboot_ctrl" 2024.04.03.13:40:02 Info: spi_master: "max10_qsys" instantiated avmms_2_spim_bridge "spi_master" 2024.04.03.13:40:02 Info: spi_slave: "max10_qsys" instantiated spi_slave_to_avalon_mm_master_bridge "spi_slave" 2024.04.03.13:40:02 Warning: Overwriting different file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets.v 2024.04.03.13:40:02 Warning: Overwriting different file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes.v 2024.04.03.13:40:02 Info: timer_0: Starting RTL generation for module 'max10_qsys_timer_0' 2024.04.03.13:40:02 Info: timer_0: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64//perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64//perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=max10_qsys_timer_0 --dir=/tmp/alt9816_2366828103330642614.dir/0099_timer_0_gen/ --quartus_dir=/home/admin/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt9816_2366828103330642614.dir/0099_timer_0_gen//max10_qsys_timer_0_component_configuration.pl --do_build_sim=0 ] 2024.04.03.13:40:02 Info: timer_0: Done RTL generation for module 'max10_qsys_timer_0' 2024.04.03.13:40:02 Info: timer_0: "max10_qsys" instantiated altera_avalon_timer "timer_0" 2024.04.03.13:40:02 Info: uart_console: Starting RTL generation for module 'max10_qsys_uart_console' 2024.04.03.13:40:02 Info: uart_console: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64/perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64/perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=max10_qsys_uart_console --dir=/tmp/alt9816_2366828103330642614.dir/0100_uart_console_gen/ --quartus_dir=/home/admin/intelFPGA/23.1std/quartus --verilog --config=/tmp/alt9816_2366828103330642614.dir/0100_uart_console_gen//max10_qsys_uart_console_component_configuration.pl --do_build_sim=0 ] 2024.04.03.13:40:03 Info: uart_console: Done RTL generation for module 'max10_qsys_uart_console' 2024.04.03.13:40:03 Info: uart_console: "max10_qsys" instantiated altera_avalon_uart "uart_console" 2024.04.03.13:40:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:03 Info: mm_interconnect_0: "max10_qsys" instantiated altera_mm_interconnect "mm_interconnect_0" 2024.04.03.13:40:03 Info: mm_interconnect_1: "max10_qsys" instantiated altera_mm_interconnect "mm_interconnect_1" 2024.04.03.13:40:03 Info: mm_interconnect_2: "max10_qsys" instantiated altera_mm_interconnect "mm_interconnect_2" 2024.04.03.13:40:04 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0 2024.04.03.13:40:05 Info: mm_interconnect_3: "max10_qsys" instantiated altera_mm_interconnect "mm_interconnect_3" 2024.04.03.13:40:05 Info: irq_mapper: "max10_qsys" instantiated altera_irq_mapper "irq_mapper" 2024.04.03.13:40:05 Info: rst_controller: "max10_qsys" instantiated altera_reset_controller "rst_controller" 2024.04.03.13:40:05 Info: control_internal: "adc" instantiated altera_modular_adc_control "control_internal" 2024.04.03.13:40:05 Info: sequencer_internal: "adc" instantiated altera_modular_adc_sequencer "sequencer_internal" 2024.04.03.13:40:05 Info: sample_store_internal: "adc" instantiated altera_modular_adc_sample_store "sample_store_internal" 2024.04.03.13:40:05 Info: conduit_splitter_internal: "adc" instantiated altera_modular_adc_conduit_splitter "conduit_splitter_internal" 2024.04.03.13:40:05 Info: dual_sync_internal: "adc" instantiated altera_modular_adc_dual_sync "dual_sync_internal" 2024.04.03.13:40:05 Info: response_merge_internal: "adc" instantiated altera_modular_adc_response_merge "response_merge_internal" 2024.04.03.13:40:05 Info: csr_controller: "fpga_flash" instantiated intel_generic_serial_flash_interface_csr "csr_controller" 2024.04.03.13:40:05 Info: avst_fifo: "Generating: avst_fifo" 2024.04.03.13:40:05 Info: xip_controller: "fpga_flash" instantiated intel_generic_serial_flash_interface_xip "xip_controller" 2024.04.03.13:40:05 Info: xip_addr_adaption: "fpga_flash" instantiated intel_generic_serial_flash_interface_addr "xip_addr_adaption" 2024.04.03.13:40:05 Info: merlin_demultiplexer_0: "fpga_flash" instantiated altera_merlin_demultiplexer "merlin_demultiplexer_0" 2024.04.03.13:40:05 Info: multiplexer: "fpga_flash" instantiated altera_merlin_multiplexer "multiplexer" 2024.04.03.13:40:05 Info: serial_flash_inf_cmd_gen_inst: "fpga_flash" instantiated intel_generic_serial_flash_interface_cmd "serial_flash_inf_cmd_gen_inst" 2024.04.03.13:40:05 Info: qspi_inf_mux: "Generating: qspi_inf_mux" 2024.04.03.13:40:05 Info: inf_sc_fifo_ser_data: "Generating: inf_sc_fifo_ser_data" 2024.04.03.13:40:05 Info: qspi_inf_inst: "fpga_flash" instantiated intel_generic_serial_flash_interface_if_ctrl "qspi_inf_inst" 2024.04.03.13:40:05 Info: cpu: Starting RTL generation for module 'max10_qsys_max10_nios_cpu' 2024.04.03.13:40:05 Info: cpu: Generation command is [exec /home/admin/intelFPGA/23.1std/quartus/linux64//perl/bin/perl -I /home/admin/intelFPGA/23.1std/quartus/linux64//perl/lib -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin/europa -I /home/admin/intelFPGA/23.1std/quartus/sopc_builder/bin -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/admin/intelFPGA/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=max10_qsys_max10_nios_cpu --dir=/tmp/alt9816_2366828103330642614.dir/0116_cpu_gen/ --quartus_bindir=/home/admin/intelFPGA/23.1std/quartus/linux64/ --verilog --config=/tmp/alt9816_2366828103330642614.dir/0116_cpu_gen//max10_qsys_max10_nios_cpu_processor_configuration.pl --do_build_sim=0 ] 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Starting Nios II generation 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Elaborating CPU configuration settings 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Creating all objects for CPU 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Testbench 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Instruction decoding 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Instruction fields 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Instruction decodes 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Signals for RTL simulation waveforms 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Instruction controls 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:05 (*) Pipeline frontend 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:06 (*) Pipeline backend 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:06 (*) Generating RTL from CPU objects 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:06 (*) Creating plain-text RTL 2024.04.03.13:40:07 Info: cpu: # 2024.04.03 13:40:07 (*) Done Nios II generation 2024.04.03.13:40:07 Info: cpu: Done RTL generation for module 'max10_qsys_max10_nios_cpu' 2024.04.03.13:40:07 Info: cpu: "max10_nios" instantiated altera_nios2_gen2_unit "cpu" 2024.04.03.13:40:07 Info: qspi_inf_mux: "Generating: qspi_inf_mux" 2024.04.03.13:40:07 Info: inf_sc_fifo_ser_data: "Generating: inf_sc_fifo_ser_data" 2024.04.03.13:40:07 Info: qspi_inf_inst: "nios_flash" instantiated intel_generic_serial_flash_interface_if_ctrl "qspi_inf_inst" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_asmiblock.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_7_channel.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_9_channels.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_12_channels.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clk_div.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clock_devider.sv 2024.04.03.13:40:07 Info: spi_slave_avalon_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "spi_slave_avalon_master_translator" 2024.04.03.13:40:07 Info: mctp_pcievdm_buffer_avmm_ingr_slv_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "mctp_pcievdm_buffer_avmm_ingr_slv_translator" 2024.04.03.13:40:07 Info: spi_slave_avalon_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "spi_slave_avalon_master_agent" 2024.04.03.13:40:07 Info: mctp_pcievdm_buffer_avmm_ingr_slv_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "mctp_pcievdm_buffer_avmm_ingr_slv_agent" 2024.04.03.13:40:07 Info: mctp_pcievdm_buffer_avmm_ingr_slv_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "mctp_pcievdm_buffer_avmm_ingr_slv_agent_rsp_fifo" 2024.04.03.13:40:07 Warning: Overwriting different file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v 2024.04.03.13:40:07 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" 2024.04.03.13:40:07 Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001" 2024.04.03.13:40:07 Info: spi_slave_avalon_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "spi_slave_avalon_master_limiter" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v 2024.04.03.13:40:07 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" 2024.04.03.13:40:07 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" 2024.04.03.13:40:07 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter" 2024.04.03.13:40:07 Info: router: "mm_interconnect_3" instantiated altera_merlin_router "router" 2024.04.03.13:40:07 Info: router_001: "mm_interconnect_3" instantiated altera_merlin_router "router_001" 2024.04.03.13:40:07 Info: router_002: "mm_interconnect_3" instantiated altera_merlin_router "router_002" 2024.04.03.13:40:07 Info: router_003: "mm_interconnect_3" instantiated altera_merlin_router "router_003" 2024.04.03.13:40:07 Info: router_004: "mm_interconnect_3" instantiated altera_merlin_router "router_004" 2024.04.03.13:40:07 Info: router_005: "mm_interconnect_3" instantiated altera_merlin_router "router_005" 2024.04.03.13:40:07 Info: router_006: "mm_interconnect_3" instantiated altera_merlin_router "router_006" 2024.04.03.13:40:07 Info: router_007: "mm_interconnect_3" instantiated altera_merlin_router "router_007" 2024.04.03.13:40:07 Info: router_009: "mm_interconnect_3" instantiated altera_merlin_router "router_009" 2024.04.03.13:40:07 Info: router_023: "mm_interconnect_3" instantiated altera_merlin_router "router_023" 2024.04.03.13:40:07 Info: router_024: "mm_interconnect_3" instantiated altera_merlin_router "router_024" 2024.04.03.13:40:07 Info: nios_flash_avl_mem_burst_adapter: "mm_interconnect_3" instantiated altera_merlin_burst_adapter "nios_flash_avl_mem_burst_adapter" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v 2024.04.03.13:40:07 Info: cmd_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux" 2024.04.03.13:40:07 Info: cmd_demux_001: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux_001" 2024.04.03.13:40:07 Info: cmd_demux_002: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux_002" 2024.04.03.13:40:07 Info: cmd_demux_003: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux_003" 2024.04.03.13:40:07 Info: cmd_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: cmd_mux_001: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux_001" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: cmd_mux_004: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux_004" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: cmd_mux_018: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux_018" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: rsp_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux" 2024.04.03.13:40:07 Info: rsp_demux_001: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux_001" 2024.04.03.13:40:07 Info: rsp_demux_004: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux_004" 2024.04.03.13:40:07 Info: rsp_demux_006: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux_006" 2024.04.03.13:40:07 Info: rsp_demux_018: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "rsp_demux_018" 2024.04.03.13:40:07 Info: rsp_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: rsp_mux_001: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux_001" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: rsp_mux_002: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux_002" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: rsp_mux_003: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux_003" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: max10_nios_data_master_to_mctp_smbus_req_ram_s1_cmd_width_adapter: "mm_interconnect_3" instantiated altera_merlin_width_adapter "max10_nios_data_master_to_mctp_smbus_req_ram_s1_cmd_width_adapter" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2024.04.03.13:40:07 Info: crosser: "mm_interconnect_3" instantiated altera_avalon_st_handshake_clock_crosser "crosser" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v 2024.04.03.13:40:07 Info: avalon_st_adapter_018: "mm_interconnect_3" instantiated altera_avalon_st_adapter "avalon_st_adapter_018" 2024.04.03.13:40:07 Info: avst_fifo: "xip_controller" instantiated intel_generic_serial_flash_interface_xip "avst_fifo" 2024.04.03.13:40:07 Info: qspi_inf_mux: "qspi_inf_inst" instantiated intel_generic_serial_flash_interface_if_ctrl "qspi_inf_mux" 2024.04.03.13:40:07 Info: inf_sc_fifo_ser_data: "qspi_inf_inst" instantiated intel_generic_serial_flash_interface_if_ctrl "inf_sc_fifo_ser_data" 2024.04.03.13:40:07 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" 2024.04.03.13:40:07 Info: error_adapter_0: "avalon_st_adapter_018" instantiated error_adapter "error_adapter_0" 2024.04.03.13:40:07 Info: qspi_inf_mux: "qspi_inf_mux" instantiated altera_merlin_multiplexer "qspi_inf_mux" 2024.04.03.13:40:07 Info: Reusing file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv 2024.04.03.13:40:07 Info: max10_qsys: Done "max10_qsys" with 94 modules, 211 files 2024.04.03.13:40:07 Info: qsys-generate succeeded. 2024.04.03.13:40:07 Info: Finished: Create HDL design files for synthesis '/home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys_replacements/synthesis/submodules/inf_sc_fifo_ser_data.v' -> '/home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/inf_sc_fifo_ser_data.v' 2024-04-03 13:40:08 :: - done ............................................................................................... 2024-04-03 13:40:08 :: Building Bootloader BSP WARNING: Parameter value for: 'associatedAddressablePoint' is 'null' WARNING: Parameter value for: 'associatedAddressablePoint' is 'null' WARNING: Parameter value for: 'associatedAddressablePoint' is 'null' patching file drivers/src/altera_avalon_i2c.c patching file drivers/src/altera_modular_dual_adc.c patching file HAL/src/alt_iic_isr_register.c 2024-04-03 13:40:20 :: Building FW BSP WARNING: Parameter value for: 'associatedAddressablePoint' is 'null' patching file drivers/src/altera_avalon_i2c.c patching file drivers/src/altera_modular_dual_adc.c patching file HAL/src/alt_iic_isr_register.c ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:23 :: Generating FW images ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:23 :: Building Bootloader ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:24 :: Extracted Bootloader version: '0x0B' 2024-04-03 13:40:24 :: make clean all: [bmc_bootloader clean complete] Info: Building ../bmc_bootloader_bsp/ make --no-print-directory -C ../bmc_bootloader_bsp/ Compiling alt_alarm_start.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c Compiling alt_busy_sleep.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c Compiling alt_close.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_close.o HAL/src/alt_close.c Compiling alt_dcache_flush.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c Compiling alt_dcache_flush_all.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c Compiling alt_dcache_flush_no_writeback.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c Compiling alt_dev.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c Compiling alt_dma_rxchan_open.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c Compiling alt_dma_txchan_open.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c Compiling alt_ecc_fatal_exception.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_ecc_fatal_exception.o HAL/src/alt_ecc_fatal_exception.c Compiling alt_exception_entry.S... nios2-elf-gcc -MP -MMD -c -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S Compiling alt_exit.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c Compiling alt_fcntl.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c Compiling alt_fd_lock.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c Compiling alt_fd_unlock.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c Compiling alt_find_dev.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c Compiling alt_find_file.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c Compiling alt_flash_dev.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c Compiling alt_fs_reg.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c Compiling alt_fstat.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c Compiling alt_get_fd.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c Compiling alt_getchar.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c In file included from HAL/src/alt_getchar.c:36: ./system.h: In function 'alt_getchar': ./system.h:916:39: warning: 'c' may be used uninitialized [-Wmaybe-uninitialized] 916 | #define ALT_MODULE_CLASS_uart_console altera_avalon_uart | ^~~~~~~~~~~~~~~~~~ In file included from HAL/src/alt_getchar.c:37: ./system.h:916:39: note: by argument 2 of type 'const char *' to 'altera_avalon_uart_read' declared here 916 | #define ALT_MODULE_CLASS_uart_console altera_avalon_uart | ^~~~~~~~~~~~~~~~~~ ./HAL/inc/sys/alt_driver.h:76:3: note: in definition of macro 'ALT_DRIVER_FUNC_NAME2' 76 | module_class ## _ ## func | ^~~~~~~~~~~~ ./HAL/inc/sys/alt_driver.h:72:3: note: in expansion of macro 'ALT_DRIVER_FUNC_NAME1' 72 | ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func) | ^~~~~~~~~~~~~~~~~~~~~ ./HAL/inc/sys/alt_driver.h:53:36: note: in expansion of macro 'ALT_MODULE_CLASS_uart_console' 53 | #define ALT_MODULE_CLASS(instance) ALT_MODULE_CLASS_ ## instance | ^~~~~~~~~~~~~~~~~ ./HAL/inc/sys/alt_driver.h:72:25: note: in expansion of macro 'ALT_MODULE_CLASS' 72 | ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func) | ^~~~~~~~~~~~~~~~ ./HAL/inc/sys/alt_driver.h:144:16: note: in expansion of macro 'ALT_DRIVER_FUNC_NAME' 144 | extern int ALT_DRIVER_FUNC_NAME(instance, read) \ | ^~~~~~~~~~~~~~~~~~~~ HAL/src/alt_getchar.c:59:5: note: in expansion of macro 'ALT_DRIVER_READ_EXTERNS' 59 | ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); | ^~~~~~~~~~~~~~~~~~~~~~~ HAL/src/alt_getchar.c:60:10: note: 'c' declared here 60 | char c; | ^ Compiling alt_gmon.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c Compiling alt_icache_flush.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c Compiling alt_icache_flush_all.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c Compiling alt_iic.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c Compiling alt_iic_isr_register.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c Compiling alt_instruction_exception_entry.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c Compiling alt_instruction_exception_register.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c Compiling alt_io_redirect.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c Compiling alt_ioctl.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c Compiling alt_irq_entry.S... nios2-elf-gcc -MP -MMD -c -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S Compiling alt_irq_handler.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c Compiling alt_irq_register.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c Compiling alt_irq_vars.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c Compiling alt_isatty.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c Compiling alt_lseek.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c Compiling alt_main.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_main.o HAL/src/alt_main.c Compiling alt_open.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_open.o HAL/src/alt_open.c Compiling alt_putchar.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c Compiling alt_putstr.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c Compiling alt_read.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_read.o HAL/src/alt_read.c Compiling alt_release_fd.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c Compiling alt_remap_cached.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c Compiling alt_remap_uncached.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c Compiling alt_sbrk.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c Compiling alt_software_exception.S... nios2-elf-gcc -MP -MMD -c -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S Compiling alt_tick.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c Compiling alt_uncached_free.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c Compiling alt_uncached_malloc.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c Compiling alt_write.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/alt_write.o HAL/src/alt_write.c Compiling altera_nios2_gen2_irq.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/HAL/src/altera_nios2_gen2_irq.o HAL/src/altera_nios2_gen2_irq.c Compiling crt0.S... nios2-elf-gcc -MP -MMD -c -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S Compiling alt_sys_init.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/alt_sys_init.o alt_sys_init.c Compiling altera_avalon_i2c.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_i2c.o drivers/src/altera_avalon_i2c.c drivers/src/altera_avalon_i2c.c: In function 'alt_avalon_i2c_master_rx': drivers/src/altera_avalon_i2c.c:567:12: warning: 'status' may be used uninitialized [-Wmaybe-uninitialized] 567 | return status; | ^~~~~~ drivers/src/altera_avalon_i2c.c:543:32: note: 'status' was declared here 543 | ALT_AVALON_I2C_STATUS_CODE status; | ^~~~~~ drivers/src/altera_avalon_i2c.c: In function 'alt_avalon_i2c_master_tx': drivers/src/altera_avalon_i2c.c:534:12: warning: 'status' may be used uninitialized [-Wmaybe-uninitialized] 534 | return status; | ^~~~~~ drivers/src/altera_avalon_i2c.c:516:32: note: 'status' was declared here 516 | ALT_AVALON_I2C_STATUS_CODE status; | ^~~~~~ Compiling altera_avalon_timer_sc.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c Compiling altera_avalon_timer_ts.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c Compiling altera_avalon_timer_vars.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c Compiling altera_avalon_uart_fd.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c Compiling altera_avalon_uart_init.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c Compiling altera_avalon_uart_ioctl.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c Compiling altera_avalon_uart_read.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c Compiling altera_avalon_uart_write.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c Compiling altera_modular_dual_adc.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o obj/drivers/src/altera_modular_dual_adc.o drivers/src/altera_modular_dual_adc.c Creating libhal_bsp.a... rm -f -f libhal_bsp.a nios2-elf-ar -src libhal_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_ecc_fatal_entry.o obj/HAL/src/alt_ecc_fatal_exception.o obj/HAL/src/alt_env_lock.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_malloc_lock.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putcharbuf.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_gen2_irq.o obj/HAL/src/crt0.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_i2c.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_modular_dual_adc.o obj/drivers/src/altera_onchip_flash.o [BSP build complete] Info: Compiling ac_bmc_boot.c to obj/default/ac_bmc_boot.o nios2-elf-gcc -xc -MP -MMD -c -I../bmc_bootloader_bsp//HAL/inc -I../bmc_bootloader_bsp/ -I../bmc_bootloader_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o "obj/default/ac_bmc_boot.o" "ac_bmc_boot.c" ac_bmc_boot.c: In function 'jump_from_bootcopier': ac_bmc_boot.c:52:6: warning: infinite recursion detected [-Winfinite-recursion] 52 | void jump_from_bootcopier(void target(void)) | ^~~~~~~~~~~~~~~~~~~~ ac_bmc_boot.c:84:3: note: recursive call 84 | jump_from_bootcopier((void(*)(void))(NIOS2_RESET_ADDR)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Info: Compiling bmc_image_valid.c to obj/default/bmc_image_valid.o nios2-elf-gcc -xc -MP -MMD -c -I../bmc_bootloader_bsp//HAL/inc -I../bmc_bootloader_bsp/ -I../bmc_bootloader_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o "obj/default/bmc_image_valid.o" "bmc_image_valid.c" Info: Compiling intel_generic_sfi.c to obj/default/intel_generic_sfi.o nios2-elf-gcc -xc -MP -MMD -c -I../bmc_bootloader_bsp//HAL/inc -I../bmc_bootloader_bsp/ -I../bmc_bootloader_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o "obj/default/intel_generic_sfi.o" "intel_generic_sfi.c" Info: Linking bmc_bootloader.elf nios2-elf-g++ -T'../bmc_bootloader_bsp//linker.x' -msys-crt0='../bmc_bootloader_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../bmc_bootloader_bsp/ -msmallc -Wl,-Map=bmc_bootloader.map -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -o bmc_bootloader.elf obj/default/ac_bmc_boot.o obj/default/bmc_image_valid.o obj/default/intel_generic_sfi.o -lm -msys-lib=m nios2-elf-insert bmc_bootloader.elf --thread_model hal --cpu_name max10_nios --qsys true --simulation_enabled false --stderr_dev uart_console --stdin_dev uart_console --stdout_dev uart_console --sopc_system_name max10_qsys --quartus_project_dir "/home/admin/otc/ofs-bmc/fw/max10/max10_bootloader" --sopcinfo /home/admin/otc/ofs-bmc/fw/max10/max10_bootloader/design/bmc_bootloader_bsp/../../max10_qsys.sopcinfo Info: (bmc_bootloader.elf) 16 KBytes program size (code + initialized data). Info: 127 KBytes free for stack + heap. Info: Creating bmc_bootloader.objdump nios2-elf-objdump --disassemble --syms --all-header --source bmc_bootloader.elf >bmc_bootloader.objdump [bmc_bootloader build complete] 2024-04-03 13:40:26 :: make mem_init_generate: Info: Building ../bmc_bootloader_bsp/ make --no-print-directory -C ../bmc_bootloader_bsp/ [BSP build complete] Post-processing to create mem_init/fpga_flash.hex... elf2hex bmc_bootloader.elf 0x10000000 0x1fffffff --width=8 --little-endian-mem --create-lanes=0 mem_init/fpga_flash.hex Post-processing to create mem_init/max10_qsys_mctp_smbus_req_ram.hex... elf2hex bmc_bootloader.elf 0x00210000 0x002103ff --width=8 --little-endian-mem --create-lanes=0 mem_init/max10_qsys_mctp_smbus_req_ram.hex Post-processing to create mem_init/max10_qsys_mctp_smbus_resp_ram.hex... elf2hex bmc_bootloader.elf 0x00220000 0x002203ff --width=8 --little-endian-mem --create-lanes=0 mem_init/max10_qsys_mctp_smbus_resp_ram.hex Post-processing to create mem_init/nios_flash.hex... elf2hex bmc_bootloader.elf 0x04000000 0x047fffff --width=8 --little-endian-mem --create-lanes=0 mem_init/nios_flash.hex Post-processing to create mem_init/max10_onchip_flash.hex... elf2hex bmc_bootloader.elf 0x00000000 0x0015ffff --width=8 --little-endian-mem --create-lanes=0 mem_init/max10_onchip_flash.hex Post-processing to create mem_init/hdl_sim/max10_qsys_mctp_smbus_req_ram.dat... elf2dat --infile=bmc_bootloader.elf --outfile=mem_init/hdl_sim/max10_qsys_mctp_smbus_req_ram.dat \ --base=0x00210000 --end=0x002103ff --width=8 \ --little-endian-mem --create-lanes=0 Post-processing to create mem_init/hdl_sim/max10_qsys_mctp_smbus_resp_ram.dat... elf2dat --infile=bmc_bootloader.elf --outfile=mem_init/hdl_sim/max10_qsys_mctp_smbus_resp_ram.dat \ --base=0x00220000 --end=0x002203ff --width=8 \ --little-endian-mem --create-lanes=0 Post-processing to create mem_init/hdl_sim/max10_onchip_flash.dat... elf2dat --infile=bmc_bootloader.elf --outfile=mem_init/hdl_sim/max10_onchip_flash.dat \ --base=0x00000000 --end=0x0015ffff --width=32 \ --little-endian-mem --create-lanes=0 Post-processing to create mem_init/hdl_sim/max10_qsys_mctp_smbus_req_ram.sym... nios2-elf-nm -n bmc_bootloader.elf > mem_init/hdl_sim/max10_qsys_mctp_smbus_req_ram.sym Post-processing to create mem_init/hdl_sim/max10_qsys_mctp_smbus_resp_ram.sym... nios2-elf-nm -n bmc_bootloader.elf > mem_init/hdl_sim/max10_qsys_mctp_smbus_resp_ram.sym Post-processing to create mem_init/hdl_sim/max10_onchip_flash.sym... nios2-elf-nm -n bmc_bootloader.elf > mem_init/hdl_sim/max10_onchip_flash.sym Post-processing to create max10_onchip_flash.flash... elf2flash --input=bmc_bootloader.elf --output=max10_onchip_flash.flash --sim_optimize=0 --base=0x00000000 --end=0x0015ffff --reset=0x00008000 Post-processing to create mem_init/meminit.spd... Post-processing to create mem_init/meminit.qip... 2024-04-03 13:40:52 :: - done ....................BEGIN Build warnings (if any).............................................. ./system.h:916:39: warning: 'c' may be used uninitialized [-Wmaybe-uninitialized] drivers/src/altera_avalon_i2c.c:567:12: warning: 'status' may be used uninitialized [-Wmaybe-uninitialized] drivers/src/altera_avalon_i2c.c:534:12: warning: 'status' may be used uninitialized [-Wmaybe-uninitialized] ac_bmc_boot.c:52:6: warning: infinite recursion detected [-Winfinite-recursion] ....................END Build warnings (if any)................................................ 2024-04-03 13:40:52 :: Creating hex file with mif part srec_cat: mem_init/max10_onchip_flash.hex: 32786: warning: data records not in strictly ascending order (expected >= 0x100000, got 0x0000) srec_cat: mem_init/max10_onchip_flash.hex: 32786: warning: data records not in strictly ascending order (expected >= 0x100000, got 0x0000) ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:53 :: build_fw, mode=factory_retail, ver_hex=0x030f00, ver_dec=3.15.0 ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:53 :: FW: mode_str=factory_retail, ver_hex=0x030f00, cflags='-DFACTORY_BUILD -DBUILD_VERSION=8589056' [bmc_fw clean complete] Info: Building ../bmc_fw_bsp/ make --no-print-directory -C ../bmc_fw_bsp/ Compiling alt_alarm_start.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c Compiling alt_busy_sleep.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c Compiling alt_close.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_close.o HAL/src/alt_close.c Compiling alt_dcache_flush.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c Compiling alt_dcache_flush_all.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c Compiling alt_dcache_flush_no_writeback.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c Compiling alt_dev.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c Compiling alt_dma_rxchan_open.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c Compiling alt_dma_txchan_open.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c Compiling alt_ecc_fatal_exception.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_ecc_fatal_exception.o HAL/src/alt_ecc_fatal_exception.c Compiling alt_exception_entry.S... nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S Compiling alt_exit.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c Compiling alt_fcntl.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c Compiling alt_fd_lock.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c Compiling alt_fd_unlock.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c Compiling alt_find_dev.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c Compiling alt_find_file.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c Compiling alt_flash_dev.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c Compiling alt_fs_reg.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c Compiling alt_fstat.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c Compiling alt_get_fd.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c Compiling alt_gmon.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c Compiling alt_icache_flush.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c Compiling alt_icache_flush_all.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c Compiling alt_iic.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c Compiling alt_iic_isr_register.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c Compiling alt_instruction_exception_entry.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c Compiling alt_instruction_exception_register.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c Compiling alt_io_redirect.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c Compiling alt_ioctl.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c Compiling alt_irq_entry.S... nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S Compiling alt_irq_handler.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c Compiling alt_irq_register.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c Compiling alt_irq_vars.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c Compiling alt_isatty.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c Compiling alt_lseek.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c Compiling alt_main.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_main.o HAL/src/alt_main.c Compiling alt_open.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_open.o HAL/src/alt_open.c Compiling alt_read.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_read.o HAL/src/alt_read.c Compiling alt_release_fd.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c Compiling alt_remap_cached.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c Compiling alt_remap_uncached.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c Compiling alt_sbrk.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c Compiling alt_software_exception.S... nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S Compiling alt_tick.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c Compiling alt_uncached_free.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c Compiling alt_uncached_malloc.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c Compiling alt_write.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/alt_write.o HAL/src/alt_write.c Compiling altera_nios2_gen2_irq.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/HAL/src/altera_nios2_gen2_irq.o HAL/src/altera_nios2_gen2_irq.c Compiling crt0.S... nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S Compiling alt_sys_init.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/alt_sys_init.o alt_sys_init.c Compiling altera_avalon_i2c.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_i2c.o drivers/src/altera_avalon_i2c.c Compiling altera_avalon_timer_sc.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c Compiling altera_avalon_timer_ts.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c Compiling altera_avalon_timer_vars.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c Compiling altera_avalon_uart_fd.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c Compiling altera_avalon_uart_init.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c Compiling altera_avalon_uart_ioctl.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c Compiling altera_avalon_uart_read.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c Compiling altera_avalon_uart_write.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c Compiling altera_modular_dual_adc.c... nios2-elf-gcc -xc -MP -MMD -c -I./HAL/inc -I. -I./drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o obj/drivers/src/altera_modular_dual_adc.o drivers/src/altera_modular_dual_adc.c Creating libhal_bsp.a... rm -f -f libhal_bsp.a nios2-elf-ar -src libhal_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_ecc_fatal_entry.o obj/HAL/src/alt_ecc_fatal_exception.o obj/HAL/src/alt_env_lock.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_malloc_lock.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putcharbuf.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_gen2_irq.o obj/HAL/src/crt0.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_i2c.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_modular_dual_adc.o obj/drivers/src/altera_onchip_flash.o [BSP build complete] Info: Compiling src/bmc_authenticate.c to obj/default/src/bmc_authenticate.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_authenticate.o" "src/bmc_authenticate.c" Info: Compiling src/bmc_board_info.c to obj/default/src/bmc_board_info.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_board_info.o" "src/bmc_board_info.c" Info: Compiling src/bmc_dma.c to obj/default/src/bmc_dma.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_dma.o" "src/bmc_dma.c" Info: Compiling src/bmc_event_log.c to obj/default/src/bmc_event_log.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_event_log.o" "src/bmc_event_log.c" Info: Compiling src/bmc_flash_qspi.c to obj/default/src/bmc_flash_qspi.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_flash_qspi.o" "src/bmc_flash_qspi.c" Info: Compiling src/bmc_flash_wearout.c to obj/default/src/bmc_flash_wearout.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_flash_wearout.o" "src/bmc_flash_wearout.c" Info: Compiling src/bmc_fpga_img_select.c to obj/default/src/bmc_fpga_img_select.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_fpga_img_select.o" "src/bmc_fpga_img_select.c" Info: Compiling src/bmc_generic_serial_flash_controller.c to obj/default/src/bmc_generic_serial_flash_controller.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_generic_serial_flash_controller.o" "src/bmc_generic_serial_flash_controller.c" Info: Compiling src/bmc_i2c_interface.c to obj/default/src/bmc_i2c_interface.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_i2c_interface.o" "src/bmc_i2c_interface.c" Info: Compiling src/bmc_i2c_test.c to obj/default/src/bmc_i2c_test.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_i2c_test.o" "src/bmc_i2c_test.c" Info: Compiling src/bmc_ioexpander_tca9539.c to obj/default/src/bmc_ioexpander_tca9539.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_ioexpander_tca9539.o" "src/bmc_ioexpander_tca9539.c" Info: Compiling src/bmc_led_control.c to obj/default/src/bmc_led_control.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_led_control.o" "src/bmc_led_control.c" Info: Compiling src/bmc_main.c to obj/default/src/bmc_main.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_main.o" "src/bmc_main.c" Info: Compiling src/bmc_mctp_over_pcievdm.c to obj/default/src/bmc_mctp_over_pcievdm.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_mctp_over_pcievdm.o" "src/bmc_mctp_over_pcievdm.c" Info: Compiling src/bmc_mctp_over_smbus.c to obj/default/src/bmc_mctp_over_smbus.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_mctp_over_smbus.o" "src/bmc_mctp_over_smbus.c" Info: Compiling src/bmc_pdr.c to obj/default/src/bmc_pdr.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_pdr.o" "src/bmc_pdr.c" Info: Compiling src/bmc_pldm_requester.c to obj/default/src/bmc_pldm_requester.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_pldm_requester.o" "src/bmc_pldm_requester.c" Info: Compiling src/bmc_pldm_responder.c to obj/default/src/bmc_pldm_responder.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_pldm_responder.o" "src/bmc_pldm_responder.c" Info: Compiling src/bmc_pmci_ss_utils.c to obj/default/src/bmc_pmci_ss_utils.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_pmci_ss_utils.o" "src/bmc_pmci_ss_utils.c" Info: Compiling src/bmc_power_event_handler.c to obj/default/src/bmc_power_event_handler.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_power_event_handler.o" "src/bmc_power_event_handler.c" Info: Compiling src/bmc_rsu.c to obj/default/src/bmc_rsu.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_rsu.o" "src/bmc_rsu.c" Info: Compiling src/bmc_sdm_commands.c to obj/default/src/bmc_sdm_commands.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sdm_commands.o" "src/bmc_sdm_commands.c" Info: Compiling src/bmc_sdm_efuse_programmer.c to obj/default/src/bmc_sdm_efuse_programmer.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sdm_efuse_programmer.o" "src/bmc_sdm_efuse_programmer.c" Info: Compiling src/bmc_sdm_jtag_interface.c to obj/default/src/bmc_sdm_jtag_interface.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sdm_jtag_interface.o" "src/bmc_sdm_jtag_interface.c" Info: Compiling src/bmc_sensor_adc.c to obj/default/src/bmc_sensor_adc.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_adc.o" "src/bmc_sensor_adc.c" Info: Compiling src/bmc_sensor_alert_handling.c to obj/default/src/bmc_sensor_alert_handling.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_alert_handling.o" "src/bmc_sensor_alert_handling.c" Info: Compiling src/bmc_sensor_ed8401.c to obj/default/src/bmc_sensor_ed8401.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_ed8401.o" "src/bmc_sensor_ed8401.c" Info: Compiling src/bmc_sensor_fpgadts.c to obj/default/src/bmc_sensor_fpgadts.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_fpgadts.o" "src/bmc_sensor_fpgadts.c" Info: Compiling src/bmc_sensor_ina3221.c to obj/default/src/bmc_sensor_ina3221.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_ina3221.o" "src/bmc_sensor_ina3221.c" Info: Compiling src/bmc_sensor_ir3806x.c to obj/default/src/bmc_sensor_ir3806x.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_ir3806x.o" "src/bmc_sensor_ir3806x.c" Info: Compiling src/bmc_sensor_isl68220.c to obj/default/src/bmc_sensor_isl68220.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_isl68220.o" "src/bmc_sensor_isl68220.c" Info: Compiling src/bmc_sensor_qsfp.c to obj/default/src/bmc_sensor_qsfp.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_qsfp.o" "src/bmc_sensor_qsfp.c" Info: Compiling src/bmc_sensor_tmp464.c to obj/default/src/bmc_sensor_tmp464.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensor_tmp464.o" "src/bmc_sensor_tmp464.c" Info: Compiling src/bmc_sensors.c to obj/default/src/bmc_sensors.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensors.o" "src/bmc_sensors.c" Info: Compiling src/bmc_sensors_info.c to obj/default/src/bmc_sensors_info.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensors_info.o" "src/bmc_sensors_info.c" Info: Compiling src/bmc_sensors_states.c to obj/default/src/bmc_sensors_states.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_sensors_states.o" "src/bmc_sensors_states.c" Info: Compiling src/bmc_smbus_custom.c to obj/default/src/bmc_smbus_custom.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_smbus_custom.o" "src/bmc_smbus_custom.c" Info: Compiling src/bmc_spi_egress_if.c to obj/default/src/bmc_spi_egress_if.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_spi_egress_if.o" "src/bmc_spi_egress_if.c" Info: Compiling src/bmc_tests.c to obj/default/src/bmc_tests.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_tests.o" "src/bmc_tests.c" Info: Compiling src/bmc_thresholds.c to obj/default/src/bmc_thresholds.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_thresholds.o" "src/bmc_thresholds.c" Info: Compiling src/bmc_timer_event_handler.c to obj/default/src/bmc_timer_event_handler.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_timer_event_handler.o" "src/bmc_timer_event_handler.c" Info: Compiling src/bmc_utils.c to obj/default/src/bmc_utils.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_utils.o" "src/bmc_utils.c" Info: Compiling src/bmc_virtual_sensors.c to obj/default/src/bmc_virtual_sensors.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_virtual_sensors.o" "src/bmc_virtual_sensors.c" Info: Compiling src/bmc_workload_thresholds.c to obj/default/src/bmc_workload_thresholds.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o "obj/default/src/bmc_workload_thresholds.o" "src/bmc_workload_thresholds.c" Info: Assembling flash_entry.S to obj/default/flash_entry.o nios2-elf-gcc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -Wa,-Iinc -Wa,-I../bmc_fw_bsp//HAL/inc -Wa,-I../bmc_fw_bsp/ -Wa,-I../bmc_fw_bsp//drivers/inc -Wa,-gdwarf2 -o "obj/default/flash_entry.o" "flash_entry.S" Info: Linking bmc_fw.elf nios2-elf-g++ -T'../bmc_fw_bsp//linker.x' -msys-crt0='../bmc_fw_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../bmc_fw_bsp/ -Wl,-Map=bmc_fw.map -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DFACTORY_BUILD -DBUILD_VERSION=8589056 -o bmc_fw.elf obj/default/src/bmc_authenticate.o obj/default/src/bmc_board_info.o obj/default/src/bmc_dma.o obj/default/src/bmc_event_log.o obj/default/src/bmc_flash_qspi.o obj/default/src/bmc_flash_wearout.o obj/default/src/bmc_fpga_img_select.o obj/default/src/bmc_generic_serial_flash_controller.o obj/default/src/bmc_i2c_interface.o obj/default/src/bmc_i2c_test.o obj/default/src/bmc_ioexpander_tca9539.o obj/default/src/bmc_led_control.o obj/default/src/bmc_main.o obj/default/src/bmc_mctp_over_pcievdm.o obj/default/src/bmc_mctp_over_smbus.o obj/default/src/bmc_pdr.o obj/default/src/bmc_pldm_requester.o obj/default/src/bmc_pldm_responder.o obj/default/src/bmc_pmci_ss_utils.o obj/default/src/bmc_power_event_handler.o obj/default/src/bmc_rsu.o obj/default/src/bmc_sdm_commands.o obj/default/src/bmc_sdm_efuse_programmer.o obj/default/src/bmc_sdm_jtag_interface.o obj/default/src/bmc_sensor_adc.o obj/default/src/bmc_sensor_alert_handling.o obj/default/src/bmc_sensor_ed8401.o obj/default/src/bmc_sensor_fpgadts.o obj/default/src/bmc_sensor_ina3221.o obj/default/src/bmc_sensor_ir3806x.o obj/default/src/bmc_sensor_isl68220.o obj/default/src/bmc_sensor_qsfp.o obj/default/src/bmc_sensor_tmp464.o obj/default/src/bmc_sensors.o obj/default/src/bmc_sensors_info.o obj/default/src/bmc_sensors_states.o obj/default/src/bmc_smbus_custom.o obj/default/src/bmc_spi_egress_if.o obj/default/src/bmc_tests.o obj/default/src/bmc_thresholds.o obj/default/src/bmc_timer_event_handler.o obj/default/src/bmc_utils.o obj/default/src/bmc_virtual_sensors.o obj/default/src/bmc_workload_thresholds.o obj/default/flash_entry.o -lm -msys-lib=m /home/admin/Complete/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/12.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: warning: bmc_fw.elf has a LOAD segment with RWX permissions nios2-elf-insert bmc_fw.elf --thread_model hal --cpu_name max10_nios --qsys true --simulation_enabled false --stderr_dev uart_console --stdin_dev uart_console --stdout_dev uart_console --sopc_system_name max10_qsys --quartus_project_dir "/home/admin/otc/ofs-bmc/fw/max10/max10_bmc_fw" --sopcinfo /home/admin/otc/ofs-bmc/fw/max10/max10_bmc_fw/design/bmc_fw_bsp/../../max10_qsys.sopcinfo Info: (bmc_fw.elf) 251 KBytes program size (code + initialized data). Info: 7940 KBytes free for stack + heap. Info: Creating bmc_fw.objdump nios2-elf-objdump --disassemble --syms --all-header --source bmc_fw.elf >bmc_fw.objdump [bmc_fw build complete] ....................BEGIN Build warnings (if any).............................................. /home/admin/Complete/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/12.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: warning: bmc_fw.elf has a LOAD segment with RWX permissions ....................END Build warnings (if any)................................................ nios2-elf-strip: bmc_fw_factory_retail.elf.tmp.elf: warning: empty loadable segment detected at vaddr=0x8000, is this intentional? Script completed successfully. ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:57 :: build_fw, mode=user_retail, ver_hex=0x030f00, ver_dec=3.15.0 ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:57 :: FW: mode_str=user_retail, ver_hex=0x030f00, cflags='-DBUILD_VERSION=0x030f00' [bmc_fw clean complete] Info: Building ../bmc_fw_bsp/ make --no-print-directory -C ../bmc_fw_bsp/ [BSP build complete] Info: Compiling src/bmc_authenticate.c to obj/default/src/bmc_authenticate.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_authenticate.o" "src/bmc_authenticate.c" Info: Compiling src/bmc_board_info.c to obj/default/src/bmc_board_info.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_board_info.o" "src/bmc_board_info.c" Info: Compiling src/bmc_dma.c to obj/default/src/bmc_dma.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_dma.o" "src/bmc_dma.c" Info: Compiling src/bmc_event_log.c to obj/default/src/bmc_event_log.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_event_log.o" "src/bmc_event_log.c" Info: Compiling src/bmc_flash_qspi.c to obj/default/src/bmc_flash_qspi.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_flash_qspi.o" "src/bmc_flash_qspi.c" Info: Compiling src/bmc_flash_wearout.c to obj/default/src/bmc_flash_wearout.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_flash_wearout.o" "src/bmc_flash_wearout.c" Info: Compiling src/bmc_fpga_img_select.c to obj/default/src/bmc_fpga_img_select.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_fpga_img_select.o" "src/bmc_fpga_img_select.c" Info: Compiling src/bmc_generic_serial_flash_controller.c to obj/default/src/bmc_generic_serial_flash_controller.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_generic_serial_flash_controller.o" "src/bmc_generic_serial_flash_controller.c" Info: Compiling src/bmc_i2c_interface.c to obj/default/src/bmc_i2c_interface.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_i2c_interface.o" "src/bmc_i2c_interface.c" Info: Compiling src/bmc_i2c_test.c to obj/default/src/bmc_i2c_test.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_i2c_test.o" "src/bmc_i2c_test.c" Info: Compiling src/bmc_ioexpander_tca9539.c to obj/default/src/bmc_ioexpander_tca9539.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_ioexpander_tca9539.o" "src/bmc_ioexpander_tca9539.c" Info: Compiling src/bmc_led_control.c to obj/default/src/bmc_led_control.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_led_control.o" "src/bmc_led_control.c" Info: Compiling src/bmc_main.c to obj/default/src/bmc_main.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_main.o" "src/bmc_main.c" Info: Compiling src/bmc_mctp_over_pcievdm.c to obj/default/src/bmc_mctp_over_pcievdm.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_mctp_over_pcievdm.o" "src/bmc_mctp_over_pcievdm.c" Info: Compiling src/bmc_mctp_over_smbus.c to obj/default/src/bmc_mctp_over_smbus.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_mctp_over_smbus.o" "src/bmc_mctp_over_smbus.c" Info: Compiling src/bmc_pdr.c to obj/default/src/bmc_pdr.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_pdr.o" "src/bmc_pdr.c" Info: Compiling src/bmc_pldm_requester.c to obj/default/src/bmc_pldm_requester.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_pldm_requester.o" "src/bmc_pldm_requester.c" Info: Compiling src/bmc_pldm_responder.c to obj/default/src/bmc_pldm_responder.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_pldm_responder.o" "src/bmc_pldm_responder.c" Info: Compiling src/bmc_pmci_ss_utils.c to obj/default/src/bmc_pmci_ss_utils.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_pmci_ss_utils.o" "src/bmc_pmci_ss_utils.c" Info: Compiling src/bmc_power_event_handler.c to obj/default/src/bmc_power_event_handler.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_power_event_handler.o" "src/bmc_power_event_handler.c" Info: Compiling src/bmc_rsu.c to obj/default/src/bmc_rsu.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_rsu.o" "src/bmc_rsu.c" Info: Compiling src/bmc_sdm_commands.c to obj/default/src/bmc_sdm_commands.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sdm_commands.o" "src/bmc_sdm_commands.c" Info: Compiling src/bmc_sdm_efuse_programmer.c to obj/default/src/bmc_sdm_efuse_programmer.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sdm_efuse_programmer.o" "src/bmc_sdm_efuse_programmer.c" Info: Compiling src/bmc_sdm_jtag_interface.c to obj/default/src/bmc_sdm_jtag_interface.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sdm_jtag_interface.o" "src/bmc_sdm_jtag_interface.c" Info: Compiling src/bmc_sensor_adc.c to obj/default/src/bmc_sensor_adc.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_adc.o" "src/bmc_sensor_adc.c" Info: Compiling src/bmc_sensor_alert_handling.c to obj/default/src/bmc_sensor_alert_handling.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_alert_handling.o" "src/bmc_sensor_alert_handling.c" Info: Compiling src/bmc_sensor_ed8401.c to obj/default/src/bmc_sensor_ed8401.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_ed8401.o" "src/bmc_sensor_ed8401.c" Info: Compiling src/bmc_sensor_fpgadts.c to obj/default/src/bmc_sensor_fpgadts.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_fpgadts.o" "src/bmc_sensor_fpgadts.c" Info: Compiling src/bmc_sensor_ina3221.c to obj/default/src/bmc_sensor_ina3221.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_ina3221.o" "src/bmc_sensor_ina3221.c" Info: Compiling src/bmc_sensor_ir3806x.c to obj/default/src/bmc_sensor_ir3806x.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_ir3806x.o" "src/bmc_sensor_ir3806x.c" Info: Compiling src/bmc_sensor_isl68220.c to obj/default/src/bmc_sensor_isl68220.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_isl68220.o" "src/bmc_sensor_isl68220.c" Info: Compiling src/bmc_sensor_qsfp.c to obj/default/src/bmc_sensor_qsfp.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_qsfp.o" "src/bmc_sensor_qsfp.c" Info: Compiling src/bmc_sensor_tmp464.c to obj/default/src/bmc_sensor_tmp464.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensor_tmp464.o" "src/bmc_sensor_tmp464.c" Info: Compiling src/bmc_sensors.c to obj/default/src/bmc_sensors.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensors.o" "src/bmc_sensors.c" Info: Compiling src/bmc_sensors_info.c to obj/default/src/bmc_sensors_info.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensors_info.o" "src/bmc_sensors_info.c" Info: Compiling src/bmc_sensors_states.c to obj/default/src/bmc_sensors_states.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_sensors_states.o" "src/bmc_sensors_states.c" Info: Compiling src/bmc_smbus_custom.c to obj/default/src/bmc_smbus_custom.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_smbus_custom.o" "src/bmc_smbus_custom.c" Info: Compiling src/bmc_spi_egress_if.c to obj/default/src/bmc_spi_egress_if.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_spi_egress_if.o" "src/bmc_spi_egress_if.c" Info: Compiling src/bmc_tests.c to obj/default/src/bmc_tests.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_tests.o" "src/bmc_tests.c" Info: Compiling src/bmc_thresholds.c to obj/default/src/bmc_thresholds.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_thresholds.o" "src/bmc_thresholds.c" Info: Compiling src/bmc_timer_event_handler.c to obj/default/src/bmc_timer_event_handler.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_timer_event_handler.o" "src/bmc_timer_event_handler.c" Info: Compiling src/bmc_utils.c to obj/default/src/bmc_utils.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_utils.o" "src/bmc_utils.c" Info: Compiling src/bmc_virtual_sensors.c to obj/default/src/bmc_virtual_sensors.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_virtual_sensors.o" "src/bmc_virtual_sensors.c" Info: Compiling src/bmc_workload_thresholds.c to obj/default/src/bmc_workload_thresholds.o nios2-elf-gcc -xc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o "obj/default/src/bmc_workload_thresholds.o" "src/bmc_workload_thresholds.c" Info: Assembling flash_entry.S to obj/default/flash_entry.o nios2-elf-gcc -MP -MMD -c -Iinc -I../bmc_fw_bsp//HAL/inc -I../bmc_fw_bsp/ -I../bmc_fw_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -Wa,-Iinc -Wa,-I../bmc_fw_bsp//HAL/inc -Wa,-I../bmc_fw_bsp/ -Wa,-I../bmc_fw_bsp//drivers/inc -Wa,-gdwarf2 -o "obj/default/flash_entry.o" "flash_entry.S" Info: Linking bmc_fw.elf nios2-elf-g++ -T'../bmc_fw_bsp//linker.x' -msys-crt0='../bmc_fw_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../bmc_fw_bsp/ -Wl,-Map=bmc_fw.map -O0 -g -Wall -fstack-protector-strong -Wformat -Wformat-security -mno-hw-div -mno-hw-div -mhw-mul -mno-hw-mulx -mgpopt=global -DBUILD_VERSION=0x030f00 -o bmc_fw.elf obj/default/src/bmc_authenticate.o obj/default/src/bmc_board_info.o obj/default/src/bmc_dma.o obj/default/src/bmc_event_log.o obj/default/src/bmc_flash_qspi.o obj/default/src/bmc_flash_wearout.o obj/default/src/bmc_fpga_img_select.o obj/default/src/bmc_generic_serial_flash_controller.o obj/default/src/bmc_i2c_interface.o obj/default/src/bmc_i2c_test.o obj/default/src/bmc_ioexpander_tca9539.o obj/default/src/bmc_led_control.o obj/default/src/bmc_main.o obj/default/src/bmc_mctp_over_pcievdm.o obj/default/src/bmc_mctp_over_smbus.o obj/default/src/bmc_pdr.o obj/default/src/bmc_pldm_requester.o obj/default/src/bmc_pldm_responder.o obj/default/src/bmc_pmci_ss_utils.o obj/default/src/bmc_power_event_handler.o obj/default/src/bmc_rsu.o obj/default/src/bmc_sdm_commands.o obj/default/src/bmc_sdm_efuse_programmer.o obj/default/src/bmc_sdm_jtag_interface.o obj/default/src/bmc_sensor_adc.o obj/default/src/bmc_sensor_alert_handling.o obj/default/src/bmc_sensor_ed8401.o obj/default/src/bmc_sensor_fpgadts.o obj/default/src/bmc_sensor_ina3221.o obj/default/src/bmc_sensor_ir3806x.o obj/default/src/bmc_sensor_isl68220.o obj/default/src/bmc_sensor_qsfp.o obj/default/src/bmc_sensor_tmp464.o obj/default/src/bmc_sensors.o obj/default/src/bmc_sensors_info.o obj/default/src/bmc_sensors_states.o obj/default/src/bmc_smbus_custom.o obj/default/src/bmc_spi_egress_if.o obj/default/src/bmc_tests.o obj/default/src/bmc_thresholds.o obj/default/src/bmc_timer_event_handler.o obj/default/src/bmc_utils.o obj/default/src/bmc_virtual_sensors.o obj/default/src/bmc_workload_thresholds.o obj/default/flash_entry.o -lm -msys-lib=m /home/admin/Complete/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/12.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: warning: bmc_fw.elf has a LOAD segment with RWX permissions nios2-elf-insert bmc_fw.elf --thread_model hal --cpu_name max10_nios --qsys true --simulation_enabled false --stderr_dev uart_console --stdin_dev uart_console --stdout_dev uart_console --sopc_system_name max10_qsys --quartus_project_dir "/home/admin/otc/ofs-bmc/fw/max10/max10_bmc_fw" --sopcinfo /home/admin/otc/ofs-bmc/fw/max10/max10_bmc_fw/design/bmc_fw_bsp/../../max10_qsys.sopcinfo Info: (bmc_fw.elf) 251 KBytes program size (code + initialized data). Info: 7940 KBytes free for stack + heap. Info: Creating bmc_fw.objdump nios2-elf-objdump --disassemble --syms --all-header --source bmc_fw.elf >bmc_fw.objdump [bmc_fw build complete] ....................BEGIN Build warnings (if any).............................................. /home/admin/Complete/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/bin/../lib/gcc/nios2-elf/12.3.1/../../../../../H-x86_64-pc-linux-gnu/nios2-elf/bin/ld: warning: bmc_fw.elf has a LOAD segment with RWX permissions ....................END Build warnings (if any)................................................ nios2-elf-strip: bmc_fw_user_retail.elf.tmp.elf: warning: empty loadable segment detected at vaddr=0x8000, is this intentional? Script completed successfully. ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:59 :: Generating RTL images ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:40:59 :: Regenerating IPs 2024.04.03.13:41:06 Info: Saving generation log to /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/pfl_ii_generation.rpt 2024.04.03.13:41:06 Info: Starting: Create simulation model 2024.04.03.13:41:06 Info: qsys-generate /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation --family="MAX 10" --part=10M50DAF256I7G 2024.04.03.13:41:06 Info: Loading pfl_ii/pfl_ii.qsys 2024.04.03.13:41:06 Info: Reading input file 2024.04.03.13:41:06 Info: Adding parallel_flash_loader_2_0 [altera_parallel_flash_loader_2 23.1] 2024.04.03.13:41:06 Info: Parameterizing module parallel_flash_loader_2_0 2024.04.03.13:41:06 Info: Building connections 2024.04.03.13:41:06 Info: Parameterizing connections 2024.04.03.13:41:06 Info: Validating 2024.04.03.13:41:06 Info: Done reading input file 2024.04.03.13:41:06 Info: pfl_ii: Generating pfl_ii "pfl_ii" for SIM_VERILOG 2024.04.03.13:41:06 Info: parallel_flash_loader_2_0: generating top-level entity altera_parallel_flash_loader_2 2024.04.03.13:41:06 Info: altera_pfl2_data_format_adapter: "Generating: altera_pfl2_data_format_adapter" 2024.04.03.13:41:06 Info: altera_pfl2_timing_adapter: "Generating: altera_pfl2_timing_adapter" 2024.04.03.13:41:06 Info: parallel_flash_loader_2_0: "pfl_ii" instantiated altera_parallel_flash_loader_2 "parallel_flash_loader_2_0" 2024.04.03.13:41:06 Info: altera_pfl2_data_format_adapter: "parallel_flash_loader_2_0" instantiated altera_parallel_flash_loader_2 "altera_pfl2_data_format_adapter" 2024.04.03.13:41:06 Info: altera_pfl2_timing_adapter: "parallel_flash_loader_2_0" instantiated altera_parallel_flash_loader_2 "altera_pfl2_timing_adapter" 2024.04.03.13:41:06 Info: altera_pfl2_data_format_adapter: "altera_pfl2_data_format_adapter" instantiated altera_pfl2_data_format_adapter "altera_pfl2_data_format_adapter" 2024.04.03.13:41:06 Info: altera_pfl2_timing_adapter: "altera_pfl2_timing_adapter" instantiated timing_adapter "altera_pfl2_timing_adapter" 2024.04.03.13:41:06 Info: pfl_ii: Done "pfl_ii" with 6 modules, 15 files 2024.04.03.13:41:06 Info: qsys-generate succeeded. 2024.04.03.13:41:06 Info: Finished: Create simulation model 2024.04.03.13:41:06 Info: Starting: Create Modelsim Project. 2024.04.03.13:41:06 Info: sim-script-gen --spd=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/pfl_ii.spd --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation/ --use-relative-paths=true 2024.04.03.13:41:06 Info: Doing: ip-make-simscript --spd=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/pfl_ii.spd --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation/ --use-relative-paths=true 2024.04.03.13:41:10 Info: Generating the following file(s) for XCELIUM simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation/ directory: 2024.04.03.13:41:10 Info: xcelium/cds.lib 2024.04.03.13:41:11 Info: xcelium/hdl.var 2024.04.03.13:41:11 Info: xcelium/xcelium_setup.sh 2024.04.03.13:41:11 Info: 3 .cds.lib files in xcelium/cds_libs/ directory 2024.04.03.13:41:11 Info: Generating the following file(s) for VCS simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation/ directory: 2024.04.03.13:41:11 Info: synopsys/vcs/vcs_setup.sh 2024.04.03.13:41:11 Info: Generating the following file(s) for MODELSIM simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation/ directory: 2024.04.03.13:41:11 Info: mentor/msim_setup.tcl 2024.04.03.13:41:11 Info: Generating the following file(s) for RIVIERA simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation/ directory: 2024.04.03.13:41:11 Info: aldec/rivierapro_setup.tcl 2024.04.03.13:41:11 Info: Generating the following file(s) for VCSMX simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation/ directory: 2024.04.03.13:41:11 Info: synopsys/vcsmx/synopsys_sim.setup 2024.04.03.13:41:11 Info: synopsys/vcsmx/vcsmx_setup.sh 2024.04.03.13:41:11 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/simulation/. 2024.04.03.13:41:11 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. 2024.04.03.13:41:11 Info: Finished: Create Modelsim Project. 2024.04.03.13:41:11 Info: 2024.04.03.13:41:11 Info: Starting: Create HDL design files for synthesis 2024.04.03.13:41:11 Info: qsys-generate /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii.qsys --synthesis=VERILOG --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis --family="MAX 10" --part=10M50DAF256I7G 2024.04.03.13:41:11 Info: Loading pfl_ii/pfl_ii.qsys 2024.04.03.13:41:11 Info: Reading input file 2024.04.03.13:41:11 Info: Adding parallel_flash_loader_2_0 [altera_parallel_flash_loader_2 23.1] 2024.04.03.13:41:11 Info: Parameterizing module parallel_flash_loader_2_0 2024.04.03.13:41:11 Info: Building connections 2024.04.03.13:41:11 Info: Parameterizing connections 2024.04.03.13:41:11 Info: Validating 2024.04.03.13:41:11 Info: Done reading input file 2024.04.03.13:41:11 Info: pfl_ii: Generating pfl_ii "pfl_ii" for QUARTUS_SYNTH 2024.04.03.13:41:11 Info: parallel_flash_loader_2_0: generating top-level entity altera_parallel_flash_loader_2 2024.04.03.13:41:11 Info: altera_pfl2_data_format_adapter: "Generating: altera_pfl2_data_format_adapter" 2024.04.03.13:41:11 Info: altera_pfl2_timing_adapter: "Generating: altera_pfl2_timing_adapter" 2024.04.03.13:41:11 Info: parallel_flash_loader_2_0: "pfl_ii" instantiated altera_parallel_flash_loader_2 "parallel_flash_loader_2_0" 2024.04.03.13:41:11 Info: altera_pfl2_data_format_adapter: "parallel_flash_loader_2_0" instantiated altera_parallel_flash_loader_2 "altera_pfl2_data_format_adapter" 2024.04.03.13:41:11 Info: altera_pfl2_timing_adapter: "parallel_flash_loader_2_0" instantiated altera_parallel_flash_loader_2 "altera_pfl2_timing_adapter" 2024.04.03.13:41:11 Info: altera_pfl2_data_format_adapter: "altera_pfl2_data_format_adapter" instantiated altera_pfl2_data_format_adapter "altera_pfl2_data_format_adapter" 2024.04.03.13:41:11 Info: altera_pfl2_timing_adapter: "altera_pfl2_timing_adapter" instantiated timing_adapter "altera_pfl2_timing_adapter" 2024.04.03.13:41:11 Info: pfl_ii: Done "pfl_ii" with 6 modules, 15 files 2024.04.03.13:41:11 Info: qsys-generate succeeded. 2024.04.03.13:41:11 Info: Finished: Create HDL design files for synthesis 2024.04.03.13:41:13 Info: Saving generation log to /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/svid_i2c_master_generation.rpt 2024.04.03.13:41:13 Info: Starting: Create simulation model 2024.04.03.13:41:13 Info: qsys-generate /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation --family="MAX 10" --part=10M50DAF256I7G 2024.04.03.13:41:13 Info: Loading svid_i2c_master/svid_i2c_master.qsys 2024.04.03.13:41:13 Info: Reading input file 2024.04.03.13:41:13 Info: Adding i2cm [altera_avalon_i2c 23.1] 2024.04.03.13:41:13 Info: Parameterizing module i2cm 2024.04.03.13:41:13 Info: Building connections 2024.04.03.13:41:13 Info: Parameterizing connections 2024.04.03.13:41:13 Info: Validating 2024.04.03.13:41:13 Info: Done reading input file 2024.04.03.13:41:13 Info: svid_i2c_master: Generating svid_i2c_master "svid_i2c_master" for SIM_VERILOG 2024.04.03.13:41:13 Info: i2cm: "svid_i2c_master" instantiated altera_avalon_i2c "i2cm" 2024.04.03.13:41:13 Info: svid_i2c_master: Done "svid_i2c_master" with 2 modules, 12 files 2024.04.03.13:41:13 Info: qsys-generate succeeded. 2024.04.03.13:41:13 Info: Finished: Create simulation model 2024.04.03.13:41:13 Info: Starting: Create Modelsim Project. 2024.04.03.13:41:13 Info: sim-script-gen --spd=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/svid_i2c_master.spd --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation/ --use-relative-paths=true 2024.04.03.13:41:13 Info: Doing: ip-make-simscript --spd=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/svid_i2c_master.spd --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation/ --use-relative-paths=true 2024.04.03.13:41:14 Info: Generating the following file(s) for XCELIUM simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation/ directory: 2024.04.03.13:41:14 Info: xcelium/cds.lib 2024.04.03.13:41:14 Info: xcelium/hdl.var 2024.04.03.13:41:14 Info: xcelium/xcelium_setup.sh 2024.04.03.13:41:14 Info: 1 .cds.lib files in xcelium/cds_libs/ directory 2024.04.03.13:41:14 Info: Generating the following file(s) for VCS simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation/ directory: 2024.04.03.13:41:14 Info: synopsys/vcs/vcs_setup.sh 2024.04.03.13:41:14 Info: Generating the following file(s) for RIVIERA simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation/ directory: 2024.04.03.13:41:14 Info: aldec/rivierapro_setup.tcl 2024.04.03.13:41:14 Info: Generating the following file(s) for MODELSIM simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation/ directory: 2024.04.03.13:41:14 Info: mentor/msim_setup.tcl 2024.04.03.13:41:14 Info: Generating the following file(s) for VCSMX simulator in /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation/ directory: 2024.04.03.13:41:14 Info: synopsys/vcsmx/synopsys_sim.setup 2024.04.03.13:41:14 Info: synopsys/vcsmx/vcsmx_setup.sh 2024.04.03.13:41:14 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/simulation/. 2024.04.03.13:41:14 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. 2024.04.03.13:41:14 Info: Finished: Create Modelsim Project. 2024.04.03.13:41:14 Info: 2024.04.03.13:41:14 Info: Starting: Create HDL design files for synthesis 2024.04.03.13:41:14 Info: qsys-generate /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master.qsys --synthesis=VERILOG --output-directory=/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis --family="MAX 10" --part=10M50DAF256I7G 2024.04.03.13:41:14 Info: Loading svid_i2c_master/svid_i2c_master.qsys 2024.04.03.13:41:14 Info: Reading input file 2024.04.03.13:41:14 Info: Adding i2cm [altera_avalon_i2c 23.1] 2024.04.03.13:41:14 Info: Parameterizing module i2cm 2024.04.03.13:41:14 Info: Building connections 2024.04.03.13:41:14 Info: Parameterizing connections 2024.04.03.13:41:14 Info: Validating 2024.04.03.13:41:14 Info: Done reading input file 2024.04.03.13:41:14 Info: svid_i2c_master: Generating svid_i2c_master "svid_i2c_master" for QUARTUS_SYNTH 2024.04.03.13:41:14 Info: i2cm: "svid_i2c_master" instantiated altera_avalon_i2c "i2cm" 2024.04.03.13:41:14 Info: svid_i2c_master: Done "svid_i2c_master" with 2 modules, 12 files 2024.04.03.13:41:14 Info: qsys-generate succeeded. 2024.04.03.13:41:14 Info: Finished: Create HDL design files for synthesis '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs_replacement/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v' -> '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v' '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs_replacement/pfl_ii/pfl_ii/synthesis/pfl_ii.v' -> '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/pfl_ii.v' '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs_replacement/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v' -> '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v' '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs_replacement/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v' -> '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v' '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs_replacement/svid_i2c_master/svid_i2c_master/synthesis/svid_i2c_master.v' -> '/home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/svid_i2c_master.v' 2024-04-03 13:41:14 :: - done ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:41:14 :: .. Building RTL .. mode=factory ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:41:14 :: rtl_revision=3.15.0, ver_hex=0x030f00 2024-04-03 13:41:14 :: rtl_set_factory: 1 2024-04-03 13:41:14 :: rtl_set_debug: 0 2024-04-03 13:41:14 :: Setting PROD_RELEASE to YES 2024-04-03 13:41:14 :: rtl_set_jtag: 0 2024-04-03 13:41:14 :: rtl_set_fruid: 0 2024-04-03 13:41:14 :: Setting FRUID_EEPROM_WP_ENABLE to YES 2024-04-03 13:41:14 :: Setting ENABLE_FLASH_FILTER to YES 2024-04-03 13:41:14 :: RTL: image_str=_factory, ver_hex=0x830f00, rtl_revision=3.15.0 2024-04-03 13:41:14 :: Running Synthesis... Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 13:41:16 2024 Info: Command: quartus_map acadp_bmc_max10 --rev=acadp_bmc_max10_factory Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Info (12023): Found entity 1: ram_sdp File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Info (12023): Found entity 1: jtag_cntrlr File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/jtag_ctrl_io_if.sv Info (12023): Found entity 1: jtag_ctrl_io_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/jtag_ctrl_io_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_jtg_ctrl_if.sv Info (12023): Found entity 1: csr_jtg_ctrl_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_jtg_ctrl_if.sv Line: 21 Info (12021): Found 1 design units, including 0 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/pkg_global.sv Info (12022): Found design unit 1: pkg_global (SystemVerilog) File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/pkg_global.sv Line: 22 Info (12021): Found 1 design units, including 0 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_smbus_pkg.sv Info (12022): Found design unit 1: mctp_smbus_pkg (SystemVerilog) File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_smbus_pkg.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_crc.v Info (12023): Found entity 1: smbus_crc File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_crc.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Info (12023): Found entity 1: smbus_arp_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Info (12023): Found entity 1: pldm_over_mctp_top_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Info (12023): Found entity 1: pldm_over_mctp_resp_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Info (12023): Found entity 1: pldm_over_mctp_req_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_slow_clk_pulse.v Info (12023): Found entity 1: mctp_slow_clk_pulse File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_slow_clk_pulse.v Line: 3 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Info (12023): Found entity 1: mctp_debouncer File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_over_smbus.sv Info (12023): Found entity 1: mctp_over_smbus File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_over_smbus.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_qspi_filter.sv Info (12023): Found entity 1: fpga_qspi_filter File: /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_qspi_filter.sv Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_flash_if_ctrl.sv Info (12023): Found entity 1: fpga_flash_if_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_flash_if_ctrl.sv Line: 48 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Info (12023): Found entity 1: power_sequencer File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Info (12023): Found entity 1: fpga_config_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Info (12023): Found entity 1: flow_control_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_io_if.sv Info (12023): Found entity 1: csr_io_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_io_if.sv Line: 21 Info (12021): Found 1 design units, including 0 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/csr/pkg_csr.sv Info (12022): Found design unit 1: pkg_csr (SystemVerilog) File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/pkg_csr.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Info (12023): Found entity 1: csr_ram File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Info (12023): Found entity 1: csr_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/common/debouncer.sv Info (12023): Found entity 1: debouncer File: /home/admin/otc/ofs-bmc/rtl/max10/design/common/debouncer.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/common/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut File: /home/admin/otc/ofs-bmc/rtl/max10/design/common/altera_std_synchronizer_nocut.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/common/bmc_sync.sv Info (12023): Found entity 1: bmc_sync File: /home/admin/otc/ofs-bmc/rtl/max10/design/common/bmc_sync.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Info (12023): Found entity 1: clk_rst_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/pwr_seq_brd_if.sv Info (12023): Found entity 1: pwr_seq_brd_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/pwr_seq_brd_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_pwr_seq_if.sv Info (12023): Found entity 1: csr_pwr_seq_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_pwr_seq_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_fconfig_if.sv Info (12023): Found entity 1: csr_fconfig_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_fconfig_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_flash_mux_if.sv Info (12023): Found entity 1: csr_flash_mux_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_flash_mux_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_mctp_smb_if.sv Info (12023): Found entity 1: csr_mctp_smb_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_mctp_smb_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_misc_if.sv Info (12023): Found entity 1: csr_misc_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_misc_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_svid_if.sv Info (12023): Found entity 1: csr_svid_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_svid_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Info (12023): Found entity 1: svid_i2c_wrapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Info (12023): Found entity 1: svid_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Info (12023): Found entity 1: system_pll File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/misc_pll/misc_pll.v Info (12023): Found entity 1: misc_pll File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/misc_pll/misc_pll.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/pfl_ii.v Info (12023): Found entity 1: pfl_ii File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/pfl_ii.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Info (12023): Found entity 1: altera_parallel_flash_loader_2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg.v Info (12023): Found entity 1: altera_pfl2_cfg File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Info (12023): Found entity 1: altera_pfl2_cfg_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_glitch.v Info (12023): Found entity 1: altera_pfl2_glitch File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_glitch.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_reset.v Info (12023): Found entity 1: altera_pfl2_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_reset.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_ready_synchronizer.v Info (12023): Found entity 1: altera_pfl2_cfg_ready_synchronizer File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_ready_synchronizer.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Info (12023): Found entity 1: altera_pfl2_qspi_cfg File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Info (12023): Found entity 1: altera_pfl2_up_converter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Info (12023): Found entity 1: altera_pfl2_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Info (12023): Found entity 1: altera_pfl2_qspi_cfg_micron_altera File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_timing_adapter.v Info (12023): Found entity 1: altera_pfl2_timing_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_timing_adapter.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter.sv Info (12023): Found entity 1: pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter.sv Line: 60 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_data_format_adapter.v Info (12023): Found entity 1: altera_pfl2_data_format_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_data_format_adapter.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter.sv Info (12023): Found entity 1: pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid.v Info (12023): Found entity 1: unique_chipid File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid.v Line: 8 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Info (12023): Found entity 1: altchip_id File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 36 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/svid_i2c_master.v Info (12023): Found entity 1: svid_i2c_master File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/svid_i2c_master.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Info (12023): Found entity 1: altera_avalon_i2c File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Info (12023): Found entity 1: altera_avalon_i2c_csr File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_clk_cnt.v Info (12023): Found entity 1: altera_avalon_i2c_clk_cnt File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_clk_cnt.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_condt_det.v Info (12023): Found entity 1: altera_avalon_i2c_condt_det File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_condt_det.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_condt_gen.v Info (12023): Found entity 1: altera_avalon_i2c_condt_gen File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_condt_gen.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Info (12023): Found entity 1: altera_avalon_i2c_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_mstfsm.v Info (12023): Found entity 1: altera_avalon_i2c_mstfsm File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_mstfsm.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_rxshifter.v Info (12023): Found entity 1: altera_avalon_i2c_rxshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_rxshifter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_txshifter.v Info (12023): Found entity 1: altera_avalon_i2c_txshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_txshifter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_spksupp.v Info (12023): Found entity 1: altera_avalon_i2c_spksupp File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_spksupp.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_txout.v Info (12023): Found entity 1: altera_avalon_i2c_txout File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_txout.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Info (12023): Found entity 1: max10_qsys File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_irq_mapper.sv Info (12023): Found entity 1: max10_qsys_irq_mapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_avalon_st_adapter_018 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_avalon_st_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_handshake_clock_crosser File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_clock_crosser.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_std_synchronizer_nocut.v Line: 44 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Info (12023): Found entity 1: altera_merlin_width_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_003.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_mux_003 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_003.sv Line: 51 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103 Info (12023): Found entity 2: altera_merlin_arb_adder File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_002.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_mux_002 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_002.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_mux_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_001.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_018.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux_018 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_018.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_006.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux_006 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_006.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_004.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux_004 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_004.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_018.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_mux_018 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_018.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_004.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_mux_004 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_004.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_mux_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_001.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_003.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_demux_003 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_003.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_002.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_demux_002 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_002.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_demux_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_demux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Info (12023): Found entity 1: altera_merlin_burst_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39 Info (12021): Found 5 design units, including 5 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40 Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55 Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77 Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98 Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_new.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_incr_burst_converter.sv Info (12023): Found entity 1: altera_incr_burst_converter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_incr_burst_converter.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_wrap_burst_converter.sv Info (12023): Found entity 1: altera_wrap_burst_converter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_default_burst_converter.sv Info (12023): Found entity 1: altera_default_burst_converter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_default_burst_converter.sv Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_traffic_limiter.sv Info (12023): Found entity 1: altera_merlin_traffic_limiter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_reorder_memory.sv Info (12023): Found entity 1: altera_merlin_reorder_memory File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28 Info (12023): Found entity 2: memory_pointer_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_024.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_024_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_024.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_024 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_024.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_023.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_023_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_023.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_023 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_023.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_009.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_009_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_009.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_009 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_009.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_007.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_007_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_007.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_007 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_007.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_006.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_006_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_006.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_006 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_006.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_005.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_005_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_005.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_005 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_005.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_004.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_004_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_004.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_004 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_004.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_003.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_003_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_003.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_003 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_003.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_002.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_002_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_002.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_002 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_001_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_001.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_master_agent.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_master_translator.sv Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_2.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_2.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_1.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_rsp_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_demux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_rsp_demux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_cmd_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_cmd_demux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_router_001_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_0_router_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_router_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_0_router File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 5 design units, including 5 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Info (12023): Found entity 1: max10_qsys_uart_console_tx File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 21 Info (12023): Found entity 2: max10_qsys_uart_console_rx_stimulus_source File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 194 Info (12023): Found entity 3: max10_qsys_uart_console_rx File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 288 Info (12023): Found entity 4: max10_qsys_uart_console_regs File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 547 Info (12023): Found entity 5: max10_qsys_uart_console File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 793 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_timer_0.v Info (12023): Found entity 1: max10_qsys_timer_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_timer_0.v Line: 21 Info (12021): Found 14 design units, including 14 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Info (12023): Found entity 1: altera_avalon_packets_to_master_inst_for_spichain_in_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 39 Info (12023): Found entity 2: altera_avalon_packets_to_master_inst_for_spichain_out_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 100 Info (12023): Found entity 3: altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 143 Info (12023): Found entity 4: altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 188 Info (12023): Found entity 5: altera_avalon_st_packets_to_bytes_inst_for_spichain_in_packets_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 233 Info (12023): Found entity 6: altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 308 Info (12023): Found entity 7: channel_adapter_btop_for_spichain_in_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 341 Info (12023): Found entity 8: channel_adapter_btop_for_spichain_out_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 416 Info (12023): Found entity 9: channel_adapter_ptob_for_spichain_in_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 453 Info (12023): Found entity 10: channel_adapter_ptob_for_spichain_out_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 520 Info (12023): Found entity 11: spislave_inst_for_spichain_avalon_streaming_sink_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 559 Info (12023): Found entity 12: spislave_inst_for_spichain_avalon_streaming_source_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 604 Info (12023): Found entity 13: SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 643 Info (12023): Found entity 14: SPISlaveToAvalonMasterBridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 688 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master_inst_for_spichain.v Info (12023): Found entity 1: altera_avalon_packets_to_master_inst_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master_inst_for_spichain.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets_inst_for_spichain.v Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets_inst_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets_inst_for_spichain.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes_inst_for_spichain.v Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes_inst_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes_inst_for_spichain.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_btop_for_spichain.v Info (12023): Found entity 1: channel_adapter_btop_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_btop_for_spichain.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_ptob_for_spichain.v Info (12023): Found entity 1: channel_adapter_ptob_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_ptob_for_spichain.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spislave_inst_for_spichain.v Info (12023): Found entity 1: spislave_inst_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spislave_inst_for_spichain.v Line: 34 Info (12021): Found 7 design units, including 7 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Info (12023): Found entity 1: altera_avalon_packets_to_master File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 22 Info (12023): Found entity 2: packets_to_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 142 Info (12023): Found entity 3: fifo_buffer_single_clock_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 512 Info (12023): Found entity 4: fifo_buffer_scfifo_with_controls File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 573 Info (12023): Found entity 5: fifo_buffer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 627 Info (12023): Found entity 6: fifo_to_packet File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 697 Info (12023): Found entity 7: packets_to_master File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 851 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets.v Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes.v Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes.v Line: 19 Info (12021): Found 6 design units, including 6 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Info (12023): Found entity 1: SPIPhy File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 59 Info (12023): Found entity 2: MOSIctl File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 267 Info (12023): Found entity 3: MISOctl File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 482 Info (12023): Found entity 4: spi_phy_internal_altera_avalon_st_idle_remover File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 625 Info (12023): Found entity 5: spi_phy_internal_altera_avalon_st_idle_inserter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 688 Info (12023): Found entity 6: single_output_pipeline_stage File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 751 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Info (12023): Found entity 1: avmms_2_spim_bridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_reboot_ctrl.v Info (12023): Found entity 1: max10_reboot_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_reboot_ctrl.v Line: 2 Info (12021): Found 7 design units, including 7 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Info (12023): Found entity 1: altera_onchip_flash_address_range_check File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 38 Info (12023): Found entity 2: altera_onchip_flash_address_write_protection_check File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 55 Info (12023): Found entity 3: altera_onchip_flash_s_address_write_protection_check File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 109 Info (12023): Found entity 4: altera_onchip_flash_a_address_write_protection_check File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 147 Info (12023): Found entity 5: altera_onchip_flash_convert_address File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 197 Info (12023): Found entity 6: altera_onchip_flash_convert_sector File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 219 Info (12023): Found entity 7: altera_onchip_flash_counter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 244 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Info (12023): Found entity 1: altera_onchip_flash File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Info (12023): Found entity 1: altera_onchip_flash_avmm_data_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v Info (12023): Found entity 1: altera_onchip_flash_avmm_csr_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/altera_onchip_flash_block.v Info (12023): Found entity 1: altera_onchip_flash_block File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/altera_onchip_flash_block.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash.v Info (12023): Found entity 1: max10_qsys_nios_flash File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_asmiblock.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_asmiblock File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_asmiblock.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Info (12023): Found entity 1: adapter_8_1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Info (12023): Found entity 1: adapter_8_2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Info (12023): Found entity 1: adapter_8_4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer.sv Info (12023): Found entity 1: demultiplexer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_7_channel.sv Info (12023): Found entity 1: demultiplexer_7_channel File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_7_channel.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_9_channels.sv Info (12023): Found entity 1: demultiplexer_9_channels File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_9_channels.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_12_channels.sv Info (12023): Found entity 1: demultiplexer_12_channels File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_12_channels.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clk_div.sv Info (12023): Found entity 1: clk_div File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clk_div.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clock_devider.sv Info (12023): Found entity 1: clock_devider File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clock_devider.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_gpio.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_gpio File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_gpio.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Info (12023): Found entity 1: max10_qsys_nios_flash_qspi_inf_inst File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/inf_sc_fifo_ser_data.v Info (12023): Found entity 1: inf_sc_fifo_ser_data File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/inf_sc_fifo_ser_data.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/qspi_inf_mux.v Info (12023): Found entity 1: qspi_inf_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/qspi_inf_mux.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_cmd File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Info (12023): Found entity 1: data_adapter_32_8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Info (12023): Found entity 1: data_adapter_8_32 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_multiplexer.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_multiplexer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_multiplexer.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_merlin_demultiplexer_0.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_merlin_demultiplexer_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_merlin_demultiplexer_0.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_addr.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_addr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_addr.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_xip_controller.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_xip_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_xip_controller.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avst_fifo.v Info (12023): Found entity 1: avst_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avst_fifo.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_csr.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_csr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_csr.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_resp_ram.v Info (12023): Found entity 1: max10_qsys_mctp_smbus_resp_ram File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_resp_ram.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Info (12023): Found entity 1: max10_qsys_mctp_smbus_req_ram File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Info (12023): Found entity 1: mctp_pcievdm_buffer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios.v Info (12023): Found entity 1: max10_qsys_max10_nios File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_test_bench.v Info (12023): Found entity 1: max10_qsys_max10_nios_cpu_test_bench File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_test_bench.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Info (12023): Found entity 1: max10_qsys_max10_nios_cpu_mult_cell File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Line: 21 Info (12021): Found 9 design units, including 9 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Info (12023): Found entity 1: max10_qsys_max10_nios_cpu_ic_data_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 21 Info (12023): Found entity 2: max10_qsys_max10_nios_cpu_ic_tag_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 89 Info (12023): Found entity 3: max10_qsys_max10_nios_cpu_bht_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 158 Info (12023): Found entity 4: max10_qsys_max10_nios_cpu_register_bank_a_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 227 Info (12023): Found entity 5: max10_qsys_max10_nios_cpu_register_bank_b_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 293 Info (12023): Found entity 6: max10_qsys_max10_nios_cpu_dc_tag_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 359 Info (12023): Found entity 7: max10_qsys_max10_nios_cpu_dc_data_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 425 Info (12023): Found entity 8: max10_qsys_max10_nios_cpu_dc_victim_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 494 Info (12023): Found entity 9: max10_qsys_max10_nios_cpu File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 562 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv Info (12023): Found entity 1: altera_nios2_gen2_rtl_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_mm_bridge.v Info (12023): Found entity 1: altera_avalon_mm_bridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_mm_bridge.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_irq_bridge.v Info (12023): Found entity 1: altera_irq_bridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_irq_bridge.v Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Info (12023): Found entity 1: altera_i2cslave_to_avlmm_bridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_avl_mst_intf_gen.v Info (12023): Found entity 1: altr_i2c_avl_mst_intf_gen File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_avl_mst_intf_gen.v Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_clk_cnt.v Info (12023): Found entity 1: altr_i2c_clk_cnt File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_clk_cnt.v Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_condt_det.v Info (12023): Found entity 1: altr_i2c_condt_det File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_condt_det.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_databuffer.v Info (12023): Found entity 1: altr_i2c_databuffer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_databuffer.v Line: 20 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_rxshifter.v Info (12023): Found entity 1: altr_i2c_rxshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_rxshifter.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_slvfsm.v Info (12023): Found entity 1: altr_i2c_slvfsm File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_slvfsm.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_spksupp.v Info (12023): Found entity 1: altr_i2c_spksupp File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_spksupp.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_txout.v Info (12023): Found entity 1: altr_i2c_txout File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_txout.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_txshifter.v Info (12023): Found entity 1: altr_i2c_txshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_txshifter.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Info (12023): Found entity 1: altera_avalon_i2c File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_csr.v Info (12023): Found entity 1: altera_avalon_i2c_csr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_csr.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_clk_cnt.v Info (12023): Found entity 1: altera_avalon_i2c_clk_cnt File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_clk_cnt.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_condt_det.v Info (12023): Found entity 1: altera_avalon_i2c_condt_det File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_condt_det.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_condt_gen.v Info (12023): Found entity 1: altera_avalon_i2c_condt_gen File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_condt_gen.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Info (12023): Found entity 1: altera_avalon_i2c_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_mstfsm.v Info (12023): Found entity 1: altera_avalon_i2c_mstfsm File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_mstfsm.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_rxshifter.v Info (12023): Found entity 1: altera_avalon_i2c_rxshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_rxshifter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_txshifter.v Info (12023): Found entity 1: altera_avalon_i2c_txshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_txshifter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_spksupp.v Info (12023): Found entity 1: altera_avalon_i2c_spksupp File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_spksupp.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_txout.v Info (12023): Found entity 1: altera_avalon_i2c_txout File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_txout.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Info (12023): Found entity 1: hyperram_ctrlr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Info (12023): Found entity 1: hyperram_io_pads File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Info (12023): Found entity 1: altgpio_one_bit File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 16 Info (12023): Found entity 2: altera_gpio_lite File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 940 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Info (12023): Found entity 1: max10_qsys_fpga_flash File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_qspi_inf_inst File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_dual_boot.v Info (12023): Found entity 1: altera_dual_boot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_dual_boot.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Info (12023): Found entity 1: alt_dual_boot_avmm File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Info (12023): Found entity 1: alt_dual_boot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top_wrapper.sv Info (12023): Found entity 1: crypto_top_wrapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top_wrapper.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Info (12023): Found entity 1: crypto_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Info (12023): Found entity 1: crypto_mem2_be File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Info (12023): Found entity 1: crypto_mem3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Info (12023): Found entity 1: crypto_mem4_be File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/csl_add_sub_393.v Info (12023): Found entity 1: csl_add_sub_393 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/csl_add_sub_393.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Info (12023): Found entity 1: ecdsa384_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Info (12023): Found entity 1: mult_384x9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Info (12023): Found entity 1: multr_all_384x384 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ocs_ecp384_ad_jpc.v Info (12023): Found entity 1: ocs_ecp384_ad_jpc File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ocs_ecp384_ad_jpc.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ch.v Info (12023): Found entity 1: ch File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ch.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/csa_64.v Info (12023): Found entity 1: csa_64 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/csa_64.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hin_init.v Info (12023): Found entity 1: hin_init File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hin_init.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/kt.v Info (12023): Found entity 1: kt File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/kt.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/maj.v Info (12023): Found entity 1: maj File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/maj.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Info (12023): Found entity 1: sha_round File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round_top.v Info (12023): Found entity 1: sha_round_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round_top.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler.v Info (12023): Found entity 1: sha_scheduler File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler_top.v Info (12023): Found entity 1: sha_scheduler_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler_top.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Info (12023): Found entity 1: sha_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_unit.v Info (12023): Found entity 1: sha_unit File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_unit.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sigma0.v Info (12023): Found entity 1: Sigma0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sigma0.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sigma1.v Info (12023): Found entity 1: Sigma1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sigma1.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Info (12023): Found entity 1: entropy_source File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Info (12023): Found entity 1: max10_trng_entropy File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Info (12023): Found entity 1: max10_trng_entropy_adjust File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Info (12023): Found entity 1: max10_trng_entropy_health File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Info (12023): Found entity 1: max10_trng_entropy_race File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Info (12023): Found entity 1: bmc_dma File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Info (12023): Found entity 1: max10_qsys_adc File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_response_merge.v Info (12023): Found entity 1: altera_modular_adc_response_merge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_response_merge.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_dual_sync.v Info (12023): Found entity 1: altera_modular_adc_dual_sync File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_dual_sync.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_conduit_splitter.v Info (12023): Found entity 1: altera_modular_adc_conduit_splitter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_conduit_splitter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store.v Info (12023): Found entity 1: altera_modular_adc_sample_store File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Info (12023): Found entity 1: altera_modular_adc_sample_store_ram File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Line: 53 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer.v Info (12023): Found entity 1: altera_modular_adc_sequencer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer_csr.v Info (12023): Found entity 1: altera_modular_adc_sequencer_csr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer_csr.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer_ctrl.v Info (12023): Found entity 1: altera_modular_adc_sequencer_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer_ctrl.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Info (12023): Found entity 1: altera_modular_adc_control File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Info (12023): Found entity 1: altera_modular_adc_control_avrg_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Line: 53 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Info (12023): Found entity 1: altera_modular_adc_control_fsm File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/chsel_code_converter_sw_to_hw.v Info (12023): Found entity 1: chsel_code_converter_sw_to_hw File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/chsel_code_converter_sw_to_hw.v Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_primitive_wrapper.v Info (12023): Found entity 1: fiftyfivenm_adcblock_primitive_wrapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_primitive_wrapper.v Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Info (12023): Found entity 1: fiftyfivenm_adcblock_top_wrapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Info (12023): Found entity 1: top_misc_interconnect File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 36 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Info (12023): Found entity 1: acadp_bmc_max10_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 23 Info (12021): Found 1 design units, including 0 entities, in source file /home/admin/otc/ofs-bmc/scripts/revision.vhd Info (12022): Found design unit 1: rev_pkg File: /home/admin/otc/ofs-bmc/scripts/revision.vhd Line: 8 Info (12021): Found 2 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/scripts/rev_wrap_factory.vhd Info (12022): Found design unit 1: rev_wrap-wrapper File: /home/admin/otc/ofs-bmc/scripts/rev_wrap_factory.vhd Line: 10 Info (12023): Found entity 1: rev_wrap File: /home/admin/otc/ofs-bmc/scripts/rev_wrap_factory.vhd Line: 6 Warning (10037): Verilog HDL or VHDL warning at SPISlaveToAvalonMasterBridge.v(665): conditional expression evaluates to a constant File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 665 Warning (10037): Verilog HDL or VHDL warning at SPISlaveToAvalonMasterBridge.v(674): conditional expression evaluates to a constant File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 674 Info (12127): Elaborating entity "acadp_bmc_max10_top" for the top level hierarchy Info (12128): Elaborating entity "pwr_seq_brd_if" for hierarchy "pwr_seq_brd_if:pwr_seq_pins" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 237 Info (12128): Elaborating entity "csr_io_if" for hierarchy "csr_io_if:avmm_slave_nios" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 339 Info (12128): Elaborating entity "csr_fconfig_if" for hierarchy "csr_fconfig_if:csr_fconfig" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 342 Info (12128): Elaborating entity "csr_pwr_seq_if" for hierarchy "csr_pwr_seq_if:csr_pwr_seq" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 343 Info (12128): Elaborating entity "csr_flash_mux_if" for hierarchy "csr_flash_mux_if:csr_flash_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 344 Info (12128): Elaborating entity "csr_svid_if" for hierarchy "csr_svid_if:csr_svid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 345 Info (12128): Elaborating entity "csr_mctp_smb_if" for hierarchy "csr_mctp_smb_if:csr_mctp_smb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 346 Info (12128): Elaborating entity "csr_misc_if" for hierarchy "csr_misc_if:csr_misc" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 347 Info (12128): Elaborating entity "csr_jtg_ctrl_if" for hierarchy "csr_jtg_ctrl_if:csr_jtag" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 348 Info (12128): Elaborating entity "jtag_ctrl_io_if" for hierarchy "jtag_ctrl_io_if:avmm_slave_jtag_nios" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 349 Info (12128): Elaborating entity "clk_rst_top" for hierarchy "clk_rst_top:clk_rst_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 412 Info (12128): Elaborating entity "system_pll" for hierarchy "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll" File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 94 Info (12128): Elaborating entity "altpll" for hierarchy "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Line: 120 Info (12130): Elaborated megafunction instantiation "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Line: 120 Info (12133): Instantiated megafunction "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Line: 120 Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "2" Info (12134): Parameter "clk0_duty_cycle" = "50" Info (12134): Parameter "clk0_multiply_by" = "1" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "clk1_divide_by" = "4" Info (12134): Parameter "clk1_duty_cycle" = "50" Info (12134): Parameter "clk1_multiply_by" = "1" Info (12134): Parameter "clk1_phase_shift" = "0" Info (12134): Parameter "clk2_divide_by" = "1" Info (12134): Parameter "clk2_duty_cycle" = "50" Info (12134): Parameter "clk2_multiply_by" = "1" Info (12134): Parameter "clk2_phase_shift" = "0" Info (12134): Parameter "clk3_divide_by" = "1" Info (12134): Parameter "clk3_duty_cycle" = "50" Info (12134): Parameter "clk3_multiply_by" = "1" Info (12134): Parameter "clk3_phase_shift" = "3333" Info (12134): Parameter "clk4_divide_by" = "10" Info (12134): Parameter "clk4_duty_cycle" = "50" Info (12134): Parameter "clk4_multiply_by" = "1" Info (12134): Parameter "clk4_phase_shift" = "0" Info (12134): Parameter "compensate_clock" = "CLK0" Info (12134): Parameter "inclk0_input_frequency" = "10000" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=system_pll" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NORMAL" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" Info (12134): Parameter "port_areset" = "PORT_USED" Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" Info (12134): Parameter "port_fbin" = "PORT_UNUSED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" Info (12134): Parameter "port_locked" = "PORT_USED" Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" Info (12134): Parameter "port_pllena" = "PORT_UNUSED" Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" Info (12134): Parameter "port_scandata" = "PORT_UNUSED" Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" Info (12134): Parameter "port_scandone" = "PORT_UNUSED" Info (12134): Parameter "port_scanread" = "PORT_UNUSED" Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_USED" Info (12134): Parameter "port_clk2" = "PORT_USED" Info (12134): Parameter "port_clk3" = "PORT_USED" Info (12134): Parameter "port_clk4" = "PORT_USED" Info (12134): Parameter "port_clk5" = "PORT_UNUSED" Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" Info (12134): Parameter "self_reset_on_loss_lock" = "OFF" Info (12134): Parameter "width_clock" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/system_pll_altpll.v Info (12023): Found entity 1: system_pll_altpll File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 31 Info (12128): Elaborating entity "system_pll_altpll" for hierarchy "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altpll.tdf Line: 898 Info (12128): Elaborating entity "csr_top" for hierarchy "csr_top:csr_top_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 448 Warning (10858): Verilog HDL warning at csr_top.sv(245): object general_purpose_debug_reg_int used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 245 Warning (10230): Verilog HDL assignment warning at csr_top.sv(1097): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 1097 Warning (10030): Net "general_purpose_debug_reg_int" at csr_top.sv(245) has no driver or initial value, using a default initial value '0' File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 245 Info (12128): Elaborating entity "rev_wrap" for hierarchy "csr_top:csr_top_inst|rev_wrap:revision_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 127 Info (12128): Elaborating entity "csr_ram" for hierarchy "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 524 Info (12128): Elaborating entity "altsyncram" for hierarchy "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Line: 91 Info (12130): Elaborated megafunction instantiation "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Line: 91 Info (12133): Instantiated megafunction "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Line: 91 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "M9K" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_gir1.tdf Info (12023): Found entity 1: altsyncram_gir1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_gir1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_gir1" for hierarchy "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd|altsyncram:altsyncram_component|altsyncram_gir1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "unique_chipid" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 784 Info (12128): Elaborating entity "altchip_id" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid.v Line: 24 Info (12128): Elaborating entity "a_graycounter" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|a_graycounter:gen_cntr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 99 Info (12130): Elaborated megafunction instantiation "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|a_graycounter:gen_cntr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 99 Info (12133): Instantiated megafunction "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|a_graycounter:gen_cntr" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 99 Info (12134): Parameter "width" = "7" Info (12134): Parameter "lpm_type" = "a_graycounter" Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_3ag.tdf Info (12023): Found entity 1: a_graycounter_3ag File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_graycounter_3ag.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_3ag" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|a_graycounter:gen_cntr|a_graycounter_3ag:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_graycounter.tdf Line: 51 Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|lpm_shiftreg:shift_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 194 Info (12130): Elaborated megafunction instantiation "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|lpm_shiftreg:shift_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 194 Info (12133): Instantiated megafunction "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|lpm_shiftreg:shift_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 194 Info (12134): Parameter "lpm_direction" = "RIGHT" Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "64" Info (12128): Elaborating entity "jtag_cntrlr" for hierarchy "jtag_cntrlr:jtag_cntrlr_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 465 Warning (10036): Verilog HDL or VHDL warning at jtag_cntrlr.sv(123): object "fpga_jtag_tck_rise_edge_det" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 123 Warning (10763): Verilog HDL warning at jtag_cntrlr.sv(219): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 219 Warning (10958): SystemVerilog warning at jtag_cntrlr.sv(219): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 219 Info (12128): Elaborating entity "ram_sdp" for hierarchy "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 426 Info (12128): Elaborating entity "altsyncram" for hierarchy "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Line: 89 Info (12130): Elaborated megafunction instantiation "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Line: 89 Info (12133): Instantiated megafunction "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Line: 89 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "M9K" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bpo1.tdf Info (12023): Found entity 1: altsyncram_bpo1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_bpo1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_bpo1" for hierarchy "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram|altsyncram:altsyncram_component|altsyncram_bpo1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "flow_control_top" for hierarchy "flow_control_top:flow_ctrl_top_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 525 Info (12128): Elaborating entity "power_sequencer" for hierarchy "flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Line: 125 Warning (10036): Verilog HDL or VHDL warning at power_sequencer.sv(206): object "pwr_dwn_timeout_fpga" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 206 Warning (10763): Verilog HDL warning at power_sequencer.sv(484): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 484 Warning (10958): SystemVerilog warning at power_sequencer.sv(484): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 484 Warning (10763): Verilog HDL warning at power_sequencer.sv(620): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 620 Warning (10958): SystemVerilog warning at power_sequencer.sv(620): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 620 Info (10264): Verilog HDL Case Statement information at power_sequencer.sv(902): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 902 Info (10264): Verilog HDL Case Statement information at power_sequencer.sv(1121): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 1121 Info (12128): Elaborating entity "fpga_config_ctrl" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Line: 171 Warning (10763): Verilog HDL warning at fpga_config_ctrl.sv(382): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 382 Warning (10958): SystemVerilog warning at fpga_config_ctrl.sv(382): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 382 Warning (10763): Verilog HDL warning at fpga_config_ctrl.sv(790): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 790 Warning (10958): SystemVerilog warning at fpga_config_ctrl.sv(790): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 790 Info (12128): Elaborating entity "bmc_sync" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|bmc_sync:sync_nconfig" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 236 Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|bmc_sync:sync_nconfig|altera_std_synchronizer_nocut:sync_loop[0].sync_nocut" File: /home/admin/otc/ofs-bmc/rtl/max10/design/common/bmc_sync.sv Line: 55 Info (12128): Elaborating entity "bmc_sync" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|bmc_sync:sync_pcie_los" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 247 Info (12128): Elaborating entity "debouncer" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|debouncer:nstatus_dbnc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 258 Info (12128): Elaborating entity "debouncer" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|debouncer:conf_done_dbnc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 269 Info (12128): Elaborating entity "pfl_ii" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Line: 211 Info (12128): Elaborating entity "altera_parallel_flash_loader_2" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/pfl_ii.v Line: 78 Info (12128): Elaborating entity "altera_pfl2_qspi_cfg" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Line: 238 Info (12128): Elaborating entity "altera_pfl2_reset" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_reset:altera_pfl2_reset" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 172 Info (12128): Elaborating entity "altera_pfl2_qspi_cfg_micron_altera" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 211 Info (10264): Verilog HDL Case Statement information at altera_pfl2_qspi_cfg_micron_altera.v(626): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 626 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:tcounter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 317 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:tcounter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 317 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:tcounter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 317 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_direction" = "UP" Info (12134): Parameter "lpm_width" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_o6j.tdf Info (12023): Found entity 1: cntr_o6j File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_o6j.tdf Line: 26 Info (12128): Elaborating entity "cntr_o6j" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:tcounter|cntr_o6j:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:io_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 445 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:io_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 445 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:io_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 445 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "16" Info (12134): Parameter "lpm_direction" = "LEFT" Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:IO_LOOP[1].io_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 464 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:IO_LOOP[1].io_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 464 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:IO_LOOP[1].io_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 464 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "8" Info (12134): Parameter "lpm_direction" = "LEFT" Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:cfg_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 488 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:cfg_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 488 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:cfg_counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 488 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_direction" = "DOWN" Info (12134): Parameter "lpm_width" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_oui.tdf Info (12023): Found entity 1: cntr_oui File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_oui.tdf Line: 26 Info (12128): Elaborating entity "cntr_oui" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:cfg_counter|cntr_oui:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:addr_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 510 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:addr_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 510 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:addr_counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 510 Info (12134): Parameter "lpm_width" = "29" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_c2h.tdf Info (12023): Found entity 1: cntr_c2h File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_c2h.tdf Line: 26 Info (12128): Elaborating entity "cntr_c2h" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:addr_counter|cntr_c2h:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "altera_pfl2_up_converter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 329 Info (10264): Verilog HDL Case Statement information at altera_pfl2_up_converter.v(148): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 148 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 122 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 122 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|lpm_counter:counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 122 Info (12134): Parameter "lpm_width" = "1" Info (12134): Parameter "lpm_direction" = "UP" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_87i.tdf Info (12023): Found entity 1: cntr_87i File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_87i.tdf Line: 26 Info (12128): Elaborating entity "cntr_87i" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|lpm_counter:counter|cntr_87i:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "altera_pfl2_fifo" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 138 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:write_pointer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 127 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:write_pointer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 127 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:write_pointer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 127 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_width" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_mle.tdf Info (12023): Found entity 1: cntr_mle File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_mle.tdf Line: 26 Info (12128): Elaborating entity "cntr_mle" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:write_pointer|cntr_mle:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:read_pointer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 139 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:read_pointer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 139 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:read_pointer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 139 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_width" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_rtg.tdf Info (12023): Found entity 1: cntr_rtg File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_rtg.tdf Line: 26 Info (12128): Elaborating entity "cntr_rtg" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:read_pointer|cntr_rtg:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:data_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 178 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:data_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 178 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:data_counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 178 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_width" = "2" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_nle.tdf Info (12023): Found entity 1: cntr_nle File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_nle.tdf Line: 26 Info (12128): Elaborating entity "cntr_nle" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:data_counter|cntr_nle:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "altera_pfl2_cfg_controller" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 381 Info (10264): Verilog HDL Case Statement information at altera_pfl2_cfg_controller.v(547): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 547 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 494 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 494 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|lpm_counter:counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 494 Info (12134): Parameter "lpm_width" = "20" Info (12134): Parameter "lpm_direction" = "DOWN" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_50j.tdf Info (12023): Found entity 1: cntr_50j File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_50j.tdf Line: 26 Info (12128): Elaborating entity "cntr_50j" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|lpm_counter:counter|cntr_50j:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "altera_pfl2_glitch" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|altera_pfl2_glitch:nstatus_sync" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 531 Info (12128): Elaborating entity "altera_pfl2_glitch" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|altera_pfl2_glitch:enable_sync" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 533 Info (12128): Elaborating entity "altera_pfl2_data_format_adapter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_data_format_adapter:data_format_adapter_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 420 Info (12128): Elaborating entity "pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_data_format_adapter:data_format_adapter_0|pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter:altera_pfl2_data_format_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_data_format_adapter.v Line: 26 Info (12128): Elaborating entity "altera_pfl2_timing_adapter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_timing_adapter:timing_adapter_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 431 Info (12128): Elaborating entity "pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_timing_adapter:timing_adapter_0|pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter:altera_pfl2_timing_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_timing_adapter.v Line: 26 Info (12128): Elaborating entity "altera_pfl2_cfg_ready_synchronizer" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_ready_synchronizer:ready_synchronizer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 442 Info (12128): Elaborating entity "max10_qsys" for hierarchy "max10_qsys:max10_qsys_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 717 Info (12128): Elaborating entity "max10_qsys_adc" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 408 Info (12128): Elaborating entity "altera_modular_adc_control" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 106 Info (12128): Elaborating entity "altera_modular_adc_control_fsm" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 108 Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_std_synchronizer:u_clk_dft_synchronizer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 156 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_std_synchronizer:u_clk_dft_synchronizer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 156 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_std_synchronizer:u_clk_dft_synchronizer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 156 Info (12134): Parameter "depth" = "2" Info (12128): Elaborating entity "altera_modular_adc_control_avrg_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 955 Info (12128): Elaborating entity "scfifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Line: 91 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Line: 91 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Line: 91 Info (12134): Parameter "add_ram_output_register" = "OFF" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M9K" Info (12134): Parameter "lpm_numwords" = "64" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "12" Info (12134): Parameter "lpm_widthu" = "6" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_ds61.tdf Info (12023): Found entity 1: scfifo_ds61 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/scfifo_ds61.tdf Line: 25 Info (12128): Elaborating entity "scfifo_ds61" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/scfifo.tdf Line: 300 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_3o41.tdf Info (12023): Found entity 1: a_dpfifo_3o41 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_3o41.tdf Line: 29 Info (12128): Elaborating entity "a_dpfifo_3o41" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/scfifo_ds61.tdf Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_c6e.tdf Info (12023): Found entity 1: a_fefifo_c6e File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_fefifo_c6e.tdf Line: 25 Info (12128): Elaborating entity "a_fefifo_c6e" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|a_fefifo_c6e:fifo_state" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_3o41.tdf Line: 41 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_337.tdf Info (12023): Found entity 1: cntr_337 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_337.tdf Line: 26 Info (12128): Elaborating entity "cntr_337" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|a_fefifo_c6e:fifo_state|cntr_337:count_usedw" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_fefifo_c6e.tdf Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rqn1.tdf Info (12023): Found entity 1: altsyncram_rqn1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_rqn1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_3o41.tdf Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_n2b.tdf Info (12023): Found entity 1: cntr_n2b File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_n2b.tdf Line: 26 Info (12128): Elaborating entity "cntr_n2b" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|cntr_n2b:rd_ptr_count" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_3o41.tdf Line: 43 Info (12128): Elaborating entity "fiftyfivenm_adcblock_top_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 152 Info (12128): Elaborating entity "chsel_code_converter_sw_to_hw" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|chsel_code_converter_sw_to_hw:decoder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 173 Info (12128): Elaborating entity "fiftyfivenm_adcblock_primitive_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 191 Info (12128): Elaborating entity "altera_modular_adc_control" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 155 Info (12128): Elaborating entity "altera_modular_adc_control_fsm" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 108 Info (12128): Elaborating entity "fiftyfivenm_adcblock_top_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 152 Info (12128): Elaborating entity "chsel_code_converter_sw_to_hw" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|chsel_code_converter_sw_to_hw:decoder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 173 Info (12128): Elaborating entity "fiftyfivenm_adcblock_primitive_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 191 Info (12128): Elaborating entity "altera_modular_adc_sequencer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sequencer:sequencer_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 306 Info (12128): Elaborating entity "altera_modular_adc_sequencer_csr" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sequencer:sequencer_internal|altera_modular_adc_sequencer_csr:u_seq_csr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer.v Line: 214 Info (12128): Elaborating entity "altera_modular_adc_sequencer_ctrl" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sequencer:sequencer_internal|altera_modular_adc_sequencer_ctrl:u_seq_ctrl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer.v Line: 304 Info (12128): Elaborating entity "altera_modular_adc_sample_store" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 325 Info (12128): Elaborating entity "altera_modular_adc_sample_store_ram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store.v Line: 175 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Line: 107 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Line: 107 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Line: 107 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "64" Info (12134): Parameter "numwords_b" = "64" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "M9K" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "widthad_a" = "6" Info (12134): Parameter "widthad_b" = "6" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r5s1.tdf Info (12023): Found entity 1: altsyncram_r5s1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_r5s1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_r5s1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram|altsyncram:altsyncram_component|altsyncram_r5s1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_modular_adc_conduit_splitter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_conduit_splitter:conduit_splitter_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 333 Info (12128): Elaborating entity "altera_modular_adc_dual_sync" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_dual_sync:dual_sync_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 342 Info (12128): Elaborating entity "altera_modular_adc_response_merge" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_response_merge:response_merge_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 362 Info (12128): Elaborating entity "bmc_dma" for hierarchy "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 437 Warning (10763): Verilog HDL warning at bmc_dma.sv(351): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 351 Warning (10958): SystemVerilog warning at bmc_dma.sv(351): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 351 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|altsyncram:dma_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 646 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|altsyncram:dma_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 646 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|altsyncram:dma_buffer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 646 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "indata_reg_b" = "CLOCK0" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_a" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "width_byteena_b" = "1" Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_k3e2.tdf Info (12023): Found entity 1: altsyncram_k3e2 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_k3e2.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_k3e2" for hierarchy "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|altsyncram:dma_buffer|altsyncram_k3e2:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "crypto_top_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 448 Info (12128): Elaborating entity "crypto_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top_wrapper.sv Line: 56 Info (12128): Elaborating entity "sha_unit" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 176 Info (12128): Elaborating entity "sha_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_unit.v Line: 62 Info (12128): Elaborating entity "kt" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|kt:kt_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 108 Info (12128): Elaborating entity "sha_scheduler_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_scheduler_top:msg_schedule_top" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 120 Info (12128): Elaborating entity "sha_scheduler" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_scheduler_top:msg_schedule_top|sha_scheduler:msg_sch_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler_top.v Line: 57 Info (12128): Elaborating entity "csa_64" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_scheduler_top:msg_schedule_top|sha_scheduler:msg_sch_inst|csa_64:csa0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler.v Line: 72 Info (12128): Elaborating entity "hin_init" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|hin_init:init_state" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 133 Info (12128): Elaborating entity "sha_round_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 148 Info (12128): Elaborating entity "sha_round" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round_top.v Line: 61 Info (12128): Elaborating entity "maj" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0|maj:fn_maj" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 71 Info (12128): Elaborating entity "Sigma0" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0|Sigma0:fn_Sigma0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 77 Info (12128): Elaborating entity "ch" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0|ch:fn_ch" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 84 Info (12128): Elaborating entity "Sigma1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0|Sigma1:fn_Sigma1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 90 Info (12128): Elaborating entity "ecdsa384_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 357 Info (12128): Elaborating entity "multr_all_384x384" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 127 Info (12128): Elaborating entity "crypto_mem3" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 47 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Line: 89 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Line: 89 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Line: 89 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "2" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "1" Info (12134): Parameter "widthad_b" = "5" Info (12134): Parameter "width_a" = "128" Info (12134): Parameter "width_b" = "8" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_aom1.tdf Info (12023): Found entity 1: altsyncram_aom1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_aom1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_aom1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31|altsyncram:altsyncram_component|altsyncram_aom1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "mult_384x9" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mult_384x9:i_m384_9" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 55 Info (12128): Elaborating entity "csl_add_sub_393" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|csl_add_sub_393:i_cs411" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 70 Info (12128): Elaborating entity "ocs_ecp384_ad_jpc" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|ocs_ecp384_ad_jpc:i_jpc" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 148 Info (12128): Elaborating entity "crypto_mem2_be" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 150 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Line: 92 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Line: 92 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Line: 92 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "32" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "5" Info (12134): Parameter "widthad_b" = "5" Info (12134): Parameter "width_a" = "128" Info (12134): Parameter "width_b" = "128" Info (12134): Parameter "width_byteena_a" = "16" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_50p1.tdf Info (12023): Found entity 1: altsyncram_50p1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_50p1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_50p1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213|altsyncram:altsyncram_component|altsyncram_50p1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "crypto_mem4_be" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 158 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Line: 92 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Line: 92 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Line: 92 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "2" Info (12134): Parameter "numwords_b" = "2" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "1" Info (12134): Parameter "widthad_b" = "1" Info (12134): Parameter "width_a" = "128" Info (12134): Parameter "width_b" = "128" Info (12134): Parameter "width_byteena_a" = "16" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nso1.tdf Info (12023): Found entity 1: altsyncram_nso1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_nso1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_nso1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413|altsyncram:altsyncram_component|altsyncram_nso1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "entropy_source" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 392 Info (12128): Elaborating entity "max10_trng_entropy" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 74 Info (12128): Elaborating entity "max10_trng_entropy_race" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 138 Info (12128): Elaborating entity "max10_trng_entropy_health" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 154 Info (12128): Elaborating entity "max10_trng_entropy_adjust" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 171 Info (12128): Elaborating entity "max10_trng_entropy_race" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 186 Info (12128): Elaborating entity "max10_trng_entropy_adjust" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 219 Info (12128): Elaborating entity "scfifo" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 116 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 116 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 116 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M9K" Info (12134): Parameter "lpm_numwords" = "256" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "32" Info (12134): Parameter "lpm_widthu" = "8" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "OFF" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_3h41.tdf Info (12023): Found entity 1: scfifo_3h41 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/scfifo_3h41.tdf Line: 25 Info (12128): Elaborating entity "scfifo_3h41" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/scfifo.tdf Line: 300 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_pc21.tdf Info (12023): Found entity 1: a_dpfifo_pc21 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 33 Info (12128): Elaborating entity "a_dpfifo_pc21" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/scfifo_3h41.tdf Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_kki1.tdf Info (12023): Found entity 1: altsyncram_kki1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_kki1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_kki1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|altsyncram_kki1:FIFOram" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 46 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_b78.tdf Info (12023): Found entity 1: cmpr_b78 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cmpr_b78.tdf Line: 23 Info (12128): Elaborating entity "cmpr_b78" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cmpr_b78:almost_full_comparer" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 55 Info (12128): Elaborating entity "cmpr_b78" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cmpr_b78:three_comparison" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 56 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_o2b.tdf Info (12023): Found entity 1: cntr_o2b File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_o2b.tdf Line: 26 Info (12128): Elaborating entity "cntr_o2b" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cntr_o2b:rd_ptr_msb" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_537.tdf Info (12023): Found entity 1: cntr_537 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_537.tdf Line: 26 Info (12128): Elaborating entity "cntr_537" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cntr_537:usedw_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_p2b.tdf Info (12023): Found entity 1: cntr_p2b File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_p2b.tdf Line: 26 Info (12128): Elaborating entity "cntr_p2b" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cntr_p2b:wr_ptr" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 59 Info (12128): Elaborating entity "altera_dual_boot" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 462 Info (12128): Elaborating entity "alt_dual_boot_avmm" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_dual_boot.v Line: 50 Info (12128): Elaborating entity "alt_dual_boot" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 143 Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:read_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 286 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:read_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 286 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:read_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 286 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "41" Info (12134): Parameter "lpm_direction" = "RIGHT" Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:write_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 324 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:write_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 324 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:write_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 324 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "41" Info (12134): Parameter "lpm_direction" = "RIGHT" Info (12128): Elaborating entity "lpm_counter" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 339 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 339 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_counter:counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 339 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_direction" = "UP" Info (12134): Parameter "lpm_width" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_d7i.tdf Info (12023): Found entity 1: cntr_d7i File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_d7i.tdf Line: 26 Info (12128): Elaborating entity "cntr_d7i" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_counter:counter|cntr_d7i:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "max10_qsys_fpga_flash" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 492 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_csr" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_csr:csr_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 200 Info (12128): Elaborating entity "max10_qsys_fpga_flash_xip_controller" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_xip_controller:xip_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 238 Info (12128): Elaborating entity "avst_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_xip_controller.sv Line: 641 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avst_fifo.v Line: 73 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_addr" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_addr:xip_addr_adaption" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 263 Info (12128): Elaborating entity "max10_qsys_fpga_flash_merlin_demultiplexer_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_merlin_demultiplexer_0:merlin_demultiplexer_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 286 Info (12128): Elaborating entity "max10_qsys_fpga_flash_multiplexer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_multiplexer:multiplexer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 309 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_multiplexer:multiplexer|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_multiplexer.sv Line: 276 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_multiplexer:multiplexer|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_cmd" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 349 Info (12128): Elaborating entity "data_adapter_32_8" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|data_adapter_32_8:data_adapter_32_8_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 645 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(36): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 36 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(40): object "state_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 40 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(42): object "in_ready_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 42 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(61): object "b_startofpacket_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 61 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(67): object "mem_readdata0" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 67 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(72): object "mem_readdata1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 72 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(77): object "mem_readdata2" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 77 Warning (10858): Verilog HDL warning at data_adapter_32_8.sv(84): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 84 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(85): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 85 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(88): object "out_channel" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 88 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(92): object "out_startofpacket" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 92 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(93): object "out_endofpacket" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 93 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(96): object "out_empty" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 96 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(99): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 99 Warning (10230): Verilog HDL assignment warning at data_adapter_32_8.sv(137): truncated value with size 4 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 137 Warning (10230): Verilog HDL assignment warning at data_adapter_32_8.sv(282): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 282 Info (12128): Elaborating entity "data_adapter_8_32" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|data_adapter_8_32:data_adapter_8_32_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 664 Warning (10036): Verilog HDL or VHDL warning at data_adapter_8_32.sv(41): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 41 Warning (10858): Verilog HDL warning at data_adapter_8_32.sv(86): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 86 Warning (10036): Verilog HDL or VHDL warning at data_adapter_8_32.sv(87): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 87 Warning (10036): Verilog HDL or VHDL warning at data_adapter_8_32.sv(90): object "out_channel" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 90 Warning (10036): Verilog HDL or VHDL warning at data_adapter_8_32.sv(96): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 96 Info (12128): Elaborating entity "max10_qsys_fpga_flash_qspi_inf_inst" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 385 Info (10264): Verilog HDL Case Statement information at max10_qsys_fpga_flash_qspi_inf_inst.sv(632): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 632 Info (10264): Verilog HDL Case Statement information at max10_qsys_fpga_flash_qspi_inf_inst.sv(889): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 889 Info (12128): Elaborating entity "demultiplexer_12_channels" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|demultiplexer_12_channels:demultiplexer_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 215 Info (12128): Elaborating entity "adapter_8_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|adapter_8_1:adapter_8_1_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 235 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(48): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 48 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(52): object "state_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 52 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(55): object "in_ready_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 55 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(78): object "b_startofpacket_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 78 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(84): object "mem_readdata0" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 84 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(89): object "mem_readdata1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 89 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(94): object "mem_readdata2" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 94 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(99): object "mem_readdata3" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 99 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(104): object "mem_readdata4" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 104 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(109): object "mem_readdata5" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 109 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(114): object "mem_readdata6" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 114 Warning (10858): Verilog HDL warning at adapter_8_1.sv(120): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 120 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(121): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 121 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(123): object "out_empty" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 123 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(126): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 126 Warning (10230): Verilog HDL assignment warning at adapter_8_1.sv(176): truncated value with size 8 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 176 Warning (10230): Verilog HDL assignment warning at adapter_8_1.sv(402): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 402 Info (12128): Elaborating entity "adapter_8_2" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|adapter_8_2:adapter_8_2_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 252 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(46): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 46 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(50): object "state_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 50 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(52): object "in_ready_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 52 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(75): object "b_startofpacket_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 75 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(81): object "mem_readdata0" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 81 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(86): object "mem_readdata1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 86 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(91): object "mem_readdata2" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 91 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(96): object "mem_readdata3" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 96 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(101): object "mem_readdata4" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 101 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(106): object "mem_readdata5" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 106 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(111): object "mem_readdata6" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 111 Warning (10858): Verilog HDL warning at adapter_8_2.sv(118): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 118 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(119): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 119 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(122): object "out_empty" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 122 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(125): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 125 Warning (10230): Verilog HDL assignment warning at adapter_8_2.sv(174): truncated value with size 8 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 174 Warning (10230): Verilog HDL assignment warning at adapter_8_2.sv(339): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 339 Warning (10230): Verilog HDL assignment warning at adapter_8_2.sv(408): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 408 Info (12128): Elaborating entity "adapter_8_4" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|adapter_8_4:adapter_8_4_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 269 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(43): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 43 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(47): object "state_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 47 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(49): object "in_ready_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 49 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(72): object "b_startofpacket_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 72 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(78): object "mem_readdata0" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 78 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(83): object "mem_readdata1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 83 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(88): object "mem_readdata2" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 88 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(93): object "mem_readdata3" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 93 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(98): object "mem_readdata4" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 98 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(103): object "mem_readdata5" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 103 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(108): object "mem_readdata6" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 108 Warning (10858): Verilog HDL warning at adapter_8_4.sv(115): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 115 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(116): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 116 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(119): object "out_empty" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 119 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(122): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 122 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(172): truncated value with size 8 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 172 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(313): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 313 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(352): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 352 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(391): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 391 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(430): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 430 Info (12128): Elaborating entity "qspi_inf_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|qspi_inf_mux:qspi_inf_mux_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 302 Info (12128): Elaborating entity "max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|qspi_inf_mux:qspi_inf_mux_inst|max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux:qspi_inf_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/qspi_inf_mux.v Line: 62 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|qspi_inf_mux:qspi_inf_mux_inst|max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux:qspi_inf_mux|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux.sv Line: 335 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|qspi_inf_mux:qspi_inf_mux_inst|max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux:qspi_inf_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "inf_sc_fifo_ser_data" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|inf_sc_fifo_ser_data:inf_sc_fifo_ser_data_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 324 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|inf_sc_fifo_ser_data:inf_sc_fifo_ser_data_inst|altera_avalon_sc_fifo:inf_sc_fifo_ser_data" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/inf_sc_fifo_ser_data.v Line: 75 Warning (10858): Verilog HDL warning at altera_avalon_sc_fifo.v(109): object wr_ptr used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 109 Warning (10858): Verilog HDL warning at altera_avalon_sc_fifo.v(116): object incremented_rd_ptr used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 116 Warning (10030): Net "wr_ptr" at altera_avalon_sc_fifo.v(109) has no driver or initial value, using a default initial value '0' File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 109 Warning (10030): Net "incremented_rd_ptr" at altera_avalon_sc_fifo.v(116) has no driver or initial value, using a default initial value '0' File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 116 Info (12128): Elaborating entity "scfifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 396 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 396 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 396 Info (12134): Parameter "add_ram_output_register" = "OFF" Info (12134): Parameter "enable_ecc" = "FALSE" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_numwords" = "8" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "10" Info (12134): Parameter "lpm_widthu" = "3" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "OFF" Info (12134): Parameter "use_eab" = "OFF" Info (12128): Elaborating entity "a_fffifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/scfifo.tdf Line: 279 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/scfifo.tdf Line: 279 Info (12128): Elaborating entity "lpm_ff" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_ff:last_data_node[7]" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 102 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_ff:last_data_node[7]", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 102 Info (12128): Elaborating entity "lpm_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 103 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 103 Info (12021): Found 1 design units, including 1 entities, in source file db/mux_l7c.tdf Info (12023): Found entity 1: mux_l7c File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mux_l7c.tdf Line: 23 Info (12128): Elaborating entity "mux_l7c" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux|mux_l7c:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_mux.tdf Line: 87 Info (12128): Elaborating entity "lpm_counter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 105 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 105 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ole.tdf Info (12023): Found entity 1: cntr_ole File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_ole.tdf Line: 26 Info (12128): Elaborating entity "cntr_ole" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_ole:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "a_fefifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 112 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 112 Info (12128): Elaborating entity "lpm_compare" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fefifo.tdf Line: 77 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fefifo.tdf Line: 77 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_upf.tdf Info (12023): Found entity 1: cmpr_upf File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cmpr_upf.tdf Line: 23 Info (12128): Elaborating entity "cmpr_upf" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare|cmpr_upf:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_compare.tdf Line: 281 Info (12128): Elaborating entity "lpm_compare" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_full_compare" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fefifo.tdf Line: 82 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_full_compare", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fefifo.tdf Line: 82 Info (12128): Elaborating entity "clk_div" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|clk_div:clk_div_new_inst_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 497 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 448 Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.v Line: 208 Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.v Line: 220 Info (12128): Elaborating entity "hyperram_ctrlr" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 527 Warning (10036): Verilog HDL or VHDL warning at hyperram_ctrlr.sv(129): object "s0_txn_addr_sync" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 129 Warning (10036): Verilog HDL or VHDL warning at hyperram_ctrlr.sv(171): object "hram_rbuf_rden_r1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 171 Warning (10763): Verilog HDL warning at hyperram_ctrlr.sv(193): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 193 Warning (10958): SystemVerilog warning at hyperram_ctrlr.sv(193): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 193 Warning (10763): Verilog HDL warning at hyperram_ctrlr.sv(369): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 369 Warning (10958): SystemVerilog warning at hyperram_ctrlr.sv(369): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 369 Warning (10230): Verilog HDL assignment warning at hyperram_ctrlr.sv(447): truncated value with size 32 to match size of target (5) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 447 Warning (10230): Verilog HDL assignment warning at hyperram_ctrlr.sv(455): truncated value with size 32 to match size of target (5) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 455 Warning (10230): Verilog HDL assignment warning at hyperram_ctrlr.sv(570): truncated value with size 32 to match size of target (16) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 570 Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|altera_std_synchronizer_nocut:sync_txn_latch" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 315 Info (12128): Elaborating entity "dcfifo" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 336 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 336 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 336 Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_numwords" = "16" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "dcfifo" Info (12134): Parameter "lpm_width" = "36" Info (12134): Parameter "lpm_widthu" = "4" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "rdsync_delaypipe" = "4" Info (12134): Parameter "read_aclr_synch" = "OFF" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "write_aclr_synch" = "OFF" Info (12134): Parameter "wrsync_delaypipe" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_e9h1.tdf Info (12023): Found entity 1: dcfifo_e9h1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 37 Info (12128): Elaborating entity "dcfifo_e9h1" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/dcfifo.tdf Line: 191 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_fg6.tdf Info (12023): Found entity 1: a_graycounter_fg6 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_graycounter_fg6.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_fg6" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|a_graycounter_fg6:rdptr_g1p" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 48 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_bub.tdf Info (12023): Found entity 1: a_graycounter_bub File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_graycounter_bub.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_bub" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|a_graycounter_bub:wrptr_g1p" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 49 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_v241.tdf Info (12023): Found entity 1: altsyncram_v241 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_v241.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_v241" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|altsyncram_v241:fifo_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 50 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_snl.tdf Info (12023): Found entity 1: alt_synch_pipe_snl File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_snl.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_snl" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|alt_synch_pipe_snl:rs_dgwp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_dd9.tdf Info (12023): Found entity 1: dffpipe_dd9 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dffpipe_dd9.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_dd9" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe12" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_snl.tdf Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tnl.tdf Info (12023): Found entity 1: alt_synch_pipe_tnl File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_tnl.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_tnl" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|alt_synch_pipe_tnl:ws_dgrp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ed9.tdf Info (12023): Found entity 1: dffpipe_ed9 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dffpipe_ed9.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_ed9" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_ed9:dffpipe15" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_tnl.tdf Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_1h5.tdf Info (12023): Found entity 1: cmpr_1h5 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cmpr_1h5.tdf Line: 23 Info (12128): Elaborating entity "cmpr_1h5" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|cmpr_1h5:rdempty_eq_comp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 59 Info (12128): Elaborating entity "hyperram_io_pads" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 644 Info (12128): Elaborating entity "altera_gpio_lite" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_dq_ddio_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Line: 108 Info (12128): Elaborating entity "altgpio_one_bit" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_dq_ddio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 1115 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 82 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object "oe_outclocken_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 334 Info (12128): Elaborating entity "altera_gpio_lite" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_rwds_ddio_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Line: 162 Info (12128): Elaborating entity "altgpio_one_bit" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_rwds_ddio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 1115 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 82 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object "oe_outclocken_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 334 Info (12128): Elaborating entity "altera_gpio_lite" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_clk_ddio_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Line: 218 Info (12128): Elaborating entity "altgpio_one_bit" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_clk_ddio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 1115 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 82 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object "oe_outclocken_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 334 Info (12128): Elaborating entity "dcfifo" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 708 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 708 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 708 Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_numwords" = "16" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "dcfifo" Info (12134): Parameter "lpm_width" = "32" Info (12134): Parameter "lpm_widthu" = "4" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "rdsync_delaypipe" = "4" Info (12134): Parameter "read_aclr_synch" = "OFF" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "write_aclr_synch" = "OFF" Info (12134): Parameter "wrsync_delaypipe" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_b2i1.tdf Info (12023): Found entity 1: dcfifo_b2i1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_b2i1.tdf Line: 37 Info (12128): Elaborating entity "dcfifo_b2i1" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/dcfifo.tdf Line: 191 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_n241.tdf Info (12023): Found entity 1: altsyncram_n241 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_n241.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_n241" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|altsyncram_n241:fifo_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_b2i1.tdf Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_unl.tdf Info (12023): Found entity 1: alt_synch_pipe_unl File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_unl.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_unl" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|alt_synch_pipe_unl:rs_dgwp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_b2i1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_fd9.tdf Info (12023): Found entity 1: dffpipe_fd9 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dffpipe_fd9.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_fd9" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe6" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_unl.tdf Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_vnl.tdf Info (12023): Found entity 1: alt_synch_pipe_vnl File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_vnl.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_vnl" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|alt_synch_pipe_vnl:ws_dgrp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_b2i1.tdf Line: 59 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf Info (12023): Found entity 1: dffpipe_gd9 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dffpipe_gd9.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_gd9" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe9" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_vnl.tdf Line: 35 Info (12128): Elaborating entity "altera_avalon_i2c" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 552 Info (12128): Elaborating entity "altera_avalon_i2c_csr" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_csr:u_csr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 207 Info (12128): Elaborating entity "altera_avalon_i2c_mstfsm" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_mstfsm:u_mstfsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 262 Info (12128): Elaborating entity "altera_avalon_i2c_rxshifter" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_rxshifter:u_rxshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 291 Info (12128): Elaborating entity "altera_avalon_i2c_txshifter" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_txshifter:u_txshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 320 Info (12128): Elaborating entity "altera_avalon_i2c_spksupp" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_spksupp:u_spksupp" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 331 Info (12128): Elaborating entity "altera_avalon_i2c_condt_det" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_condt_det:u_condt_det" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 359 Info (12128): Elaborating entity "altera_avalon_i2c_condt_gen" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_condt_gen:u_condt_gen" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 397 Info (12128): Elaborating entity "altera_avalon_i2c_clk_cnt" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_clk_cnt:u_clk_cnt" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 443 Info (12128): Elaborating entity "altera_avalon_i2c_txout" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_txout:u_txout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 466 Info (12128): Elaborating entity "altera_avalon_i2c_fifo" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 491 Info (10264): Verilog HDL Case Statement information at altera_avalon_i2c_fifo.v(129): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "power_up_uninitialized" = "TRUE" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "width_a" = "10" Info (12134): Parameter "width_b" = "10" Info (12134): Parameter "widthad_a" = "6" Info (12134): Parameter "widthad_b" = "6" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "numwords_a" = "64" Info (12134): Parameter "numwords_b" = "64" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_n6b1.tdf Info (12023): Found entity 1: altsyncram_n6b1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_n6b1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_n6b1" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram|altsyncram_n6b1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_avalon_i2c_fifo" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 513 Info (10264): Verilog HDL Case Statement information at altera_avalon_i2c_fifo.v(129): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "power_up_uninitialized" = "TRUE" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "width_a" = "8" Info (12134): Parameter "width_b" = "8" Info (12134): Parameter "widthad_a" = "6" Info (12134): Parameter "widthad_b" = "6" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "numwords_a" = "64" Info (12134): Parameter "numwords_b" = "64" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_54b1.tdf Info (12023): Found entity 1: altsyncram_54b1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_54b1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_54b1" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram|altsyncram_54b1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_i2cslave_to_avlmm_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 599 Warning (10230): Verilog HDL assignment warning at altera_i2cslave_to_avlmm_bridge.v(701): truncated value with size 32 to match size of target (2) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 701 Info (12128): Elaborating entity "altr_i2c_spksupp" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_spksupp:i_altr_i2c_spksupp" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 397 Info (12128): Elaborating entity "altr_i2c_condt_det" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_condt_det:i_altr_i2c_condt_det" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 428 Info (12128): Elaborating entity "altr_i2c_databuffer" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_databuffer:tx_databuffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 444 Warning (10230): Verilog HDL assignment warning at altr_i2c_databuffer.v(48): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_databuffer.v Line: 48 Info (12128): Elaborating entity "altr_i2c_slvfsm" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_slvfsm:i_altr_i2c_slvfsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 507 Info (12128): Elaborating entity "altr_i2c_avl_mst_intf_gen" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_avl_mst_intf_gen:i_altr_i2c_avl_mst_intf_gen" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 538 Info (12128): Elaborating entity "altr_i2c_txshifter" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_txshifter:i_altr_i2c_txshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 594 Info (12128): Elaborating entity "altr_i2c_rxshifter" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_rxshifter:i_altr_i2c_rxshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 659 Info (12128): Elaborating entity "altr_i2c_txout" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_txout:i_altr_i2c_txout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 695 Info (12128): Elaborating entity "altr_i2c_clk_cnt" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_clk_cnt:i_altr_i2c_clk_cnt" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 762 Info (12128): Elaborating entity "altera_irq_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_irq_bridge:irq_bridge" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 639 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_mm_bridge:jtag_ctrlr_bridge" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 673 Info (12128): Elaborating entity "max10_qsys_max10_nios" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 695 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios.v Line: 51 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_test_bench" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_test_bench:the_max10_qsys_max10_nios_cpu_test_bench" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 3075 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_ic_data_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 4077 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 61 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 61 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 61 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "1024" Info (12134): Parameter "numwords_b" = "1024" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "10" Info (12134): Parameter "widthad_b" = "10" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_2uc1.tdf Info (12023): Found entity 1: altsyncram_2uc1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_2uc1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_2uc1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_2uc1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_ic_tag_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 4143 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 129 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 129 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 129 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "128" Info (12134): Parameter "numwords_b" = "128" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "24" Info (12134): Parameter "width_b" = "24" Info (12134): Parameter "widthad_a" = "7" Info (12134): Parameter "widthad_b" = "7" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1lc1.tdf Info (12023): Found entity 1: altsyncram_1lc1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_1lc1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_1lc1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_1lc1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_bht_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 4313 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 198 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 198 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 198 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "2" Info (12134): Parameter "width_b" = "2" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_vhc1.tdf Info (12023): Found entity 1: altsyncram_vhc1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_vhc1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_vhc1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht|altsyncram:the_altsyncram|altsyncram_vhc1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_register_bank_a_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 5254 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 264 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 264 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 264 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "32" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "5" Info (12134): Parameter "widthad_b" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5tb1.tdf Info (12023): Found entity 1: altsyncram_5tb1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_5tb1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_5tb1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_5tb1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_register_bank_b_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_b_module:max10_qsys_max10_nios_cpu_register_bank_b" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 5272 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_mult_cell" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 5689 Info (12128): Elaborating entity "altera_mult_add" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Line: 63 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Line: 63 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Line: 63 Info (12134): Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0" Info (12134): Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0" Info (12134): Parameter "addnsub_multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "dedicated_multiplier_circuitry" = "YES" Info (12134): Parameter "input_register_a0" = "UNREGISTERED" Info (12134): Parameter "input_register_b0" = "UNREGISTERED" Info (12134): Parameter "input_source_a0" = "DATAA" Info (12134): Parameter "input_source_b0" = "DATAB" Info (12134): Parameter "lpm_type" = "altera_mult_add" Info (12134): Parameter "multiplier1_direction" = "ADD" Info (12134): Parameter "multiplier_aclr0" = "ACLR0" Info (12134): Parameter "multiplier_register0" = "CLOCK0" Info (12134): Parameter "number_of_multipliers" = "1" Info (12134): Parameter "output_register" = "UNREGISTERED" Info (12134): Parameter "port_addnsub1" = "PORT_UNUSED" Info (12134): Parameter "port_addnsub3" = "PORT_UNUSED" Info (12134): Parameter "representation_a" = "UNSIGNED" Info (12134): Parameter "representation_b" = "UNSIGNED" Info (12134): Parameter "selected_device_family" = "MAX10" Info (12134): Parameter "signed_pipeline_aclr_a" = "ACLR0" Info (12134): Parameter "signed_pipeline_aclr_b" = "ACLR0" Info (12134): Parameter "signed_pipeline_register_a" = "CLOCK0" Info (12134): Parameter "signed_pipeline_register_b" = "CLOCK0" Info (12134): Parameter "signed_register_a" = "UNREGISTERED" Info (12134): Parameter "signed_register_b" = "UNREGISTERED" Info (12134): Parameter "width_a" = "16" Info (12134): Parameter "width_b" = "16" Info (12134): Parameter "width_result" = "32" Info (12021): Found 1 design units, including 1 entities, in source file db/altera_mult_add_bbo2.v Info (12023): Found entity 1: altera_mult_add_bbo2 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altera_mult_add_bbo2.v Line: 29 Info (12128): Elaborating entity "altera_mult_add_bbo2" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add.tdf Line: 455 Info (12128): Elaborating entity "altera_mult_add_rtl" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altera_mult_add_bbo2.v Line: 117 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altera_mult_add_bbo2.v Line: 117 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altera_mult_add_bbo2.v Line: 117 Info (12134): Parameter "accum_direction" = "ADD" Info (12134): Parameter "accum_sload_aclr" = "NONE" Info (12134): Parameter "accum_sload_latency_aclr" = "NONE" Info (12134): Parameter "accum_sload_latency_clock" = "UNREGISTERED" Info (12134): Parameter "accum_sload_latency_sclr" = "NONE" Info (12134): Parameter "accum_sload_register" = "UNREGISTERED" Info (12134): Parameter "accum_sload_sclr" = "NONE" Info (12134): Parameter "accumulator" = "NO" Info (12134): Parameter "adder1_rounding" = "NO" Info (12134): Parameter "adder3_rounding" = "NO" Info (12134): Parameter "addnsub1_round_aclr" = "NONE" Info (12134): Parameter "addnsub1_round_pipeline_aclr" = "NONE" Info (12134): Parameter "addnsub1_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "addnsub1_round_pipeline_sclr" = "NONE" Info (12134): Parameter "addnsub1_round_register" = "UNREGISTERED" Info (12134): Parameter "addnsub1_round_sclr" = "NONE" Info (12134): Parameter "addnsub3_round_aclr" = "NONE" Info (12134): Parameter "addnsub3_round_pipeline_aclr" = "NONE" Info (12134): Parameter "addnsub3_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "addnsub3_round_pipeline_sclr" = "NONE" Info (12134): Parameter "addnsub3_round_register" = "UNREGISTERED" Info (12134): Parameter "addnsub3_round_sclr" = "NONE" Info (12134): Parameter "addnsub_multiplier_aclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_aclr3" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_aclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_aclr3" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_clock1" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_latency_clock3" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_latency_sclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_sclr3" = "NONE" Info (12134): Parameter "addnsub_multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_register3" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_sclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_sclr3" = "NONE" Info (12134): Parameter "chainout_aclr" = "NONE" Info (12134): Parameter "chainout_adder" = "NO" Info (12134): Parameter "chainout_adder_direction" = "ADD" Info (12134): Parameter "chainout_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_aclr" = "NONE" Info (12134): Parameter "chainout_round_output_aclr" = "NONE" Info (12134): Parameter "chainout_round_output_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_output_sclr" = "NONE" Info (12134): Parameter "chainout_round_pipeline_aclr" = "NONE" Info (12134): Parameter "chainout_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_pipeline_sclr" = "NONE" Info (12134): Parameter "chainout_round_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_sclr" = "NONE" Info (12134): Parameter "chainout_rounding" = "NO" Info (12134): Parameter "chainout_saturate_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_output_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_output_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturate_output_sclr" = "NONE" Info (12134): Parameter "chainout_saturate_pipeline_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturate_pipeline_sclr" = "NONE" Info (12134): Parameter "chainout_saturate_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturate_sclr" = "NONE" Info (12134): Parameter "chainout_saturation" = "NO" Info (12134): Parameter "chainout_sclr" = "NONE" Info (12134): Parameter "coef0_0" = "0" Info (12134): Parameter "coef0_1" = "0" Info (12134): Parameter "coef0_2" = "0" Info (12134): Parameter "coef0_3" = "0" Info (12134): Parameter "coef0_4" = "0" Info (12134): Parameter "coef0_5" = "0" Info (12134): Parameter "coef0_6" = "0" Info (12134): Parameter "coef0_7" = "0" Info (12134): Parameter "coef1_0" = "0" Info (12134): Parameter "coef1_1" = "0" Info (12134): Parameter "coef1_2" = "0" Info (12134): Parameter "coef1_3" = "0" Info (12134): Parameter "coef1_4" = "0" Info (12134): Parameter "coef1_5" = "0" Info (12134): Parameter "coef1_6" = "0" Info (12134): Parameter "coef1_7" = "0" Info (12134): Parameter "coef2_0" = "0" Info (12134): Parameter "coef2_1" = "0" Info (12134): Parameter "coef2_2" = "0" Info (12134): Parameter "coef2_3" = "0" Info (12134): Parameter "coef2_4" = "0" Info (12134): Parameter "coef2_5" = "0" Info (12134): Parameter "coef2_6" = "0" Info (12134): Parameter "coef2_7" = "0" Info (12134): Parameter "coef3_0" = "0" Info (12134): Parameter "coef3_1" = "0" Info (12134): Parameter "coef3_2" = "0" Info (12134): Parameter "coef3_3" = "0" Info (12134): Parameter "coef3_4" = "0" Info (12134): Parameter "coef3_5" = "0" Info (12134): Parameter "coef3_6" = "0" Info (12134): Parameter "coef3_7" = "0" Info (12134): Parameter "coefsel0_aclr" = "NONE" Info (12134): Parameter "coefsel0_latency_aclr" = "NONE" Info (12134): Parameter "coefsel0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel0_latency_sclr" = "NONE" Info (12134): Parameter "coefsel0_register" = "UNREGISTERED" Info (12134): Parameter "coefsel0_sclr" = "NONE" Info (12134): Parameter "coefsel1_aclr" = "NONE" Info (12134): Parameter "coefsel1_latency_aclr" = "NONE" Info (12134): Parameter "coefsel1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel1_latency_sclr" = "NONE" Info (12134): Parameter "coefsel1_register" = "UNREGISTERED" Info (12134): Parameter "coefsel1_sclr" = "NONE" Info (12134): Parameter "coefsel2_aclr" = "NONE" Info (12134): Parameter "coefsel2_latency_aclr" = "NONE" Info (12134): Parameter "coefsel2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel2_latency_sclr" = "NONE" Info (12134): Parameter "coefsel2_register" = "UNREGISTERED" Info (12134): Parameter "coefsel2_sclr" = "NONE" Info (12134): Parameter "coefsel3_aclr" = "NONE" Info (12134): Parameter "coefsel3_latency_aclr" = "NONE" Info (12134): Parameter "coefsel3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel3_latency_sclr" = "NONE" Info (12134): Parameter "coefsel3_register" = "UNREGISTERED" Info (12134): Parameter "coefsel3_sclr" = "NONE" Info (12134): Parameter "dedicated_multiplier_circuitry" = "YES" Info (12134): Parameter "double_accum" = "NO" Info (12134): Parameter "dsp_block_balancing" = "Auto" Info (12134): Parameter "extra_latency" = "0" Info (12134): Parameter "input_a0_latency_aclr" = "NONE" Info (12134): Parameter "input_a0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a0_latency_sclr" = "NONE" Info (12134): Parameter "input_a1_latency_aclr" = "NONE" Info (12134): Parameter "input_a1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a1_latency_sclr" = "NONE" Info (12134): Parameter "input_a2_latency_aclr" = "NONE" Info (12134): Parameter "input_a2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a2_latency_sclr" = "NONE" Info (12134): Parameter "input_a3_latency_aclr" = "NONE" Info (12134): Parameter "input_a3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a3_latency_sclr" = "NONE" Info (12134): Parameter "input_aclr_a0" = "NONE" Info (12134): Parameter "input_aclr_a1" = "NONE" Info (12134): Parameter "input_aclr_a2" = "NONE" Info (12134): Parameter "input_aclr_a3" = "NONE" Info (12134): Parameter "input_aclr_b0" = "NONE" Info (12134): Parameter "input_aclr_b1" = "NONE" Info (12134): Parameter "input_aclr_b2" = "NONE" Info (12134): Parameter "input_aclr_b3" = "NONE" Info (12134): Parameter "input_aclr_c0" = "NONE" Info (12134): Parameter "input_aclr_c1" = "NONE" Info (12134): Parameter "input_aclr_c2" = "NONE" Info (12134): Parameter "input_aclr_c3" = "NONE" Info (12134): Parameter "input_b0_latency_aclr" = "NONE" Info (12134): Parameter "input_b0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b0_latency_sclr" = "NONE" Info (12134): Parameter "input_b1_latency_aclr" = "NONE" Info (12134): Parameter "input_b1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b1_latency_sclr" = "NONE" Info (12134): Parameter "input_b2_latency_aclr" = "NONE" Info (12134): Parameter "input_b2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b2_latency_sclr" = "NONE" Info (12134): Parameter "input_b3_latency_aclr" = "NONE" Info (12134): Parameter "input_b3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b3_latency_sclr" = "NONE" Info (12134): Parameter "input_c0_latency_aclr" = "NONE" Info (12134): Parameter "input_c0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c0_latency_sclr" = "NONE" Info (12134): Parameter "input_c1_latency_aclr" = "NONE" Info (12134): Parameter "input_c1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c1_latency_sclr" = "NONE" Info (12134): Parameter "input_c2_latency_aclr" = "NONE" Info (12134): Parameter "input_c2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c2_latency_sclr" = "NONE" Info (12134): Parameter "input_c3_latency_aclr" = "NONE" Info (12134): Parameter "input_c3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c3_latency_sclr" = "NONE" Info (12134): Parameter "input_register_a0" = "UNREGISTERED" Info (12134): Parameter "input_register_a1" = "UNREGISTERED" Info (12134): Parameter "input_register_a2" = "UNREGISTERED" Info (12134): Parameter "input_register_a3" = "UNREGISTERED" Info (12134): Parameter "input_register_b0" = "UNREGISTERED" Info (12134): Parameter "input_register_b1" = "UNREGISTERED" Info (12134): Parameter "input_register_b2" = "UNREGISTERED" Info (12134): Parameter "input_register_b3" = "UNREGISTERED" Info (12134): Parameter "input_register_c0" = "UNREGISTERED" Info (12134): Parameter "input_register_c1" = "UNREGISTERED" Info (12134): Parameter "input_register_c2" = "UNREGISTERED" Info (12134): Parameter "input_register_c3" = "UNREGISTERED" Info (12134): Parameter "input_sclr_a0" = "NONE" Info (12134): Parameter "input_sclr_a1" = "NONE" Info (12134): Parameter "input_sclr_a2" = "NONE" Info (12134): Parameter "input_sclr_a3" = "NONE" Info (12134): Parameter "input_sclr_b0" = "NONE" Info (12134): Parameter "input_sclr_b1" = "NONE" Info (12134): Parameter "input_sclr_b2" = "NONE" Info (12134): Parameter "input_sclr_b3" = "NONE" Info (12134): Parameter "input_sclr_c0" = "NONE" Info (12134): Parameter "input_sclr_c1" = "NONE" Info (12134): Parameter "input_sclr_c2" = "NONE" Info (12134): Parameter "input_sclr_c3" = "NONE" Info (12134): Parameter "input_source_a0" = "DATAA" Info (12134): Parameter "input_source_a1" = "DATAA" Info (12134): Parameter "input_source_a2" = "DATAA" Info (12134): Parameter "input_source_a3" = "DATAA" Info (12134): Parameter "input_source_b0" = "DATAB" Info (12134): Parameter "input_source_b1" = "DATAB" Info (12134): Parameter "input_source_b2" = "DATAB" Info (12134): Parameter "input_source_b3" = "DATAB" Info (12134): Parameter "latency" = "0" Info (12134): Parameter "loadconst_control_aclr" = "NONE" Info (12134): Parameter "loadconst_control_register" = "UNREGISTERED" Info (12134): Parameter "loadconst_control_sclr" = "NONE" Info (12134): Parameter "loadconst_value" = "64" Info (12134): Parameter "mult01_round_aclr" = "NONE" Info (12134): Parameter "mult01_round_register" = "UNREGISTERED" Info (12134): Parameter "mult01_round_sclr" = "NONE" Info (12134): Parameter "mult01_saturation_aclr" = "ACLR0" Info (12134): Parameter "mult01_saturation_register" = "UNREGISTERED" Info (12134): Parameter "mult01_saturation_sclr" = "ACLR0" Info (12134): Parameter "mult23_round_aclr" = "NONE" Info (12134): Parameter "mult23_round_register" = "UNREGISTERED" Info (12134): Parameter "mult23_round_sclr" = "NONE" Info (12134): Parameter "mult23_saturation_aclr" = "NONE" Info (12134): Parameter "mult23_saturation_register" = "UNREGISTERED" Info (12134): Parameter "mult23_saturation_sclr" = "NONE" Info (12134): Parameter "multiplier01_rounding" = "NO" Info (12134): Parameter "multiplier01_saturation" = "NO" Info (12134): Parameter "multiplier1_direction" = "ADD" Info (12134): Parameter "multiplier23_rounding" = "NO" Info (12134): Parameter "multiplier23_saturation" = "NO" Info (12134): Parameter "multiplier3_direction" = "ADD" Info (12134): Parameter "multiplier_aclr0" = "ACLR0" Info (12134): Parameter "multiplier_aclr1" = "NONE" Info (12134): Parameter "multiplier_aclr2" = "NONE" Info (12134): Parameter "multiplier_aclr3" = "NONE" Info (12134): Parameter "multiplier_register0" = "CLOCK0" Info (12134): Parameter "multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "multiplier_register2" = "UNREGISTERED" Info (12134): Parameter "multiplier_register3" = "UNREGISTERED" Info (12134): Parameter "multiplier_sclr0" = "NONE" Info (12134): Parameter "multiplier_sclr1" = "NONE" Info (12134): Parameter "multiplier_sclr2" = "NONE" Info (12134): Parameter "multiplier_sclr3" = "NONE" Info (12134): Parameter "negate_aclr" = "NONE" Info (12134): Parameter "negate_latency_aclr" = "NONE" Info (12134): Parameter "negate_latency_clock" = "UNREGISTERED" Info (12134): Parameter "negate_latency_sclr" = "NONE" Info (12134): Parameter "negate_register" = "UNREGISTERED" Info (12134): Parameter "negate_sclr" = "NONE" Info (12134): Parameter "number_of_multipliers" = "1" Info (12134): Parameter "output_aclr" = "NONE" Info (12134): Parameter "output_register" = "UNREGISTERED" Info (12134): Parameter "output_round_aclr" = "NONE" Info (12134): Parameter "output_round_pipeline_aclr" = "NONE" Info (12134): Parameter "output_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "output_round_pipeline_sclr" = "NONE" Info (12134): Parameter "output_round_register" = "UNREGISTERED" Info (12134): Parameter "output_round_sclr" = "NONE" Info (12134): Parameter "output_round_type" = "NEAREST_INTEGER" Info (12134): Parameter "output_rounding" = "NO" Info (12134): Parameter "output_saturate_aclr" = "NONE" Info (12134): Parameter "output_saturate_pipeline_aclr" = "NONE" Info (12134): Parameter "output_saturate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "output_saturate_pipeline_sclr" = "NONE" Info (12134): Parameter "output_saturate_register" = "UNREGISTERED" Info (12134): Parameter "output_saturate_sclr" = "NONE" Info (12134): Parameter "output_saturate_type" = "ASYMMETRIC" Info (12134): Parameter "output_saturation" = "NO" Info (12134): Parameter "output_sclr" = "NONE" Info (12134): Parameter "port_addnsub1" = "PORT_UNUSED" Info (12134): Parameter "port_addnsub3" = "PORT_UNUSED" Info (12134): Parameter "port_chainout_sat_is_overflow" = "PORT_UNUSED" Info (12134): Parameter "port_negate" = "PORT_UNUSED" Info (12134): Parameter "port_output_is_overflow" = "PORT_UNUSED" Info (12134): Parameter "port_signa" = "PORT_UNUSED" Info (12134): Parameter "port_signb" = "PORT_UNUSED" Info (12134): Parameter "preadder_direction_0" = "ADD" Info (12134): Parameter "preadder_direction_1" = "ADD" Info (12134): Parameter "preadder_direction_2" = "ADD" Info (12134): Parameter "preadder_direction_3" = "ADD" Info (12134): Parameter "preadder_mode" = "SIMPLE" Info (12134): Parameter "representation_a" = "UNSIGNED" Info (12134): Parameter "representation_b" = "UNSIGNED" Info (12134): Parameter "rotate_aclr" = "NONE" Info (12134): Parameter "rotate_output_aclr" = "NONE" Info (12134): Parameter "rotate_output_register" = "UNREGISTERED" Info (12134): Parameter "rotate_output_sclr" = "NONE" Info (12134): Parameter "rotate_pipeline_aclr" = "NONE" Info (12134): Parameter "rotate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "rotate_pipeline_sclr" = "NONE" Info (12134): Parameter "rotate_register" = "UNREGISTERED" Info (12134): Parameter "rotate_sclr" = "NONE" Info (12134): Parameter "scanouta_aclr" = "NONE" Info (12134): Parameter "scanouta_register" = "UNREGISTERED" Info (12134): Parameter "scanouta_sclr" = "NONE" Info (12134): Parameter "selected_device_family" = "MAX 10" Info (12134): Parameter "shift_mode" = "NO" Info (12134): Parameter "shift_right_aclr" = "NONE" Info (12134): Parameter "shift_right_output_aclr" = "NONE" Info (12134): Parameter "shift_right_output_register" = "UNREGISTERED" Info (12134): Parameter "shift_right_output_sclr" = "NONE" Info (12134): Parameter "shift_right_pipeline_aclr" = "NONE" Info (12134): Parameter "shift_right_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "shift_right_pipeline_sclr" = "NONE" Info (12134): Parameter "shift_right_register" = "UNREGISTERED" Info (12134): Parameter "shift_right_sclr" = "NONE" Info (12134): Parameter "signed_aclr_a" = "NONE" Info (12134): Parameter "signed_aclr_b" = "NONE" Info (12134): Parameter "signed_latency_aclr_a" = "NONE" Info (12134): Parameter "signed_latency_aclr_b" = "NONE" Info (12134): Parameter "signed_latency_clock_a" = "UNREGISTERED" Info (12134): Parameter "signed_latency_clock_b" = "UNREGISTERED" Info (12134): Parameter "signed_latency_sclr_a" = "NONE" Info (12134): Parameter "signed_latency_sclr_b" = "NONE" Info (12134): Parameter "signed_register_a" = "UNREGISTERED" Info (12134): Parameter "signed_register_b" = "UNREGISTERED" Info (12134): Parameter "signed_sclr_a" = "NONE" Info (12134): Parameter "signed_sclr_b" = "NONE" Info (12134): Parameter "systolic_aclr1" = "NONE" Info (12134): Parameter "systolic_aclr3" = "NONE" Info (12134): Parameter "systolic_delay1" = "UNREGISTERED" Info (12134): Parameter "systolic_delay3" = "UNREGISTERED" Info (12134): Parameter "systolic_sclr1" = "NONE" Info (12134): Parameter "systolic_sclr3" = "NONE" Info (12134): Parameter "use_sload_accum_port" = "NO" Info (12134): Parameter "use_subnadd" = "NO" Info (12134): Parameter "width_a" = "16" Info (12134): Parameter "width_b" = "16" Info (12134): Parameter "width_c" = "22" Info (12134): Parameter "width_chainin" = "1" Info (12134): Parameter "width_coef" = "18" Info (12134): Parameter "width_msb" = "17" Info (12134): Parameter "width_result" = "32" Info (12134): Parameter "width_saturate_sign" = "1" Info (12134): Parameter "zero_chainout_output_aclr" = "NONE" Info (12134): Parameter "zero_chainout_output_register" = "UNREGISTERED" Info (12134): Parameter "zero_chainout_output_sclr" = "NONE" Info (12134): Parameter "zero_loopback_aclr" = "NONE" Info (12134): Parameter "zero_loopback_output_aclr" = "NONE" Info (12134): Parameter "zero_loopback_output_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_output_sclr" = "NONE" Info (12134): Parameter "zero_loopback_pipeline_aclr" = "NONE" Info (12134): Parameter "zero_loopback_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_pipeline_sclr" = "NONE" Info (12134): Parameter "zero_loopback_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_sclr" = "NONE" Info (12134): Parameter "lpm_type" = "altera_mult_add_rtl" Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:signa_reg_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 907 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:signa_reg_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 907 Info (12128): Elaborating entity "ama_data_split_reg_ext_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1023 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1023 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_register_function:data_register_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1989 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_register_function:data_register_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1989 Info (12128): Elaborating entity "ama_dynamic_signed_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_dynamic_signed_function:data0_signed_extension_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2145 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_dynamic_signed_function:data0_signed_extension_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2145 Info (12128): Elaborating entity "ama_data_split_reg_ext_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1113 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1113 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_register_function:data_register_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1989 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_register_function:data_register_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1989 Info (12128): Elaborating entity "ama_dynamic_signed_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_dynamic_signed_function:data0_signed_extension_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2145 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_dynamic_signed_function:data0_signed_extension_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2145 Info (12128): Elaborating entity "ama_preadder_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1265 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1265 Info (12128): Elaborating entity "ama_adder_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3264 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3264 Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:first_adder_ext_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2705 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:first_adder_ext_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2705 Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:second_adder_ext_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2738 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:second_adder_ext_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2738 Info (12128): Elaborating entity "ama_multiplier_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1309 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1309 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3060 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3060 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3074 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_1", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3074 Info (12128): Elaborating entity "ama_adder_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1350 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1350 Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:first_adder_ext_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2705 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:first_adder_ext_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2705 Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:second_adder_ext_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2738 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:second_adder_ext_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2738 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:output_reg_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1490 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:output_reg_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1490 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_dc_tag_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 6111 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 396 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 396 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 396 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "128" Info (12134): Parameter "numwords_b" = "128" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "19" Info (12134): Parameter "width_b" = "19" Info (12134): Parameter "widthad_a" = "7" Info (12134): Parameter "widthad_b" = "7" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_v0c1.tdf Info (12023): Found entity 1: altsyncram_v0c1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_v0c1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_v0c1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_v0c1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_dc_data_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 6177 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 465 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 465 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 465 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "1024" Info (12134): Parameter "numwords_b" = "1024" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "10" Info (12134): Parameter "widthad_b" = "10" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ote1.tdf Info (12023): Found entity 1: altsyncram_ote1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_ote1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_ote1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_ote1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_dc_victim_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 6289 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 534 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 534 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 534 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "8" Info (12134): Parameter "numwords_b" = "8" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "3" Info (12134): Parameter "widthad_b" = "3" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_hec1.tdf Info (12023): Found entity 1: altsyncram_hec1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_hec1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_hec1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_hec1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_nios2_gen2_rtl_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|altera_nios2_gen2_rtl_module:the_nios2_rtl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 6861 Info (12128): Elaborating entity "mctp_pcievdm_buffer" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 733 Warning (10763): Verilog HDL warning at mctp_pcievdm_buffer.sv(406): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 406 Warning (10958): SystemVerilog warning at mctp_pcievdm_buffer.sv(406): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 406 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:ingress_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 539 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:ingress_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 539 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:ingress_buffer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 539 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_etm1.tdf Info (12023): Found entity 1: altsyncram_etm1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_etm1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_etm1" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:ingress_buffer|altsyncram_etm1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:egress_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 590 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:egress_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 590 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:egress_buffer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 590 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "indata_reg_b" = "CLOCK0" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_a" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "width_byteena_b" = "1" Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_m3e2.tdf Info (12023): Found entity 1: altsyncram_m3e2 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_m3e2.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_m3e2" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:egress_buffer|altsyncram_m3e2:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_mm_bridge:mctp_smbus_req_bridge" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 767 Info (12128): Elaborating entity "max10_qsys_mctp_smbus_req_ram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 780 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Line: 63 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Line: 63 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Line: 63 Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "1024" Info (12134): Parameter "numwords_a" = "1024" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "DONT_CARE" Info (12134): Parameter "width_a" = "8" Info (12134): Parameter "widthad_a" = "10" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fv91.tdf Info (12023): Found entity 1: altsyncram_fv91 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_fv91.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_fv91" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram|altsyncram:the_altsyncram|altsyncram_fv91:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_mctp_smbus_resp_ram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_resp_ram:mctp_smbus_resp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 827 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_mm_bridge:mlb_csr_bridge" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 861 Info (12128): Elaborating entity "max10_qsys_nios_flash" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 888 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_addr" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|intel_generic_serial_flash_interface_addr:xip_addr_adaption" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash.v Line: 260 Info (12128): Elaborating entity "max10_qsys_nios_flash_qspi_inf_inst" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_nios_flash_qspi_inf_inst:qspi_inf_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash.v Line: 379 Info (10264): Verilog HDL Case Statement information at max10_qsys_nios_flash_qspi_inf_inst.sv(629): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Line: 629 Info (10264): Verilog HDL Case Statement information at max10_qsys_nios_flash_qspi_inf_inst.sv(886): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Line: 886 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_gpio" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_nios_flash_qspi_inf_inst:qspi_inf_inst|intel_generic_serial_flash_interface_gpio:dedicated_interface" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Line: 950 Info (12128): Elaborating entity "altera_onchip_flash" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 953 Info (12128): Elaborating entity "altera_onchip_flash_avmm_csr_controller" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Line: 203 Info (12128): Elaborating entity "altera_onchip_flash_avmm_data_controller" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Line: 282 Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 569 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 569 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 569 Info (12134): Parameter "depth" = "2" Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1182 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1182 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1182 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "32" Info (12134): Parameter "lpm_direction" = "LEFT" Info (12128): Elaborating entity "altera_onchip_flash_address_range_check" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1192 Info (12128): Elaborating entity "altera_onchip_flash_convert_address" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1203 Info (12128): Elaborating entity "altera_onchip_flash_a_address_write_protection_check" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1245 Info (12128): Elaborating entity "altera_onchip_flash_s_address_write_protection_check" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_s_address_write_protection_check:sector_address_write_protection_checker" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1255 Info (12128): Elaborating entity "altera_onchip_flash_convert_sector" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_sector:sector_convertor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1266 Info (12128): Elaborating entity "altera_onchip_flash_block" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_block:altera_onchip_flash_block" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Line: 327 Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /home/admin/otc/ofs-bmc/rtl/max10/build/max10_onchip_flash.hex -- setting all initial values to 0 Info (12128): Elaborating entity "max10_reboot_ctrl" for hierarchy "max10_qsys:max10_qsys_inst|max10_reboot_ctrl:reboot_ctrl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 976 Info (10264): Verilog HDL Case Statement information at max10_reboot_ctrl.v(253): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_reboot_ctrl.v Line: 253 Info (12128): Elaborating entity "avmms_2_spim_bridge" for hierarchy "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1012 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(223): truncated value with size 32 to match size of target (3) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 223 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(224): truncated value with size 32 to match size of target (16) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 224 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(243): truncated value with size 32 to match size of target (8) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 243 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(244): truncated value with size 32 to match size of target (8) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 244 Warning (10763): Verilog HDL warning at avmms_2_spim_bridge.sv(443): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 443 Warning (10958): SystemVerilog warning at avmms_2_spim_bridge.sv(443): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 443 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(523): truncated value with size 32 to match size of target (11) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 523 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(528): truncated value with size 32 to match size of target (21) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 528 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_sc_fifo:avst_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 425 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes" for hierarchy "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_st_packets_to_bytes:pkts_to_bytes" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 788 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets" for hierarchy "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_st_bytes_to_packets:bytes_to_pkts" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 808 Info (12128): Elaborating entity "SPISlaveToAvalonMasterBridge" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1031 Info (12128): Elaborating entity "altera_avalon_packets_to_master_inst_for_spichain_in_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain_in_stream_arbitrator:the_altera_avalon_packets_to_master_inst_for_spichain_in_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 818 Info (12128): Elaborating entity "altera_avalon_packets_to_master_inst_for_spichain_out_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain_out_stream_arbitrator:the_altera_avalon_packets_to_master_inst_for_spichain_out_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 831 Info (12128): Elaborating entity "altera_avalon_packets_to_master_inst_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain:the_altera_avalon_packets_to_master_inst_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 855 Info (12128): Elaborating entity "altera_avalon_packets_to_master" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain:the_altera_avalon_packets_to_master_inst_for_spichain|altera_avalon_packets_to_master:the_altera_avalon_packets_to_master" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master_inst_for_spichain.v Line: 114 Info (12128): Elaborating entity "packets_to_master" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain:the_altera_avalon_packets_to_master_inst_for_spichain|altera_avalon_packets_to_master:the_altera_avalon_packets_to_master|packets_to_master:p2m" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 137 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_arbitrator:the_altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 867 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_arbitrator:the_altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 881 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets_inst_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_bytes_to_packets_inst_for_spichain:the_altera_avalon_st_bytes_to_packets_inst_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 896 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_bytes_to_packets_inst_for_spichain:the_altera_avalon_st_bytes_to_packets_inst_for_spichain|altera_avalon_st_bytes_to_packets:the_altera_avalon_st_bytes_to_packets" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets_inst_for_spichain.v Line: 83 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes_inst_for_spichain_in_packets_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_packets_to_bytes_inst_for_spichain_in_packets_stream_arbitrator:the_altera_avalon_st_packets_to_bytes_inst_for_spichain_in_packets_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 915 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_arbitrator:the_altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 925 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes_inst_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_packets_to_bytes_inst_for_spichain:the_altera_avalon_st_packets_to_bytes_inst_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 940 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_packets_to_bytes_inst_for_spichain:the_altera_avalon_st_packets_to_bytes_inst_for_spichain|altera_avalon_st_packets_to_bytes:the_altera_avalon_st_packets_to_bytes" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes_inst_for_spichain.v Line: 80 Info (12128): Elaborating entity "channel_adapter_btop_for_spichain_in_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_btop_for_spichain_in_arbitrator:the_channel_adapter_btop_for_spichain_in" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 959 Info (12128): Elaborating entity "channel_adapter_btop_for_spichain_out_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_btop_for_spichain_out_arbitrator:the_channel_adapter_btop_for_spichain_out" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 971 Info (12128): Elaborating entity "channel_adapter_btop_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_btop_for_spichain:the_channel_adapter_btop_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 988 Warning (10036): Verilog HDL or VHDL warning at channel_adapter_btop_for_spichain.v(40): object "out_channel" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_btop_for_spichain.v Line: 40 Warning (10230): Verilog HDL assignment warning at channel_adapter_btop_for_spichain.v(52): truncated value with size 8 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_btop_for_spichain.v Line: 52 Info (12128): Elaborating entity "channel_adapter_ptob_for_spichain_in_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_ptob_for_spichain_in_arbitrator:the_channel_adapter_ptob_for_spichain_in" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1005 Info (12128): Elaborating entity "channel_adapter_ptob_for_spichain_out_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_ptob_for_spichain_out_arbitrator:the_channel_adapter_ptob_for_spichain_out" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1018 Info (12128): Elaborating entity "channel_adapter_ptob_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_ptob_for_spichain:the_channel_adapter_ptob_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1035 Info (12128): Elaborating entity "spislave_inst_for_spichain_avalon_streaming_sink_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain_avalon_streaming_sink_arbitrator:the_spislave_inst_for_spichain_avalon_streaming_sink" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1047 Info (12128): Elaborating entity "spislave_inst_for_spichain_avalon_streaming_source_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain_avalon_streaming_source_arbitrator:the_spislave_inst_for_spichain_avalon_streaming_source" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1058 Info (12128): Elaborating entity "spislave_inst_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1074 Info (12128): Elaborating entity "SPIPhy" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spislave_inst_for_spichain.v Line: 86 Info (12128): Elaborating entity "MOSIctl" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|MOSIctl:SPIPhy_MOSIctl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 137 Info (12128): Elaborating entity "MISOctl" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|MISOctl:SPIPhy_MISOctl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 157 Info (12128): Elaborating entity "spi_phy_internal_altera_avalon_st_idle_remover" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|spi_phy_internal_altera_avalon_st_idle_remover:SPIPhy_altera_avalon_st_idle_remover" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 178 Info (12128): Elaborating entity "single_output_pipeline_stage" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|single_output_pipeline_stage:SPIPhy_single_output_pipeline_stage" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 191 Info (12128): Elaborating entity "spi_phy_internal_altera_avalon_st_idle_inserter" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|spi_phy_internal_altera_avalon_st_idle_inserter:SPIPhy_altera_avalon_st_idle_inserter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 209 Info (12128): Elaborating entity "SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module:SPISlaveToAvalonMasterBridge_reset_clk_domain_synch" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1084 Info (12128): Elaborating entity "max10_qsys_timer_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_timer_0:timer_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1076 Info (12128): Elaborating entity "max10_qsys_uart_console" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1102 Info (12128): Elaborating entity "max10_qsys_uart_console_tx" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console|max10_qsys_uart_console_tx:the_max10_qsys_uart_console_tx" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 867 Info (12128): Elaborating entity "max10_qsys_uart_console_rx" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console|max10_qsys_uart_console_rx:the_max10_qsys_uart_console_rx" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 885 Info (12128): Elaborating entity "max10_qsys_uart_console_rx_stimulus_source" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console|max10_qsys_uart_console_rx:the_max10_qsys_uart_console_rx|max10_qsys_uart_console_rx_stimulus_source:the_max10_qsys_uart_console_rx_stimulus_source" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 366 Info (12128): Elaborating entity "max10_qsys_uart_console_regs" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console|max10_qsys_uart_console_regs:the_max10_qsys_uart_console_regs" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 916 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1132 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:spi_slave_avalon_master_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 252 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:mctp_pcievdm_buffer_avmm_ingr_slv_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 316 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:mlb_csr_bridge_s0_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 380 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:spi_slave_avalon_master_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 461 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:mctp_pcievdm_buffer_avmm_ingr_slv_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 545 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:mctp_pcievdm_buffer_avmm_ingr_slv_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:mctp_pcievdm_buffer_avmm_ingr_slv_agent_rsp_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 586 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_router" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_router:router" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 727 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_router_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_router:router|max10_qsys_mm_interconnect_0_router_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router.sv Line: 180 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_router_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_router_001:router_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 743 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_router_001_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_router_001:router_001|max10_qsys_mm_interconnect_0_router_001_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router_001.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:spi_slave_avalon_master_limiter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 809 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_cmd_demux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_cmd_demux:cmd_demux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 832 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_cmd_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_cmd_mux:cmd_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 849 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_rsp_demux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_rsp_demux:rsp_demux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 883 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_rsp_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_rsp_mux:rsp_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 923 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_mux.sv Line: 310 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_avalon_st_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 952 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_1:mm_interconnect_1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1153 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:mctp_pcievdm_buffer_avmm_egrs_mstr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_1.v Line: 100 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:spi_master_avmm_dir_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_1.v Line: 164 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_2" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_2:mm_interconnect_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1173 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:reboot_ctrl_avmm_master_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_2.v Line: 99 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:dual_boot_avalon_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_2.v Line: 163 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1375 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:bmc_dma_avmm_mstr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 1955 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:max10_nios_data_master_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2015 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:max10_nios_instruction_master_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2075 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:mctp_smbus_resp_bridge_m0_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2135 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:nios_flash_avl_mem_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2259 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:fpga_flash_avl_mem_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2323 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:hyper_ram_avmm_s0_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2387 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:onchip_flash_data_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2451 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:nios_flash_avl_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2515 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:crypto_384_avmm_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2643 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:spi_master_avmm_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2707 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:bmc_dma_avmm_nios_slv_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2835 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:onchip_flash_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2899 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:i2c_1_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2963 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:jtag_ctrlr_bridge_s0_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3155 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:timer_0_s1_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3219 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:uart_console_s1_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3347 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:mctp_smbus_req_ram_s1_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3411 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:adc_sample_store_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3539 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:adc_sequencer_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3603 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:bmc_dma_avmm_mstr_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3684 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:max10_nios_data_master_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3765 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:max10_nios_instruction_master_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3846 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:mctp_smbus_resp_bridge_m0_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3927 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:mctp_smbus_req_bridge_m0_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4008 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:nios_flash_avl_mem_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4092 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:nios_flash_avl_mem_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:nios_flash_avl_mem_agent_rsp_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4133 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:hyper_ram_avmm_s0_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4342 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:hyper_ram_avmm_s0_agent_rsp_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4383 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:nios_flash_avl_csr_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4592 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:crypto_384_avmm_csr_agent_rdata_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4924 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:mctp_smbus_req_ram_s1_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6383 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:mctp_smbus_req_ram_s1_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:mctp_smbus_req_ram_s1_agent_rsp_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6424 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router:router" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6815 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router:router|max10_qsys_mm_interconnect_3_router_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router.sv Line: 180 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_001:router_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6831 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_001_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_001:router_001|max10_qsys_mm_interconnect_3_router_001_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_001.sv Line: 200 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_002" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_002:router_002" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6847 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_002_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_002:router_002|max10_qsys_mm_interconnect_3_router_002_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_002.sv Line: 181 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_003" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_003:router_003" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6863 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_003_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_003:router_003|max10_qsys_mm_interconnect_3_router_003_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_003.sv Line: 174 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_004" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_004:router_004" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6879 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_004_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_004:router_004|max10_qsys_mm_interconnect_3_router_004_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_004.sv Line: 174 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_005" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_005:router_005" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6895 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_005_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_005:router_005|max10_qsys_mm_interconnect_3_router_005_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_005.sv Line: 178 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_006" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_006:router_006" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6911 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_006_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_006:router_006|max10_qsys_mm_interconnect_3_router_006_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_006.sv Line: 173 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_007" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_007:router_007" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6927 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_007_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_007:router_007|max10_qsys_mm_interconnect_3_router_007_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_007.sv Line: 178 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_009" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_009:router_009" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6959 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_009_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_009:router_009|max10_qsys_mm_interconnect_3_router_009_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_009.sv Line: 173 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_023" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_023:router_023" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7183 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_023_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_023:router_023|max10_qsys_mm_interconnect_3_router_023_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_023.sv Line: 173 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_024" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_024:router_024" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7199 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_024_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_024:router_024|max10_qsys_mm_interconnect_3_router_024_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_024.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_traffic_limiter:bmc_dma_avmm_mstr_limiter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7281 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_traffic_limiter:max10_nios_data_master_limiter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7331 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_traffic_limiter:max10_nios_instruction_master_limiter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7381 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7431 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778 Info (12128): Elaborating entity "altera_merlin_burst_adapter_burstwrap_increment" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 979 Info (12128): Elaborating entity "altera_merlin_burst_adapter_min" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 1004 Info (12128): Elaborating entity "altera_merlin_burst_adapter_subtractor" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 157 Info (12128): Elaborating entity "altera_merlin_burst_adapter_adder" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 88 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:fpga_flash_avl_mem_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7481 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:fpga_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:hyper_ram_avmm_s0_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7531 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:hyper_ram_avmm_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_csr_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7631 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_csr_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:mctp_smbus_req_ram_s1_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8331 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:mctp_smbus_req_ram_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:mctp_smbus_req_ram_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778 Warning (10230): Verilog HDL assignment warning at altera_merlin_address_alignment.sv(155): truncated value with size 4 to match size of target (2) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv Line: 155 Warning (10230): Verilog HDL assignment warning at altera_merlin_address_alignment.sv(259): truncated value with size 34 to match size of target (32) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv Line: 259 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_demux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_demux:cmd_demux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8504 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_demux_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_demux_001:cmd_demux_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8647 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_demux_002" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_demux_002:cmd_demux_002" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8676 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_demux_003" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_demux_003:cmd_demux_003" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8693 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux:cmd_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8739 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux.sv Line: 301 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_mux_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux_001:cmd_mux_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8762 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_001.sv Line: 287 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_mux_004" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux_004:cmd_mux_004" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8825 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_mux_018" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux_018:cmd_mux_018" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9069 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux:rsp_demux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9155 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux_001:rsp_demux_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9178 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux_004" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux_004:rsp_demux_004" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9241 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux_006" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux_006:rsp_demux_006" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9275 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux_018" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux_018:rsp_demux_018" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9485 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux:rsp_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9565 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_mux_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_001:rsp_mux_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9708 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_001.sv Line: 630 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_mux_002" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_002:rsp_mux_002" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9737 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_002:rsp_mux_002|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_002.sv Line: 326 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_mux_003" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_003:rsp_mux_003" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9754 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_width_adapter:max10_nios_data_master_to_mctp_smbus_req_ram_s1_cmd_width_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9837 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_width_adapter:mctp_smbus_req_ram_s1_to_max10_nios_data_master_rsp_width_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9969 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Line: 742 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Line: 743 Info (12128): Elaborating entity "altera_avalon_st_handshake_clock_crosser" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 10069 Info (12128): Elaborating entity "altera_avalon_st_clock_crosser" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 149 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_avalon_st_adapter_018" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_avalon_st_adapter_018:avalon_st_adapter_018" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 10654 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_avalon_st_adapter_018:avalon_st_adapter_018|max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0:error_adapter_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018.v Line: 200 Info (12128): Elaborating entity "max10_qsys_irq_mapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_irq_mapper:irq_mapper" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1389 Info (12128): Elaborating entity "fpga_flash_if_ctrl" for hierarchy "fpga_flash_if_ctrl:fpga_flash_if_ctrl_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 811 Info (12128): Elaborating entity "fpga_qspi_filter" for hierarchy "fpga_flash_if_ctrl:fpga_flash_if_ctrl_inst|fpga_qspi_filter:fpga_qspi_filter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_flash_if_ctrl.sv Line: 157 Info (12128): Elaborating entity "bmc_sync" for hierarchy "fpga_flash_if_ctrl:fpga_flash_if_ctrl_inst|bmc_sync:error_sync" File: /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_flash_if_ctrl.sv Line: 320 Info (12128): Elaborating entity "mctp_over_smbus" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 857 Info (12128): Elaborating entity "pldm_over_mctp_top_controller" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_over_smbus.sv Line: 263 Info (12128): Elaborating entity "mctp_slow_clk_pulse" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_slow_clk_pulse:slow_clk_pulse_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 472 Info (12128): Elaborating entity "mctp_debouncer" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 491 Info (12128): Elaborating entity "smbus_arp_controller" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 721 Warning (10036): Verilog HDL or VHDL warning at smbus_arp_controller.v(153): object "smbus_scl_cycle_start" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 153 Info (12128): Elaborating entity "smbus_crc" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_crc:crc8_calc_arp_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 2115 Info (12128): Elaborating entity "pldm_over_mctp_req_ctrl" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 804 Warning (10036): Verilog HDL or VHDL warning at pldm_over_mctp_req_ctrl.v(158): object "mm_bridge_req_s0_readdata" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 158 Warning (10036): Verilog HDL or VHDL warning at pldm_over_mctp_req_ctrl.v(159): object "mm_bridge_req_s0_readdatavalid" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 159 Info (12128): Elaborating entity "pldm_over_mctp_resp_ctrl" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 867 Info (10264): Verilog HDL Case Statement information at pldm_over_mctp_resp_ctrl.v(1327): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 1327 Info (12128): Elaborating entity "svid_controller" for hierarchy "svid_controller:svid_ctrlr_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 883 Warning (10763): Verilog HDL warning at svid_controller.sv(257): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 257 Warning (10958): SystemVerilog warning at svid_controller.sv(257): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 257 Info (12128): Elaborating entity "bmc_sync" for hierarchy "svid_controller:svid_ctrlr_inst|bmc_sync:sdm_pmbus_alert" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 201 Info (12128): Elaborating entity "lpm_mult" for hierarchy "svid_controller:svid_ctrlr_inst|lpm_mult:vout_mult_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 484 Info (12130): Elaborated megafunction instantiation "svid_controller:svid_ctrlr_inst|lpm_mult:vout_mult_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 484 Info (12133): Instantiated megafunction "svid_controller:svid_ctrlr_inst|lpm_mult:vout_mult_inst" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 484 Info (12134): Parameter "lpm_hint" = "INPUT_B_IS_CONSTANT=YES,DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5" Info (12134): Parameter "lpm_pipeline" = "2" Info (12134): Parameter "lpm_representation" = "UNSIGNED" Info (12134): Parameter "lpm_type" = "LPM_MULT" Info (12134): Parameter "lpm_widtha" = "18" Info (12134): Parameter "lpm_widthb" = "18" Info (12134): Parameter "lpm_widthp" = "36" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_2ru.tdf Info (12023): Found entity 1: mult_2ru File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mult_2ru.tdf Line: 29 Info (12128): Elaborating entity "mult_2ru" for hierarchy "svid_controller:svid_ctrlr_inst|lpm_mult:vout_mult_inst|mult_2ru:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_mult.tdf Line: 377 Info (12128): Elaborating entity "svid_i2c_wrapper" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 594 Warning (10763): Verilog HDL warning at svid_i2c_wrapper.sv(107): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Line: 107 Warning (10958): SystemVerilog warning at svid_i2c_wrapper.sv(107): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Line: 107 Info (12128): Elaborating entity "svid_i2c_master" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Line: 277 Info (12128): Elaborating entity "altera_avalon_i2c" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/svid_i2c_master.v Line: 54 Info (12128): Elaborating entity "altera_avalon_i2c_csr" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_csr:u_csr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 212 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(257): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 257 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(258): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 258 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(259): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 259 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(269): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 269 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(270): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 270 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(271): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 271 Info (12128): Elaborating entity "altera_avalon_i2c_mstfsm" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_mstfsm:u_mstfsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 267 Info (12128): Elaborating entity "altera_avalon_i2c_rxshifter" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_rxshifter:u_rxshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 296 Info (12128): Elaborating entity "altera_avalon_i2c_txshifter" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_txshifter:u_txshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 325 Info (12128): Elaborating entity "altera_avalon_i2c_spksupp" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_spksupp:u_spksupp" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 336 Info (12128): Elaborating entity "altera_avalon_i2c_condt_det" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_condt_det:u_condt_det" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 364 Info (12128): Elaborating entity "altera_avalon_i2c_condt_gen" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_condt_gen:u_condt_gen" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 402 Info (12128): Elaborating entity "altera_avalon_i2c_clk_cnt" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_clk_cnt:u_clk_cnt" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 448 Info (12128): Elaborating entity "altera_avalon_i2c_txout" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_txout:u_txout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 471 Info (12128): Elaborating entity "altera_avalon_i2c_fifo" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 496 Info (10264): Verilog HDL Case Statement information at altera_avalon_i2c_fifo.v(129): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12130): Elaborated megafunction instantiation "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12133): Instantiated megafunction "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "power_up_uninitialized" = "TRUE" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "width_a" = "10" Info (12134): Parameter "width_b" = "10" Info (12134): Parameter "widthad_a" = "3" Info (12134): Parameter "widthad_b" = "3" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "numwords_a" = "8" Info (12134): Parameter "numwords_b" = "8" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_d3b1.tdf Info (12023): Found entity 1: altsyncram_d3b1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_d3b1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_d3b1" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram|altsyncram_d3b1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_avalon_i2c_fifo" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 518 Info (10264): Verilog HDL Case Statement information at altera_avalon_i2c_fifo.v(129): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12130): Elaborated megafunction instantiation "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12133): Instantiated megafunction "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "power_up_uninitialized" = "TRUE" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "width_a" = "8" Info (12134): Parameter "width_b" = "8" Info (12134): Parameter "widthad_a" = "3" Info (12134): Parameter "widthad_b" = "3" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "numwords_a" = "8" Info (12134): Parameter "numwords_b" = "8" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r0b1.tdf Info (12023): Found entity 1: altsyncram_r0b1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_r0b1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_r0b1" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram|altsyncram_r0b1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "top_misc_interconnect" for hierarchy "top_misc_interconnect:top_misc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 996 Warning (10036): Verilog HDL or VHDL warning at top_misc_interconnect.sv(172): object "dummy_assign" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 172 Info (12128): Elaborating entity "bmc_sync" for hierarchy "top_misc_interconnect:top_misc_inst|bmc_sync:i2c_sync" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 574 Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following RAM node(s): Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 40 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 70 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 100 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 130 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 160 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 190 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 220 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 250 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 280 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 310 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 340 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 370 Info (13014): Ignored 8 buffer(s) Info (13016): Ignored 8 CARRY_SUM buffer(s) Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13049): Converted tri-state buffer "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|flash_ncs[0]" feeding internal logic into a wire File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Line: 105 Warning (13049): Converted tri-state buffer "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|flash_sck[0]" feeding internal logic into a wire File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Line: 104 Info (276014): Found 1 instances of uninferred RAM logic Info (276004): RAM logic "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|data_array" is uninferred due to inappropriate RAM size File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 76 Info (19000): Inferred 3 megafunctions from design logic Info (276029): Inferred altsyncram megafunction from the following design logic: "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_sc_fifo:avst_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 34 Info (286033): Parameter WIDTHAD_A set to 8 Info (286033): Parameter NUMWORDS_A set to 256 Info (286033): Parameter WIDTH_B set to 34 Info (286033): Parameter WIDTHAD_B set to 8 Info (286033): Parameter NUMWORDS_B set to 256 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (276029): Inferred altsyncram megafunction from the following design logic: "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 33 Info (286033): Parameter WIDTHAD_A set to 6 Info (286033): Parameter NUMWORDS_A set to 64 Info (286033): Parameter WIDTH_B set to 33 Info (286033): Parameter WIDTHAD_B set to 6 Info (286033): Parameter NUMWORDS_B set to 64 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (276029): Inferred altsyncram megafunction from the following design logic: "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 33 Info (286033): Parameter WIDTHAD_A set to 6 Info (286033): Parameter NUMWORDS_A set to 64 Info (286033): Parameter WIDTH_B set to 33 Info (286033): Parameter WIDTHAD_B set to 6 Info (286033): Parameter NUMWORDS_B set to 64 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (278001): Inferred 4 megafunctions from design logic Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p3|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mult_384x9:i_m384_9|Mult0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Line: 21 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_sc_fifo:avst_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_sc_fifo:avst_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "34" Info (12134): Parameter "WIDTHAD_A" = "8" Info (12134): Parameter "NUMWORDS_A" = "256" Info (12134): Parameter "WIDTH_B" = "34" Info (12134): Parameter "WIDTHAD_B" = "8" Info (12134): Parameter "NUMWORDS_B" = "256" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_uag1.tdf Info (12023): Found entity 1: altsyncram_uag1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_uag1.tdf Line: 28 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "33" Info (12134): Parameter "WIDTHAD_A" = "6" Info (12134): Parameter "NUMWORDS_A" = "64" Info (12134): Parameter "WIDTH_B" = "33" Info (12134): Parameter "WIDTHAD_B" = "6" Info (12134): Parameter "NUMWORDS_B" = "64" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_i7g1.tdf Info (12023): Found entity 1: altsyncram_i7g1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_i7g1.tdf Line: 28 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" with the following parameter: File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (12134): Parameter "LPM_WIDTHA" = "17" Info (12134): Parameter "LPM_WIDTHB" = "17" Info (12134): Parameter "LPM_WIDTHP" = "34" Info (12134): Parameter "LPM_WIDTHR" = "34" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_9401.tdf Info (12023): Found entity 1: mult_9401 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mult_9401.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" with the following parameter: File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (12134): Parameter "LPM_WIDTHA" = "16" Info (12134): Parameter "LPM_WIDTHB" = "16" Info (12134): Parameter "LPM_WIDTHP" = "32" Info (12134): Parameter "LPM_WIDTHR" = "32" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_9b01.tdf Info (12023): Found entity 1: mult_9b01 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mult_9b01.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mult_384x9:i_m384_9|lpm_mult:Mult0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Line: 21 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mult_384x9:i_m384_9|lpm_mult:Mult0" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Line: 21 Info (12134): Parameter "LPM_WIDTHA" = "384" Info (12134): Parameter "LPM_WIDTHB" = "8" Info (12134): Parameter "LPM_WIDTHP" = "392" Info (12134): Parameter "LPM_WIDTHR" = "392" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "5" Info (12134): Parameter "DEDICATED_MULTIPLIER_CIRCUITRY" = "YES" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_mu01.tdf Info (12023): Found entity 1: mult_mu01 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mult_mu01.tdf Line: 31 Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (13014): Ignored 916 buffer(s) Info (13019): Ignored 916 SOFT buffer(s) Warning (13050): Open-drain buffer(s) that do not directly drive top-level pin(s) are removed Warning (13051): Converted the fanout from the open-drain buffer "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|nconfig_opndrn" to the node "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|bmc_sync:sync_nconfig|altera_std_synchronizer_nocut:sync_loop[0].sync_nocut|din_s1" into a wire File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 543 Warning (13051): Converted the fanout from the open-drain buffer "flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|csr_pwr_seq.debug_pwr_sequencer_sts_2[23]" to the node "csr_top:csr_top_inst|Mux8" into a wire File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 43 Info (13000): Registers with preset signals will power-up high File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 706 Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "hram_ck_n" is stuck at VCC File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 86 Info (286030): Timing-Driven Synthesis is running Info (17049): 1736 registers lost all their fanouts during netlist optimizations. Info (17016): Found the following redundant logic cells in design Info (17048): Logic cell "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_shiftnld" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 358 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_regin" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 293 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_scl_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 240 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_scl_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 242 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 244 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_sda_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 241 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_sda_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 243 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_sda_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 245 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_interrupt_n" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 289 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_idle_assert" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 266 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_idle_assert" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 280 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_multi_pkt_msg_flag" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 287 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_multi_pkt" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 321 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_mctp_message_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 338 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_slow_clk_pulse:slow_clk_pulse_inst0|ctr_bit8" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_slow_clk_pulse.v Line: 14 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|scl_in_valid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 238 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_packet_valid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 282 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_multi_pkt_msg_flag_exded" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 288 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_valid_config" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 330 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_valid_received" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 283 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_valid_debug_mode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 329 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[127]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_payload_buffer_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 168 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_message_flag_to_expected" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 167 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_headers_debug_mode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 328 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_message_interrupt_clr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 169 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_packet_num[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 293 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_multi_pkt_timeout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 310 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_packet_num[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 293 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_state_timeout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 309 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_state_timeout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 267 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_message_receive_ready" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 165 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_packet_num[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 322 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_packet_num[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 322 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_ready" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 320 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|sda_in" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 229 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|scl_in" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 228 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[126]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[119]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_message_flag_to_config" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 170 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_packet_num[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 293 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pkt_smbus_pec_valid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 308 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_state_timeout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 341 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[125]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[118]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[111]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_cmd_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 214 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_mctp_packet_busy_pos" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 337 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[124]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[117]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_device_address_type[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 133 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[110]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[103]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[120]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[121]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[122]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[123]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[116]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[109]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[102]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[95]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[112]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[113]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[114]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[115]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_message_flag_to" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[108]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[101]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[94]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[87]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[104]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[105]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[106]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[107]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_message_flag_to_debug_mode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_tag[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 129 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[100]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[93]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[86]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[79]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[96]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[97]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[98]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[99]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_flag_to_debug_mode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 327 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_tag[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 129 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 316 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 315 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_2|flush1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 45 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_2|flush0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 46 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_1|flush1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 45 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_1|flush0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 46 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[92]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[85]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[78]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[71]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[88]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[89]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[90]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[91]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_tag[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 129 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_tag_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 335 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_msg_flag_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 306 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[84]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[77]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[70]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[63]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[80]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[81]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[82]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[83]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_tag_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 335 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_msg_flag_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 306 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_2|flush2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 44 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_1|flush2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 44 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[76]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[69]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[62]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[55]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[72]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[73]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[74]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[75]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_tag_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 335 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_msg_flag_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 306 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[68]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[61]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[54]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[47]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[64]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[65]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[66]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[67]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[60]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[53]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[46]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[39]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[56]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[57]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[58]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[59]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[52]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[45]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[38]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[48]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[49]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[50]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[51]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[44]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[37]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[40]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[41]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[42]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[43]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[36]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[32]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[33]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[34]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[35]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (128000): Starting physical synthesis optimizations for speed Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_b2i1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_gd9:dffpipe9|dffe10a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a* Info (332165): Entity dcfifo_e9h1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a* Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.sdc' Info (332104): Reading SDC File: 'acadp_bmc_max10.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[2]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[4]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|dataa" Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 19 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 100.000 clk_10m Info (332111): 40.000 clk_25m Info (332111): 20.000 clk_50m Info (332111): 10.000 clk_100m Info (332111): 10.000 clk_100m_p90 Info (332111): 40.000 egrs_spi_clk Info (332111): 40.000 egrs_spi_clk_int Info (332111): 40.000 flash_se_neg_reg Info (332111): 20.000 fpga_avst_clk Info (332111): 40.000 fpga_qspi_clk Info (332111): 10.000 hram_clk Info (332111): 10.000 hram_rwds_clk Info (332111): 10.000 hram_rwds_virt Info (332111): 40.000 ingrs_spi_clk Info (332111): 10.000 m10_clk_100m Info (332111): 181.818 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332111): 40.000 nqspi_sclk Info (332111): 40.000 nqspi_sclk_int Info (332111): 40.000 ru_clk Info (128002): Starting physical synthesis algorithm register retiming Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:15 Info (144001): Generated suppressed messages file /home/admin/otc/ofs-bmc/rtl/max10/build/output_files_factory/acadp_bmc_max10_factory.map.smsg Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 1 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "hps_cold_reset_n" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 124 Info (21057): Implemented 51882 device resources after synthesis - the final resource count might be different Info (21058): Implemented 64 input pins Info (21059): Implemented 63 output pins Info (21060): Implemented 30 bidirectional pins Info (21061): Implemented 49602 logic cells Info (21064): Implemented 2047 RAM segments Info (21065): Implemented 1 PLLs Info (21062): Implemented 51 DSP elements Info (21070): Implemented 1 User Flash Memory blocks Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 186 warnings Info: Peak virtual memory: 1533 megabytes Info: Processing ended: Wed Apr 3 13:46:15 2024 Info: Elapsed time: 00:04:59 Info: Total CPU time (on all processors): 00:04:54 ............................................................................................... 2024-04-03 13:46:15 :: Building with seed = 1 2024-04-03 13:46:15 :: Running Fitter... Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 13:46:15 2024 Info: Command: quartus_fit acadp_bmc_max10 --rev=acadp_bmc_max10_factory --seed=1 Info: qfit2_default_script.tcl version: #1 Info: Project = acadp_bmc_max10 Info: Revision = acadp_bmc_max10_factory Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (119006): Selected device 10M50DAF256I6G for design "acadp_bmc_max10_factory" Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (15535): Implemented PLL "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|pll1" as MAX 10 PLL type File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (15099): Implementing clock multiplication of 1, clock division of 2, and phase shift of 0 degrees (0 ps) for max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|dual_boot_int_clk port File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (15099): Implementing clock multiplication of 1, clock division of 4, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of 120 degrees (3333 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[3] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 10, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[4] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device 10M16DAF256I6G is compatible Info (176445): Device 10M25DAF256I6G is compatible Info (176445): Device 10M40DAF256I6G is compatible Info (176445): Device 10M40DAF256I6GVM is compatible Info (169124): Fitter converted 3 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_JTAGEN~ is reserved at location G6 Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location F8 Info (169125): Pin ~ALTERA_CRC_ERROR~ is reserved at location C5 Info (169141): DATA[0] dual-purpose pin not reserved Info (12825): Data[1]/ASDO dual-purpose pin not reserved Info (12825): nCSO dual-purpose pin not reserved Info (12825): DCLK dual-purpose pin not reserved Info (169124): Fitter converted 16 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_ADC1IN1~ is reserved at location F5 Info (169125): Pin ~ALTERA_ADC2IN1~ is reserved at location C4 Info (169125): Pin ~ALTERA_ADC1IN2~ is reserved at location F4 Info (169125): Pin ~ALTERA_ADC2IN8~ is reserved at location C3 Info (169125): Pin ~ALTERA_ADC1IN3~ is reserved at location H5 Info (169125): Pin ~ALTERA_ADC2IN3~ is reserved at location E3 Info (169125): Pin ~ALTERA_ADC1IN4~ is reserved at location G5 Info (169125): Pin ~ALTERA_ADC2IN4~ is reserved at location F2 Info (169125): Pin ~ALTERA_ADC1IN5~ is reserved at location G2 Info (169125): Pin ~ALTERA_ADC2IN5~ is reserved at location C2 Info (169125): Pin ~ALTERA_ADC1IN6~ is reserved at location F1 Info (169125): Pin ~ALTERA_ADC2IN6~ is reserved at location B2 Info (169125): Pin ~ALTERA_ADC1IN7~ is reserved at location E1 Info (169125): Pin ~ALTERA_ADC2IN7~ is reserved at location B1 Info (169125): Pin ~ALTERA_ADC1IN8~ is reserved at location D1 Info (169125): Pin ~ALTERA_ADC2IN2~ is reserved at location C1 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_b2i1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_gd9:dffpipe9|dffe10a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a* Info (332165): Entity dcfifo_e9h1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a* Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.sdc' Info (332104): Reading SDC File: 'acadp_bmc_max10.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[2]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[4]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|dataa" Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 19 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 100.000 clk_10m Info (332111): 40.000 clk_25m Info (332111): 20.000 clk_50m Info (332111): 10.000 clk_100m Info (332111): 10.000 clk_100m_p90 Info (332111): 40.000 egrs_spi_clk Info (332111): 40.000 egrs_spi_clk_int Info (332111): 40.000 flash_se_neg_reg Info (332111): 20.000 fpga_avst_clk Info (332111): 40.000 fpga_qspi_clk Info (332111): 10.000 hram_clk Info (332111): 10.000 hram_rwds_clk Info (332111): 10.000 hram_rwds_virt Info (332111): 40.000 ingrs_spi_clk Info (332111): 10.000 m10_clk_100m Info (332111): 181.818 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332111): 40.000 nqspi_sclk Info (332111): 40.000 nqspi_sclk_int Info (332111): 40.000 ru_clk Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C3 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[3] (placed in counter C4 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 Info (176353): Automatically promoted node m10_clk_100m~input (placed in PIN P8 (CLK6p, DIFFIO_TX_RX_B18p, DIFFOUT_B18p, High_Speed)) File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 25 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|dual_boot_int_clk (placed in counter C1 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 Info (176353): Automatically promoted node ingrs_spi_clk~input (placed in PIN L3 (CLK0p, DIFFIO_RX_L28p, DIFFOUT_L28p, High_Speed)) File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 98 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_block:altera_onchip_flash_block|osc File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/altera_onchip_flash_block.v Line: 147 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_waitrequest~3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 180 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_waitrequest~6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 180 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|next_state.STATE_SAME~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 127 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~31 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~33 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|write_operation~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 80 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~36 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~40 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~44 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|always9~0 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|rst_sync_50m[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 56 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|fpga_pwr_dwn File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 154 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|cvl_pwr_dwn File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 155 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[3] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[4] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[5] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node top_misc_interconnect:top_misc_inst|cfg_qspi0_rst_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 107 Info (176357): Destination node top_misc_interconnect:top_misc_inst|ptp_clk_rst_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 105 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|crypto_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 136 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[4] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[3] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|rflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|done File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|aflag[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|aflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|rflag[9] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|last_word_detect File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 118 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_ole:auto_generated|_~0 File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|comb~0 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|last_word_detect File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 118 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_nios_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_ole:auto_generated|_~0 File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|comb~0 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|in_t2_sel.01~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 32 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|dma_reset_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 105 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_resp_reset_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 348 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module:SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 654 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|MISOctl:SPIPhy_MISOctl|spi_domain_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 544 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 139 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_1|adjusting File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Line: 27 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_2|adjusting File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Line: 27 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|entropy_sel File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 60 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|consecutive_zeros File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|consecutive_ones File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 21 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|repeated_bits File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 22 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|consecutive_zeros File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|consecutive_ones File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 21 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|repeated_bits File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 22 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|race2_ok_i File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 59 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hbus_rwds_rst File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 156 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hbus_rwds_rst~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 156 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|locked File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 40 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|Selector1~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|Selector1~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|Selector0~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|Selector0~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|rst_sync_100m[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 129 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176218): Packed 134 registers into blocks of type Block RAM Extra Info (176218): Packed 48 registers into blocks of type Embedded multiplier block Extra Info (176218): Packed 64 registers into blocks of type Embedded multiplier output Extra Info (176218): Packed 6 registers into blocks of type I/O Input Buffer Extra Info (176218): Packed 7 registers into blocks of type I/O Output Buffer Extra Info (176220): Created 55 register duplicates Warning (15064): PLL "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "fpga_avst_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (128000): Starting physical synthesis optimizations for speed Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:15 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:55 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:16 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:02:02 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 29% of the available device resources Info (170196): Router estimated peak interconnect usage is 64% of the available device resources in the region that extends from location X22_Y22 to location X32_Y32 Info (170194): Fitter routing operations ending: elapsed time is 00:02:42 Info (11888): Total time spent on timing analysis during the Fitter is 146.37 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:32 Warning (169177): 42 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin bmc_smclk uses I/O standard 3.3-V LVCMOS at N5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 28 Info (169178): Pin bmc_smdat uses I/O standard 3.3-V LVCMOS at R1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 29 Info (169178): Pin m10_i2c_3v3_scl uses I/O standard 3.3-V LVCMOS at P4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 34 Info (169178): Pin m10_i2c_3v3_sda uses I/O standard 3.3-V LVCMOS at P2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 35 Info (169178): Pin pm_scl_3v3 uses I/O standard 3.3-V LVCMOS at R3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 38 Info (169178): Pin pm_sda_3v3 uses I/O standard 3.3-V LVCMOS at L7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 39 Info (169178): Pin vid_scl_3v3 uses I/O standard 3.3-V LVCMOS at A9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 44 Info (169178): Pin vid_sda_3v3 uses I/O standard 3.3-V LVCMOS at B8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 45 Info (169178): Pin gf_pcie_perst_n uses I/O standard 3.3-V LVCMOS at M9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 133 Info (169178): Pin m10_clk_100m uses I/O standard 3.3-V LVCMOS at P8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 25 Info (169178): Pin pg_vtt_0v6 uses I/O standard 3.3-V LVCMOS at B7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 168 Info (169178): Pin pg_vcc_3v3 uses I/O standard 3.3-V LVCMOS at A11 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 184 Info (169178): Pin pg_vcc_5v uses I/O standard 3.3-V LVCMOS at C10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 183 Info (169178): Pin pg_vcch_0v9 uses I/O standard 3.3-V LVCMOS at A3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 179 Info (169178): Pin pg_vccl_fpga_vid uses I/O standard 3.3-V LVCMOS at A5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 178 Info (169178): Pin pg_vcca_1v8 uses I/O standard 3.3-V LVCMOS at B9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 169 Info (169178): Pin pg_vcch_gxer_1v1 uses I/O standard 3.3-V LVCMOS at A12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 188 Info (169178): Pin pg_vcc_1v2 uses I/O standard 3.3-V LVCMOS at A2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 180 Info (169178): Pin pg_vcc_1v1_cvl uses I/O standard 3.3-V LVCMOS at C6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 174 Info (169178): Pin pg_avddh_1v1_cvl uses I/O standard 3.3-V LVCMOS at A6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 175 Info (169178): Pin pg_avdd_pcie_0v9_cvl uses I/O standard 3.3-V LVCMOS at B4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 177 Info (169178): Pin pg_avdd_eth_0v9_cvl uses I/O standard 3.3-V LVCMOS at B5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 176 Info (169178): Pin pg_vdd_0v8_cvl uses I/O standard 3.3-V LVCMOS at A7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 173 Info (169178): Pin qsfpa_modpres uses I/O standard 3.3-V LVCMOS at D12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 142 Info (169178): Pin qsfpb_modpres uses I/O standard 3.3-V LVCMOS at C13 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 143 Info (169178): Pin pcie_clk_los uses I/O standard 3.3-V LVCMOS at B10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 192 Info (169178): Pin pg_12v_aux_efuse uses I/O standard 3.3-V LVCMOS at B3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 181 Info (169178): Pin pg_12v_pcie_efuse uses I/O standard 3.3-V LVCMOS at A4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 182 Info (169178): Pin vcc_3v3_pcie_uv uses I/O standard 3.3-V LVCMOS at M8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 165 Info (169178): Pin vcc_12v_pcie_uv uses I/O standard 3.3-V LVCMOS at R9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 164 Info (169178): Pin edge_pwr_shdn uses I/O standard 3.3-V LVCMOS at T2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 57 Info (169178): Pin pg_pwr_qsfp0n uses I/O standard 3.3-V LVCMOS at A8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 171 Info (169178): Pin pg_pwr_qsfp1n uses I/O standard 3.3-V LVCMOS at B6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 172 Info (169178): Pin pm_alertn_3v3 uses I/O standard 3.3-V LVCMOS at R4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 41 Info (169178): Pin fpga_therm_alertn uses I/O standard 3.3-V LVCMOS at A15 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 53 Info (169178): Pin vr_vid_alertn uses I/O standard 3.3-V LVCMOS at T3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 48 Info (169178): Pin edge_pwr_warn uses I/O standard 3.3-V LVCMOS at P5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 56 Info (169178): Pin si5392_lol uses I/O standard 3.3-V LVCMOS at A10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 195 Info (169178): Pin ptp_clk_lol uses I/O standard 3.3-V LVCMOS at R6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 193 Info (169178): Pin alert_power2 uses I/O standard 3.3-V LVCMOS at E10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 202 Info (169178): Pin io_expndr_int_n uses I/O standard 3.3-V LVCMOS at R5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 199 Info (169178): Pin nios_uart_rx uses I/O standard 3.3-V LVCMOS at F12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 207 Critical Warning (16248): Pin m10_jtag_tck is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 72 Critical Warning (16248): Pin m10_jtag_tms is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 73 Critical Warning (16248): Pin m10_jtag_tdi is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 74 Critical Warning (16248): Pin strap_1_pclass1 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 197 Critical Warning (16248): Pin strap_3_cvl_prsnt0_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 141 Critical Warning (16248): Pin pg_vpp_2v5 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 170 Critical Warning (16248): Pin fpga_therm_shdn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 51 Critical Warning (16248): Pin m10_jtag_tdo is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 75 Critical Warning (16248): Pin m10_jtagen_sw is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 76 Critical Warning (16248): Pin fpga_qspi_cs_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 94 Critical Warning (16248): Pin ingrs_spi_csn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 99 Critical Warning (16248): Pin egrs_spi_csn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 103 Critical Warning (16248): Pin fpga_fabric_reset_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 136 Critical Warning (16248): Pin m10_status_led_g is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 127 Critical Warning (16248): Pin en_avdd_eth_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 155 Critical Warning (16248): Pin en_avdd_pcie_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 156 Critical Warning (16248): Pin en_vccl_fpga_vid is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 157 Critical Warning (16248): Pin en_vcc_1v2 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 158 Critical Warning (16248): Pin vid_scl_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 44 Critical Warning (16248): Pin vid_sda_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 45 Critical Warning (16248): Pin pg_vtt_0v6 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 168 Critical Warning (16248): Pin pg_vcc_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 184 Critical Warning (16248): Pin pg_vcc_5v is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 183 Critical Warning (16248): Pin pg_vcch_0v9 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 179 Critical Warning (16248): Pin pg_vccl_fpga_vid is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 178 Critical Warning (16248): Pin pg_vcca_1v8 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 169 Critical Warning (16248): Pin pg_vcch_gxer_1v1 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 188 Critical Warning (16248): Pin pg_vcc_1v2 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 180 Critical Warning (16248): Pin pg_vcc_1v1_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 174 Critical Warning (16248): Pin pg_avddh_1v1_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 175 Critical Warning (16248): Pin pg_avdd_pcie_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 177 Critical Warning (16248): Pin pg_avdd_eth_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 176 Critical Warning (16248): Pin pg_vdd_0v8_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 173 Critical Warning (16248): Pin pcie_clk_los is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 192 Critical Warning (16248): Pin pg_12v_aux_efuse is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 181 Critical Warning (16248): Pin pg_12v_pcie_efuse is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 182 Critical Warning (16248): Pin pg_pwr_qsfp0n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 171 Critical Warning (16248): Pin pg_pwr_qsfp1n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 172 Critical Warning (16248): Pin si5392_lol is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 195 Warning (169202): Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs. Info (144001): Generated suppressed messages file /home/admin/otc/ofs-bmc/rtl/max10/build/output_files_factory/acadp_bmc_max10_factory.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 56 warnings Info: Peak virtual memory: 3160 megabytes Info: Processing ended: Wed Apr 3 13:53:18 2024 Info: Elapsed time: 00:07:03 Info: Total CPU time (on all processors): 00:19:01 2024-04-03 13:53:19 :: Running Timing Analyzer... Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 13:53:19 2024 Info: Command: quartus_sta acadp_bmc_max10 --rev=acadp_bmc_max10_factory Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_b2i1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_gd9:dffpipe9|dffe10a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a* Info (332165): Entity dcfifo_e9h1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a* Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.sdc' Info (332104): Reading SDC File: 'acadp_bmc_max10.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[2]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[4]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|datac" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|datad" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|datad" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|datad" Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 100C Model Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Info (332146): Worst-case setup slack is 0.182 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.182 0.000 hram_clk Info (332119): 1.047 0.000 hram_rwds_clk Info (332119): 1.395 0.000 clk_100m Info (332119): 1.460 0.000 clk_50m Info (332119): 1.736 0.000 n/a Info (332119): 2.912 0.000 clk_100m_p90 Info (332119): 4.470 0.000 fpga_avst_clk Info (332119): 6.246 0.000 nqspi_sclk Info (332119): 6.718 0.000 egrs_spi_clk Info (332119): 7.449 0.000 m10_clk_100m Info (332119): 9.211 0.000 clk_25m Info (332119): 9.425 0.000 ingrs_spi_clk Info (332119): 12.737 0.000 fpga_qspi_clk Info (332119): 14.989 0.000 flash_se_neg_reg Info (332146): Worst-case hold slack is 0.194 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.194 0.000 clk_50m Info (332119): 0.233 0.000 hram_rwds_clk Info (332119): 0.303 0.000 clk_25m Info (332119): 0.331 0.000 m10_clk_100m Info (332119): 0.336 0.000 ingrs_spi_clk Info (332119): 0.368 0.000 fpga_qspi_clk Info (332119): 0.396 0.000 clk_100m Info (332119): 0.823 0.000 hram_clk Info (332119): 1.065 0.000 egrs_spi_clk Info (332119): 2.112 0.000 clk_100m_p90 Info (332119): 2.754 0.000 fpga_avst_clk Info (332119): 2.983 0.000 n/a Info (332119): 3.083 0.000 flash_se_neg_reg Info (332119): 5.030 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 3.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.666 0.000 clk_100m Info (332119): 4.517 0.000 clk_50m Info (332119): 4.914 0.000 ingrs_spi_clk Info (332119): 5.959 0.000 clk_100m_p90 Info (332119): 6.977 0.000 hram_rwds_clk Info (332119): 16.346 0.000 fpga_qspi_clk Info (332119): 34.683 0.000 clk_25m Info (332146): Worst-case removal slack is 0.956 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.956 0.000 clk_50m Info (332119): 1.332 0.000 clk_100m Info (332119): 1.783 0.000 hram_rwds_clk Info (332119): 2.517 0.000 ingrs_spi_clk Info (332119): 2.753 0.000 fpga_qspi_clk Info (332119): 3.665 0.000 clk_100m_p90 Info (332119): 3.994 0.000 clk_25m Info (332146): Worst-case minimum pulse width slack is 4.577 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.577 0.000 m10_clk_100m Info (332119): 4.671 0.000 clk_100m Info (332119): 4.672 0.000 hram_rwds_clk Info (332119): 4.733 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.707 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.706 0.000 flash_se_neg_reg Info (332119): 19.644 0.000 clk_25m Info (332119): 19.654 0.000 fpga_qspi_clk Info (332119): 19.689 0.000 ingrs_spi_clk Info (332119): 19.861 0.000 egrs_spi_clk_int Info (332119): 19.967 0.000 nqspi_sclk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.246 0.000 clk_10m Info (332119): 90.665 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 14.769 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info: Analyzing Slow 1200mV -40C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 0.346 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.346 0.000 hram_clk Info (332119): 1.145 0.000 hram_rwds_clk Info (332119): 1.756 0.000 clk_100m Info (332119): 2.627 0.000 clk_50m Info (332119): 2.652 0.000 n/a Info (332119): 3.108 0.000 clk_100m_p90 Info (332119): 5.698 0.000 fpga_avst_clk Info (332119): 6.285 0.000 nqspi_sclk Info (332119): 6.867 0.000 egrs_spi_clk Info (332119): 7.798 0.000 m10_clk_100m Info (332119): 9.462 0.000 ingrs_spi_clk Info (332119): 13.382 0.000 clk_25m Info (332119): 13.596 0.000 fpga_qspi_clk Info (332119): 15.652 0.000 flash_se_neg_reg Info (332146): Worst-case hold slack is 0.150 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.150 0.000 clk_50m Info (332119): 0.221 0.000 hram_rwds_clk Info (332119): 0.246 0.000 clk_25m Info (332119): 0.287 0.000 m10_clk_100m Info (332119): 0.291 0.000 ingrs_spi_clk Info (332119): 0.299 0.000 clk_100m Info (332119): 0.319 0.000 fpga_qspi_clk Info (332119): 1.064 0.000 hram_clk Info (332119): 1.437 0.000 egrs_spi_clk Info (332119): 2.057 0.000 clk_100m_p90 Info (332119): 2.236 0.000 fpga_avst_clk Info (332119): 2.606 0.000 flash_se_neg_reg Info (332119): 2.675 0.000 n/a Info (332119): 5.193 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 4.480 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.480 0.000 clk_100m Info (332119): 5.214 0.000 clk_50m Info (332119): 6.182 0.000 clk_100m_p90 Info (332119): 6.344 0.000 ingrs_spi_clk Info (332119): 7.278 0.000 hram_rwds_clk Info (332119): 16.718 0.000 fpga_qspi_clk Info (332119): 35.404 0.000 clk_25m Info (332146): Worst-case removal slack is 0.802 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.802 0.000 clk_50m Info (332119): 1.141 0.000 clk_100m Info (332119): 1.552 0.000 hram_rwds_clk Info (332119): 2.228 0.000 ingrs_spi_clk Info (332119): 2.266 0.000 fpga_qspi_clk Info (332119): 3.418 0.000 clk_100m_p90 Info (332119): 3.438 0.000 clk_25m Info (332146): Worst-case minimum pulse width slack is 4.585 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.585 0.000 m10_clk_100m Info (332119): 4.618 0.000 hram_rwds_clk Info (332119): 4.699 0.000 clk_100m Info (332119): 4.711 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.607 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.679 0.000 flash_se_neg_reg Info (332119): 19.667 0.000 clk_25m Info (332119): 19.714 0.000 ingrs_spi_clk Info (332119): 19.741 0.000 fpga_qspi_clk Info (332119): 19.936 0.000 egrs_spi_clk_int Info (332119): 19.945 0.000 nqspi_sclk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.255 0.000 clk_10m Info (332119): 90.661 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 15.244 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info: Analyzing Fast 1200mV -40C Model Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 0.081 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.081 0.000 hram_rwds_clk Info (332119): 0.502 0.000 hram_clk Info (332119): 2.656 0.000 clk_100m Info (332119): 4.083 0.000 clk_100m_p90 Info (332119): 5.785 0.000 clk_50m Info (332119): 5.945 0.000 n/a Info (332119): 7.151 0.000 nqspi_sclk Info (332119): 8.021 0.000 fpga_avst_clk Info (332119): 8.151 0.000 egrs_spi_clk Info (332119): 8.833 0.000 m10_clk_100m Info (332119): 9.735 0.000 ingrs_spi_clk Info (332119): 16.483 0.000 fpga_qspi_clk Info (332119): 17.475 0.000 flash_se_neg_reg Info (332119): 25.738 0.000 clk_25m Info (332146): Worst-case hold slack is 0.089 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.089 0.000 clk_50m Info (332119): 0.092 0.000 hram_rwds_clk Info (332119): 0.139 0.000 m10_clk_100m Info (332119): 0.143 0.000 ingrs_spi_clk Info (332119): 0.153 0.000 clk_25m Info (332119): 0.158 0.000 fpga_qspi_clk Info (332119): 0.182 0.000 clk_100m Info (332119): 0.660 0.000 fpga_avst_clk Info (332119): 0.682 0.000 flash_se_neg_reg Info (332119): 0.905 0.000 hram_clk Info (332119): 0.994 0.000 egrs_spi_clk Info (332119): 1.433 0.000 n/a Info (332119): 1.827 0.000 clk_100m_p90 Info (332119): 4.634 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 6.919 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 6.919 0.000 clk_100m Info (332119): 7.229 0.000 clk_100m_p90 Info (332119): 7.288 0.000 clk_50m Info (332119): 8.351 0.000 hram_rwds_clk Info (332119): 10.004 0.000 ingrs_spi_clk Info (332119): 18.116 0.000 fpga_qspi_clk Info (332119): 37.393 0.000 clk_25m Info (332146): Worst-case removal slack is 0.433 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.433 0.000 clk_50m Info (332119): 0.612 0.000 clk_100m Info (332119): 0.844 0.000 hram_rwds_clk Info (332119): 0.980 0.000 ingrs_spi_clk Info (332119): 1.152 0.000 fpga_qspi_clk Info (332119): 1.912 0.000 clk_25m Info (332119): 2.513 0.000 clk_100m_p90 Info (332146): Worst-case minimum pulse width slack is 3.532 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.532 0.000 m10_clk_100m Info (332119): 4.593 0.000 hram_rwds_clk Info (332119): 4.727 0.000 clk_100m Info (332119): 4.743 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.957 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.963 0.000 flash_se_neg_reg Info (332119): 19.699 0.000 fpga_qspi_clk Info (332119): 19.721 0.000 clk_25m Info (332119): 19.753 0.000 ingrs_spi_clk Info (332119): 19.966 0.000 nqspi_sclk_int Info (332119): 19.973 0.000 egrs_spi_clk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.904 0.000 clk_10m Info (332119): 90.689 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 17.524 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info (332101): Design is fully constrained for setup requirements Info (332101): Design is fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 13 warnings Info: Peak virtual memory: 1264 megabytes Info: Processing ended: Wed Apr 3 13:53:41 2024 Info: Elapsed time: 00:00:22 Info: Total CPU time (on all processors): 00:01:15 ....................BEGIN CRITICAL warnings (if any)........................................... ....................END CRITICAL warnings (if any)............................................. 2024-04-03 13:53:41 :: Timing OK 2024-04-03 13:53:41 :: Generating programming file... Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 13:53:42 2024 Info: Command: quartus_asm acadp_bmc_max10 --rev=acadp_bmc_max10_factory Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 814 megabytes Info: Processing ended: Wed Apr 3 13:53:47 2024 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 2024-04-03 13:53:47 :: - done 2024-04-03 13:53:47 :: Archiving project... Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 13:53:47 2024 Info: Command: quartus_sh --archive -output output_files_factory/acadp_bmc_max10_factory -include_output acadp_bmc_max10.qpf Info: Quartus(args): -qar -output output_files_factory/acadp_bmc_max10_factory -include_output acadp_bmc_max10.qpf Info: qar.tcl version #1 Info: File Set 'Compilation database and output' contains: Info: Project source and settings files Info: Automatically detected source files Info: Report files Info: Programming output files Info: Version-incompatible compilation database files Info: Incremental compilation and Rapid Recompile database files (version-incompatible) Warning: Hierarchical Platform Designer systems and custom IP components(_hw.tcl and associated files) are not archived by the Quartus Archiver Info: Archive will store files relative to the closest common parent directory Info (13213): Using common directory /home/admin/otc/ofs-bmc/ Info: ---------------------------------------------------------- Info: ---------------------------------------------------------- Info: Generated archive 'output_files_factory/acadp_bmc_max10_factory.qar' Info: ---------------------------------------------------------- Info: ---------------------------------------------------------- Info: Generated report 'acadp_bmc_max10_factory.archive.rpt' Info (23030): Evaluation of Tcl script /home/admin/intelFPGA/23.1std/quartus/common/tcl/apps/qpm/qar.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 1 warning Info: Peak virtual memory: 1006 megabytes Info: Processing ended: Wed Apr 3 13:53:52 2024 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 2024-04-03 13:53:52 :: - done ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:53:52 :: .. Building RTL .. mode=retail ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 13:53:52 :: rtl_revision=3.15.0, ver_hex=0x030f00 2024-04-03 13:53:52 :: rtl_set_factory: 0 2024-04-03 13:53:52 :: rtl_set_debug: 0 2024-04-03 13:53:52 :: Setting PROD_RELEASE to YES 2024-04-03 13:53:52 :: rtl_set_jtag: 0 2024-04-03 13:53:52 :: rtl_set_fruid: 0 2024-04-03 13:53:52 :: Setting FRUID_EEPROM_WP_ENABLE to YES 2024-04-03 13:53:52 :: Setting ENABLE_FLASH_FILTER to YES 2024-04-03 13:53:52 :: RTL: image_str=_retail, ver_hex=0x030f00, rtl_revision=3.15.0 2024-04-03 13:53:52 :: Running Synthesis... Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 13:53:53 2024 Info: Command: quartus_map acadp_bmc_max10 --rev=acadp_bmc_max10_retail Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Info (12023): Found entity 1: ram_sdp File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Info (12023): Found entity 1: jtag_cntrlr File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/jtag_ctrl_io_if.sv Info (12023): Found entity 1: jtag_ctrl_io_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/jtag_ctrl_io_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_jtg_ctrl_if.sv Info (12023): Found entity 1: csr_jtg_ctrl_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_jtg_ctrl_if.sv Line: 21 Info (12021): Found 1 design units, including 0 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/pkg_global.sv Info (12022): Found design unit 1: pkg_global (SystemVerilog) File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/pkg_global.sv Line: 22 Info (12021): Found 1 design units, including 0 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_smbus_pkg.sv Info (12022): Found design unit 1: mctp_smbus_pkg (SystemVerilog) File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_smbus_pkg.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_crc.v Info (12023): Found entity 1: smbus_crc File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_crc.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Info (12023): Found entity 1: smbus_arp_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Info (12023): Found entity 1: pldm_over_mctp_top_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Info (12023): Found entity 1: pldm_over_mctp_resp_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Info (12023): Found entity 1: pldm_over_mctp_req_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_slow_clk_pulse.v Info (12023): Found entity 1: mctp_slow_clk_pulse File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_slow_clk_pulse.v Line: 3 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Info (12023): Found entity 1: mctp_debouncer File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_over_smbus.sv Info (12023): Found entity 1: mctp_over_smbus File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_over_smbus.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_qspi_filter.sv Info (12023): Found entity 1: fpga_qspi_filter File: /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_qspi_filter.sv Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_flash_if_ctrl.sv Info (12023): Found entity 1: fpga_flash_if_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_flash_if_ctrl.sv Line: 48 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Info (12023): Found entity 1: power_sequencer File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Info (12023): Found entity 1: fpga_config_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Info (12023): Found entity 1: flow_control_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_io_if.sv Info (12023): Found entity 1: csr_io_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_io_if.sv Line: 21 Info (12021): Found 1 design units, including 0 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/csr/pkg_csr.sv Info (12022): Found design unit 1: pkg_csr (SystemVerilog) File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/pkg_csr.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Info (12023): Found entity 1: csr_ram File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Info (12023): Found entity 1: csr_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/common/debouncer.sv Info (12023): Found entity 1: debouncer File: /home/admin/otc/ofs-bmc/rtl/max10/design/common/debouncer.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/common/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut File: /home/admin/otc/ofs-bmc/rtl/max10/design/common/altera_std_synchronizer_nocut.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/common/bmc_sync.sv Info (12023): Found entity 1: bmc_sync File: /home/admin/otc/ofs-bmc/rtl/max10/design/common/bmc_sync.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Info (12023): Found entity 1: clk_rst_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/pwr_seq_brd_if.sv Info (12023): Found entity 1: pwr_seq_brd_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/pwr_seq_brd_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_pwr_seq_if.sv Info (12023): Found entity 1: csr_pwr_seq_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_pwr_seq_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_fconfig_if.sv Info (12023): Found entity 1: csr_fconfig_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_fconfig_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_flash_mux_if.sv Info (12023): Found entity 1: csr_flash_mux_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_flash_mux_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_mctp_smb_if.sv Info (12023): Found entity 1: csr_mctp_smb_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_mctp_smb_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_misc_if.sv Info (12023): Found entity 1: csr_misc_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_misc_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_svid_if.sv Info (12023): Found entity 1: csr_svid_if File: /home/admin/otc/ofs-bmc/rtl/max10/design/includes/csr_svid_if.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Info (12023): Found entity 1: svid_i2c_wrapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Info (12023): Found entity 1: svid_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Info (12023): Found entity 1: system_pll File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/misc_pll/misc_pll.v Info (12023): Found entity 1: misc_pll File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/misc_pll/misc_pll.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/pfl_ii.v Info (12023): Found entity 1: pfl_ii File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/pfl_ii.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Info (12023): Found entity 1: altera_parallel_flash_loader_2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg.v Info (12023): Found entity 1: altera_pfl2_cfg File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Info (12023): Found entity 1: altera_pfl2_cfg_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_glitch.v Info (12023): Found entity 1: altera_pfl2_glitch File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_glitch.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_reset.v Info (12023): Found entity 1: altera_pfl2_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_reset.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_ready_synchronizer.v Info (12023): Found entity 1: altera_pfl2_cfg_ready_synchronizer File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_ready_synchronizer.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Info (12023): Found entity 1: altera_pfl2_qspi_cfg File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Info (12023): Found entity 1: altera_pfl2_up_converter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Info (12023): Found entity 1: altera_pfl2_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Info (12023): Found entity 1: altera_pfl2_qspi_cfg_micron_altera File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_timing_adapter.v Info (12023): Found entity 1: altera_pfl2_timing_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_timing_adapter.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter.sv Info (12023): Found entity 1: pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter.sv Line: 60 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_data_format_adapter.v Info (12023): Found entity 1: altera_pfl2_data_format_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_data_format_adapter.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter.sv Info (12023): Found entity 1: pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid.v Info (12023): Found entity 1: unique_chipid File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid.v Line: 8 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Info (12023): Found entity 1: altchip_id File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 36 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/svid_i2c_master.v Info (12023): Found entity 1: svid_i2c_master File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/svid_i2c_master.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Info (12023): Found entity 1: altera_avalon_i2c File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Info (12023): Found entity 1: altera_avalon_i2c_csr File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_clk_cnt.v Info (12023): Found entity 1: altera_avalon_i2c_clk_cnt File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_clk_cnt.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_condt_det.v Info (12023): Found entity 1: altera_avalon_i2c_condt_det File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_condt_det.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_condt_gen.v Info (12023): Found entity 1: altera_avalon_i2c_condt_gen File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_condt_gen.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Info (12023): Found entity 1: altera_avalon_i2c_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_mstfsm.v Info (12023): Found entity 1: altera_avalon_i2c_mstfsm File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_mstfsm.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_rxshifter.v Info (12023): Found entity 1: altera_avalon_i2c_rxshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_rxshifter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_txshifter.v Info (12023): Found entity 1: altera_avalon_i2c_txshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_txshifter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_spksupp.v Info (12023): Found entity 1: altera_avalon_i2c_spksupp File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_spksupp.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_txout.v Info (12023): Found entity 1: altera_avalon_i2c_txout File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_txout.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Info (12023): Found entity 1: max10_qsys File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_irq_mapper.sv Info (12023): Found entity 1: max10_qsys_irq_mapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_avalon_st_adapter_018 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_avalon_st_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_handshake_clock_crosser File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_clock_crosser.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_std_synchronizer_nocut.v Line: 44 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Info (12023): Found entity 1: altera_merlin_width_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_003.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_mux_003 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_003.sv Line: 51 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103 Info (12023): Found entity 2: altera_merlin_arb_adder File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_002.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_mux_002 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_002.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_mux_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_001.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_018.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux_018 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_018.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_006.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux_006 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_006.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_004.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux_004 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_004.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_rsp_demux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_018.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_mux_018 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_018.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_004.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_mux_004 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_004.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_mux_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_001.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_003.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_demux_003 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_003.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_002.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_demux_002 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_002.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_demux_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_cmd_demux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Info (12023): Found entity 1: altera_merlin_burst_adapter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39 Info (12021): Found 5 design units, including 5 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40 Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55 Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77 Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98 Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_new.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_incr_burst_converter.sv Info (12023): Found entity 1: altera_incr_burst_converter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_incr_burst_converter.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_wrap_burst_converter.sv Info (12023): Found entity 1: altera_wrap_burst_converter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_default_burst_converter.sv Info (12023): Found entity 1: altera_default_burst_converter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_default_burst_converter.sv Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_traffic_limiter.sv Info (12023): Found entity 1: altera_merlin_traffic_limiter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_reorder_memory.sv Info (12023): Found entity 1: altera_merlin_reorder_memory File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28 Info (12023): Found entity 2: memory_pointer_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_024.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_024_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_024.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_024 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_024.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_023.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_023_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_023.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_023 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_023.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_009.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_009_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_009.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_009 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_009.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_007.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_007_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_007.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_007 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_007.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_006.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_006_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_006.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_006 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_006.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_005.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_005_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_005.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_005 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_005.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_004.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_004_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_004.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_004 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_004.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_003.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_003_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_003.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_003 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_003.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_002.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_002_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_002.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_002 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_001_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_001.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_3_router_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_3_router File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_master_agent.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_master_translator.sv Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_2.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_2.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_1.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Info (12023): Found entity 1: max10_qsys_mm_interconnect_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_rsp_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_demux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_rsp_demux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_cmd_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_cmd_demux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_router_001_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_0_router_001 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router.sv Info (12023): Found entity 1: max10_qsys_mm_interconnect_0_router_default_decode File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: max10_qsys_mm_interconnect_0_router File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 5 design units, including 5 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Info (12023): Found entity 1: max10_qsys_uart_console_tx File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 21 Info (12023): Found entity 2: max10_qsys_uart_console_rx_stimulus_source File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 194 Info (12023): Found entity 3: max10_qsys_uart_console_rx File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 288 Info (12023): Found entity 4: max10_qsys_uart_console_regs File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 547 Info (12023): Found entity 5: max10_qsys_uart_console File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 793 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_timer_0.v Info (12023): Found entity 1: max10_qsys_timer_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_timer_0.v Line: 21 Info (12021): Found 14 design units, including 14 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Info (12023): Found entity 1: altera_avalon_packets_to_master_inst_for_spichain_in_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 39 Info (12023): Found entity 2: altera_avalon_packets_to_master_inst_for_spichain_out_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 100 Info (12023): Found entity 3: altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 143 Info (12023): Found entity 4: altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 188 Info (12023): Found entity 5: altera_avalon_st_packets_to_bytes_inst_for_spichain_in_packets_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 233 Info (12023): Found entity 6: altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 308 Info (12023): Found entity 7: channel_adapter_btop_for_spichain_in_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 341 Info (12023): Found entity 8: channel_adapter_btop_for_spichain_out_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 416 Info (12023): Found entity 9: channel_adapter_ptob_for_spichain_in_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 453 Info (12023): Found entity 10: channel_adapter_ptob_for_spichain_out_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 520 Info (12023): Found entity 11: spislave_inst_for_spichain_avalon_streaming_sink_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 559 Info (12023): Found entity 12: spislave_inst_for_spichain_avalon_streaming_source_arbitrator File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 604 Info (12023): Found entity 13: SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 643 Info (12023): Found entity 14: SPISlaveToAvalonMasterBridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 688 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master_inst_for_spichain.v Info (12023): Found entity 1: altera_avalon_packets_to_master_inst_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master_inst_for_spichain.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets_inst_for_spichain.v Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets_inst_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets_inst_for_spichain.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes_inst_for_spichain.v Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes_inst_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes_inst_for_spichain.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_btop_for_spichain.v Info (12023): Found entity 1: channel_adapter_btop_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_btop_for_spichain.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_ptob_for_spichain.v Info (12023): Found entity 1: channel_adapter_ptob_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_ptob_for_spichain.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spislave_inst_for_spichain.v Info (12023): Found entity 1: spislave_inst_for_spichain File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spislave_inst_for_spichain.v Line: 34 Info (12021): Found 7 design units, including 7 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Info (12023): Found entity 1: altera_avalon_packets_to_master File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 22 Info (12023): Found entity 2: packets_to_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 142 Info (12023): Found entity 3: fifo_buffer_single_clock_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 512 Info (12023): Found entity 4: fifo_buffer_scfifo_with_controls File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 573 Info (12023): Found entity 5: fifo_buffer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 627 Info (12023): Found entity 6: fifo_to_packet File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 697 Info (12023): Found entity 7: packets_to_master File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 851 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets.v Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets.v Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes.v Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes.v Line: 19 Info (12021): Found 6 design units, including 6 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Info (12023): Found entity 1: SPIPhy File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 59 Info (12023): Found entity 2: MOSIctl File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 267 Info (12023): Found entity 3: MISOctl File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 482 Info (12023): Found entity 4: spi_phy_internal_altera_avalon_st_idle_remover File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 625 Info (12023): Found entity 5: spi_phy_internal_altera_avalon_st_idle_inserter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 688 Info (12023): Found entity 6: single_output_pipeline_stage File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 751 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Info (12023): Found entity 1: avmms_2_spim_bridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_reboot_ctrl.v Info (12023): Found entity 1: max10_reboot_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_reboot_ctrl.v Line: 2 Info (12021): Found 7 design units, including 7 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Info (12023): Found entity 1: altera_onchip_flash_address_range_check File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 38 Info (12023): Found entity 2: altera_onchip_flash_address_write_protection_check File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 55 Info (12023): Found entity 3: altera_onchip_flash_s_address_write_protection_check File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 109 Info (12023): Found entity 4: altera_onchip_flash_a_address_write_protection_check File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 147 Info (12023): Found entity 5: altera_onchip_flash_convert_address File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 197 Info (12023): Found entity 6: altera_onchip_flash_convert_sector File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 219 Info (12023): Found entity 7: altera_onchip_flash_counter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_util.v Line: 244 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Info (12023): Found entity 1: altera_onchip_flash File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Info (12023): Found entity 1: altera_onchip_flash_avmm_data_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v Info (12023): Found entity 1: altera_onchip_flash_avmm_csr_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/altera_onchip_flash_block.v Info (12023): Found entity 1: altera_onchip_flash_block File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/altera_onchip_flash_block.v Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash.v Info (12023): Found entity 1: max10_qsys_nios_flash File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_asmiblock.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_asmiblock File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_asmiblock.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Info (12023): Found entity 1: adapter_8_1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Info (12023): Found entity 1: adapter_8_2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Info (12023): Found entity 1: adapter_8_4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer.sv Info (12023): Found entity 1: demultiplexer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_7_channel.sv Info (12023): Found entity 1: demultiplexer_7_channel File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_7_channel.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_9_channels.sv Info (12023): Found entity 1: demultiplexer_9_channels File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_9_channels.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_12_channels.sv Info (12023): Found entity 1: demultiplexer_12_channels File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/demultiplexer_12_channels.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clk_div.sv Info (12023): Found entity 1: clk_div File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clk_div.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clock_devider.sv Info (12023): Found entity 1: clock_devider File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/clock_devider.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_gpio.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_gpio File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_gpio.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Info (12023): Found entity 1: max10_qsys_nios_flash_qspi_inf_inst File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/inf_sc_fifo_ser_data.v Info (12023): Found entity 1: inf_sc_fifo_ser_data File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/inf_sc_fifo_ser_data.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/qspi_inf_mux.v Info (12023): Found entity 1: qspi_inf_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/qspi_inf_mux.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_cmd File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Info (12023): Found entity 1: data_adapter_32_8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Info (12023): Found entity 1: data_adapter_8_32 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_multiplexer.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_multiplexer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_multiplexer.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_merlin_demultiplexer_0.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_merlin_demultiplexer_0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_merlin_demultiplexer_0.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_addr.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_addr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_addr.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_xip_controller.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_xip_controller File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_xip_controller.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avst_fifo.v Info (12023): Found entity 1: avst_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avst_fifo.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_csr.sv Info (12023): Found entity 1: intel_generic_serial_flash_interface_csr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_csr.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_resp_ram.v Info (12023): Found entity 1: max10_qsys_mctp_smbus_resp_ram File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_resp_ram.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Info (12023): Found entity 1: max10_qsys_mctp_smbus_req_ram File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Info (12023): Found entity 1: mctp_pcievdm_buffer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios.v Info (12023): Found entity 1: max10_qsys_max10_nios File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_test_bench.v Info (12023): Found entity 1: max10_qsys_max10_nios_cpu_test_bench File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_test_bench.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Info (12023): Found entity 1: max10_qsys_max10_nios_cpu_mult_cell File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Line: 21 Info (12021): Found 9 design units, including 9 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Info (12023): Found entity 1: max10_qsys_max10_nios_cpu_ic_data_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 21 Info (12023): Found entity 2: max10_qsys_max10_nios_cpu_ic_tag_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 89 Info (12023): Found entity 3: max10_qsys_max10_nios_cpu_bht_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 158 Info (12023): Found entity 4: max10_qsys_max10_nios_cpu_register_bank_a_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 227 Info (12023): Found entity 5: max10_qsys_max10_nios_cpu_register_bank_b_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 293 Info (12023): Found entity 6: max10_qsys_max10_nios_cpu_dc_tag_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 359 Info (12023): Found entity 7: max10_qsys_max10_nios_cpu_dc_data_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 425 Info (12023): Found entity 8: max10_qsys_max10_nios_cpu_dc_victim_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 494 Info (12023): Found entity 9: max10_qsys_max10_nios_cpu File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 562 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv Info (12023): Found entity 1: altera_nios2_gen2_rtl_module File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_nios2_gen2_rtl_module.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_mm_bridge.v Info (12023): Found entity 1: altera_avalon_mm_bridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_mm_bridge.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_irq_bridge.v Info (12023): Found entity 1: altera_irq_bridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_irq_bridge.v Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Info (12023): Found entity 1: altera_i2cslave_to_avlmm_bridge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_avl_mst_intf_gen.v Info (12023): Found entity 1: altr_i2c_avl_mst_intf_gen File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_avl_mst_intf_gen.v Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_clk_cnt.v Info (12023): Found entity 1: altr_i2c_clk_cnt File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_clk_cnt.v Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_condt_det.v Info (12023): Found entity 1: altr_i2c_condt_det File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_condt_det.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_databuffer.v Info (12023): Found entity 1: altr_i2c_databuffer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_databuffer.v Line: 20 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_rxshifter.v Info (12023): Found entity 1: altr_i2c_rxshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_rxshifter.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_slvfsm.v Info (12023): Found entity 1: altr_i2c_slvfsm File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_slvfsm.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_spksupp.v Info (12023): Found entity 1: altr_i2c_spksupp File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_spksupp.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_txout.v Info (12023): Found entity 1: altr_i2c_txout File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_txout.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_txshifter.v Info (12023): Found entity 1: altr_i2c_txshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_txshifter.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Info (12023): Found entity 1: altera_avalon_i2c File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_csr.v Info (12023): Found entity 1: altera_avalon_i2c_csr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_csr.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_clk_cnt.v Info (12023): Found entity 1: altera_avalon_i2c_clk_cnt File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_clk_cnt.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_condt_det.v Info (12023): Found entity 1: altera_avalon_i2c_condt_det File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_condt_det.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_condt_gen.v Info (12023): Found entity 1: altera_avalon_i2c_condt_gen File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_condt_gen.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Info (12023): Found entity 1: altera_avalon_i2c_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_mstfsm.v Info (12023): Found entity 1: altera_avalon_i2c_mstfsm File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_mstfsm.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_rxshifter.v Info (12023): Found entity 1: altera_avalon_i2c_rxshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_rxshifter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_txshifter.v Info (12023): Found entity 1: altera_avalon_i2c_txshifter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_txshifter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_spksupp.v Info (12023): Found entity 1: altera_avalon_i2c_spksupp File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_spksupp.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_txout.v Info (12023): Found entity 1: altera_avalon_i2c_txout File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_txout.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Info (12023): Found entity 1: hyperram_ctrlr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Info (12023): Found entity 1: hyperram_io_pads File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Info (12023): Found entity 1: altgpio_one_bit File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 16 Info (12023): Found entity 2: altera_gpio_lite File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 940 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Info (12023): Found entity 1: max10_qsys_fpga_flash File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Info (12023): Found entity 1: max10_qsys_fpga_flash_qspi_inf_inst File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_dual_boot.v Info (12023): Found entity 1: altera_dual_boot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_dual_boot.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Info (12023): Found entity 1: alt_dual_boot_avmm File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Info (12023): Found entity 1: alt_dual_boot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top_wrapper.sv Info (12023): Found entity 1: crypto_top_wrapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top_wrapper.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Info (12023): Found entity 1: crypto_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Info (12023): Found entity 1: crypto_mem2_be File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Info (12023): Found entity 1: crypto_mem3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Info (12023): Found entity 1: crypto_mem4_be File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/csl_add_sub_393.v Info (12023): Found entity 1: csl_add_sub_393 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/csl_add_sub_393.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Info (12023): Found entity 1: ecdsa384_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Info (12023): Found entity 1: mult_384x9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Info (12023): Found entity 1: multr_all_384x384 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ocs_ecp384_ad_jpc.v Info (12023): Found entity 1: ocs_ecp384_ad_jpc File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ocs_ecp384_ad_jpc.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ch.v Info (12023): Found entity 1: ch File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ch.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/csa_64.v Info (12023): Found entity 1: csa_64 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/csa_64.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hin_init.v Info (12023): Found entity 1: hin_init File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hin_init.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/kt.v Info (12023): Found entity 1: kt File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/kt.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/maj.v Info (12023): Found entity 1: maj File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/maj.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Info (12023): Found entity 1: sha_round File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round_top.v Info (12023): Found entity 1: sha_round_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round_top.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler.v Info (12023): Found entity 1: sha_scheduler File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler_top.v Info (12023): Found entity 1: sha_scheduler_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler_top.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Info (12023): Found entity 1: sha_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_unit.v Info (12023): Found entity 1: sha_unit File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_unit.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sigma0.v Info (12023): Found entity 1: Sigma0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sigma0.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sigma1.v Info (12023): Found entity 1: Sigma1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sigma1.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Info (12023): Found entity 1: entropy_source File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Info (12023): Found entity 1: max10_trng_entropy File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Info (12023): Found entity 1: max10_trng_entropy_adjust File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Info (12023): Found entity 1: max10_trng_entropy_health File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Info (12023): Found entity 1: max10_trng_entropy_race File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Info (12023): Found entity 1: bmc_dma File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Info (12023): Found entity 1: max10_qsys_adc File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_response_merge.v Info (12023): Found entity 1: altera_modular_adc_response_merge File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_response_merge.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_dual_sync.v Info (12023): Found entity 1: altera_modular_adc_dual_sync File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_dual_sync.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_conduit_splitter.v Info (12023): Found entity 1: altera_modular_adc_conduit_splitter File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_conduit_splitter.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store.v Info (12023): Found entity 1: altera_modular_adc_sample_store File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Info (12023): Found entity 1: altera_modular_adc_sample_store_ram File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Line: 53 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer.v Info (12023): Found entity 1: altera_modular_adc_sequencer File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer_csr.v Info (12023): Found entity 1: altera_modular_adc_sequencer_csr File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer_csr.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer_ctrl.v Info (12023): Found entity 1: altera_modular_adc_sequencer_ctrl File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer_ctrl.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Info (12023): Found entity 1: altera_modular_adc_control File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Info (12023): Found entity 1: altera_modular_adc_control_avrg_fifo File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Line: 53 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Info (12023): Found entity 1: altera_modular_adc_control_fsm File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/chsel_code_converter_sw_to_hw.v Info (12023): Found entity 1: chsel_code_converter_sw_to_hw File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/chsel_code_converter_sw_to_hw.v Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_primitive_wrapper.v Info (12023): Found entity 1: fiftyfivenm_adcblock_primitive_wrapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_primitive_wrapper.v Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Info (12023): Found entity 1: fiftyfivenm_adcblock_top_wrapper File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Info (12023): Found entity 1: top_misc_interconnect File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 36 Info (12021): Found 1 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Info (12023): Found entity 1: acadp_bmc_max10_top File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 23 Info (12021): Found 1 design units, including 0 entities, in source file /home/admin/otc/ofs-bmc/scripts/revision.vhd Info (12022): Found design unit 1: rev_pkg File: /home/admin/otc/ofs-bmc/scripts/revision.vhd Line: 8 Info (12021): Found 2 design units, including 1 entities, in source file /home/admin/otc/ofs-bmc/scripts/rev_wrap_retail.vhd Info (12022): Found design unit 1: rev_wrap-wrapper File: /home/admin/otc/ofs-bmc/scripts/rev_wrap_retail.vhd Line: 9 Info (12023): Found entity 1: rev_wrap File: /home/admin/otc/ofs-bmc/scripts/rev_wrap_retail.vhd Line: 5 Warning (10037): Verilog HDL or VHDL warning at SPISlaveToAvalonMasterBridge.v(665): conditional expression evaluates to a constant File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 665 Warning (10037): Verilog HDL or VHDL warning at SPISlaveToAvalonMasterBridge.v(674): conditional expression evaluates to a constant File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 674 Info (12127): Elaborating entity "acadp_bmc_max10_top" for the top level hierarchy Info (12128): Elaborating entity "pwr_seq_brd_if" for hierarchy "pwr_seq_brd_if:pwr_seq_pins" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 237 Info (12128): Elaborating entity "csr_io_if" for hierarchy "csr_io_if:avmm_slave_nios" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 339 Info (12128): Elaborating entity "csr_fconfig_if" for hierarchy "csr_fconfig_if:csr_fconfig" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 342 Info (12128): Elaborating entity "csr_pwr_seq_if" for hierarchy "csr_pwr_seq_if:csr_pwr_seq" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 343 Info (12128): Elaborating entity "csr_flash_mux_if" for hierarchy "csr_flash_mux_if:csr_flash_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 344 Info (12128): Elaborating entity "csr_svid_if" for hierarchy "csr_svid_if:csr_svid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 345 Info (12128): Elaborating entity "csr_mctp_smb_if" for hierarchy "csr_mctp_smb_if:csr_mctp_smb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 346 Info (12128): Elaborating entity "csr_misc_if" for hierarchy "csr_misc_if:csr_misc" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 347 Info (12128): Elaborating entity "csr_jtg_ctrl_if" for hierarchy "csr_jtg_ctrl_if:csr_jtag" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 348 Info (12128): Elaborating entity "jtag_ctrl_io_if" for hierarchy "jtag_ctrl_io_if:avmm_slave_jtag_nios" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 349 Info (12128): Elaborating entity "clk_rst_top" for hierarchy "clk_rst_top:clk_rst_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 412 Info (12128): Elaborating entity "system_pll" for hierarchy "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll" File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 94 Info (12128): Elaborating entity "altpll" for hierarchy "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Line: 120 Info (12130): Elaborated megafunction instantiation "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Line: 120 Info (12133): Instantiated megafunction "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/system_pll/system_pll.v Line: 120 Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "2" Info (12134): Parameter "clk0_duty_cycle" = "50" Info (12134): Parameter "clk0_multiply_by" = "1" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "clk1_divide_by" = "4" Info (12134): Parameter "clk1_duty_cycle" = "50" Info (12134): Parameter "clk1_multiply_by" = "1" Info (12134): Parameter "clk1_phase_shift" = "0" Info (12134): Parameter "clk2_divide_by" = "1" Info (12134): Parameter "clk2_duty_cycle" = "50" Info (12134): Parameter "clk2_multiply_by" = "1" Info (12134): Parameter "clk2_phase_shift" = "0" Info (12134): Parameter "clk3_divide_by" = "1" Info (12134): Parameter "clk3_duty_cycle" = "50" Info (12134): Parameter "clk3_multiply_by" = "1" Info (12134): Parameter "clk3_phase_shift" = "3333" Info (12134): Parameter "clk4_divide_by" = "10" Info (12134): Parameter "clk4_duty_cycle" = "50" Info (12134): Parameter "clk4_multiply_by" = "1" Info (12134): Parameter "clk4_phase_shift" = "0" Info (12134): Parameter "compensate_clock" = "CLK0" Info (12134): Parameter "inclk0_input_frequency" = "10000" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=system_pll" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NORMAL" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" Info (12134): Parameter "port_areset" = "PORT_USED" Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" Info (12134): Parameter "port_fbin" = "PORT_UNUSED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" Info (12134): Parameter "port_locked" = "PORT_USED" Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" Info (12134): Parameter "port_pllena" = "PORT_UNUSED" Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" Info (12134): Parameter "port_scandata" = "PORT_UNUSED" Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" Info (12134): Parameter "port_scandone" = "PORT_UNUSED" Info (12134): Parameter "port_scanread" = "PORT_UNUSED" Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_USED" Info (12134): Parameter "port_clk2" = "PORT_USED" Info (12134): Parameter "port_clk3" = "PORT_USED" Info (12134): Parameter "port_clk4" = "PORT_USED" Info (12134): Parameter "port_clk5" = "PORT_UNUSED" Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" Info (12134): Parameter "self_reset_on_loss_lock" = "OFF" Info (12134): Parameter "width_clock" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/system_pll_altpll.v Info (12023): Found entity 1: system_pll_altpll File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 31 Info (12128): Elaborating entity "system_pll_altpll" for hierarchy "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altpll.tdf Line: 898 Info (12128): Elaborating entity "csr_top" for hierarchy "csr_top:csr_top_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 448 Warning (10858): Verilog HDL warning at csr_top.sv(245): object general_purpose_debug_reg_int used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 245 Warning (10230): Verilog HDL assignment warning at csr_top.sv(1097): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 1097 Warning (10030): Net "general_purpose_debug_reg_int" at csr_top.sv(245) has no driver or initial value, using a default initial value '0' File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 245 Info (12128): Elaborating entity "rev_wrap" for hierarchy "csr_top:csr_top_inst|rev_wrap:revision_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 127 Info (12128): Elaborating entity "csr_ram" for hierarchy "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 524 Info (12128): Elaborating entity "altsyncram" for hierarchy "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Line: 91 Info (12130): Elaborated megafunction instantiation "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Line: 91 Info (12133): Instantiated megafunction "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_ram.sv Line: 91 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "M9K" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_gir1.tdf Info (12023): Found entity 1: altsyncram_gir1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_gir1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_gir1" for hierarchy "csr_top:csr_top_inst|csr_ram:csr_ram_0x400_host_sw_rd|altsyncram:altsyncram_component|altsyncram_gir1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "unique_chipid" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/csr/csr_top.sv Line: 784 Info (12128): Elaborating entity "altchip_id" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid.v Line: 24 Info (12128): Elaborating entity "a_graycounter" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|a_graycounter:gen_cntr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 99 Info (12130): Elaborated megafunction instantiation "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|a_graycounter:gen_cntr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 99 Info (12133): Instantiated megafunction "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|a_graycounter:gen_cntr" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 99 Info (12134): Parameter "width" = "7" Info (12134): Parameter "lpm_type" = "a_graycounter" Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_3ag.tdf Info (12023): Found entity 1: a_graycounter_3ag File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_graycounter_3ag.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_3ag" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|a_graycounter:gen_cntr|a_graycounter_3ag:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_graycounter.tdf Line: 51 Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|lpm_shiftreg:shift_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 194 Info (12130): Elaborated megafunction instantiation "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|lpm_shiftreg:shift_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 194 Info (12133): Instantiated megafunction "csr_top:csr_top_inst|unique_chipid:uchipid|altchip_id:unique_chipid_inst|lpm_shiftreg:shift_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/unique_chipid/unique_chipid/altchip_id.v Line: 194 Info (12134): Parameter "lpm_direction" = "RIGHT" Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "64" Info (12128): Elaborating entity "jtag_cntrlr" for hierarchy "jtag_cntrlr:jtag_cntrlr_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 465 Warning (10036): Verilog HDL or VHDL warning at jtag_cntrlr.sv(123): object "fpga_jtag_tck_rise_edge_det" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 123 Warning (10763): Verilog HDL warning at jtag_cntrlr.sv(219): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 219 Warning (10958): SystemVerilog warning at jtag_cntrlr.sv(219): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 219 Info (12128): Elaborating entity "ram_sdp" for hierarchy "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/jtag_cntrlr.sv Line: 426 Info (12128): Elaborating entity "altsyncram" for hierarchy "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Line: 89 Info (12130): Elaborated megafunction instantiation "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Line: 89 Info (12133): Instantiated megafunction "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/jtag_ctrlr/ram_sdp.v Line: 89 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "M9K" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bpo1.tdf Info (12023): Found entity 1: altsyncram_bpo1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_bpo1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_bpo1" for hierarchy "jtag_cntrlr:jtag_cntrlr_inst|ram_sdp:comnd_ram|altsyncram:altsyncram_component|altsyncram_bpo1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "flow_control_top" for hierarchy "flow_control_top:flow_ctrl_top_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 525 Info (12128): Elaborating entity "power_sequencer" for hierarchy "flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Line: 125 Warning (10036): Verilog HDL or VHDL warning at power_sequencer.sv(206): object "pwr_dwn_timeout_fpga" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 206 Warning (10763): Verilog HDL warning at power_sequencer.sv(484): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 484 Warning (10958): SystemVerilog warning at power_sequencer.sv(484): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 484 Warning (10763): Verilog HDL warning at power_sequencer.sv(620): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 620 Warning (10958): SystemVerilog warning at power_sequencer.sv(620): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 620 Info (10264): Verilog HDL Case Statement information at power_sequencer.sv(902): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 902 Info (10264): Verilog HDL Case Statement information at power_sequencer.sv(1121): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 1121 Info (12128): Elaborating entity "fpga_config_ctrl" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Line: 171 Warning (10763): Verilog HDL warning at fpga_config_ctrl.sv(382): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 382 Warning (10958): SystemVerilog warning at fpga_config_ctrl.sv(382): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 382 Warning (10763): Verilog HDL warning at fpga_config_ctrl.sv(790): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 790 Warning (10958): SystemVerilog warning at fpga_config_ctrl.sv(790): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 790 Info (12128): Elaborating entity "bmc_sync" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|bmc_sync:sync_nconfig" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 236 Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|bmc_sync:sync_nconfig|altera_std_synchronizer_nocut:sync_loop[0].sync_nocut" File: /home/admin/otc/ofs-bmc/rtl/max10/design/common/bmc_sync.sv Line: 55 Info (12128): Elaborating entity "bmc_sync" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|bmc_sync:sync_pcie_los" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 247 Info (12128): Elaborating entity "debouncer" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|debouncer:nstatus_dbnc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 258 Info (12128): Elaborating entity "debouncer" for hierarchy "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|debouncer:conf_done_dbnc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/fpga_config_ctrl.sv Line: 269 Info (12128): Elaborating entity "pfl_ii" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/flow_control/flow_control_top.sv Line: 211 Info (12128): Elaborating entity "altera_parallel_flash_loader_2" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/pfl_ii.v Line: 78 Info (12128): Elaborating entity "altera_pfl2_qspi_cfg" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Line: 238 Info (12128): Elaborating entity "altera_pfl2_reset" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_reset:altera_pfl2_reset" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 172 Info (12128): Elaborating entity "altera_pfl2_qspi_cfg_micron_altera" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 211 Info (10264): Verilog HDL Case Statement information at altera_pfl2_qspi_cfg_micron_altera.v(626): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 626 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:tcounter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 317 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:tcounter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 317 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:tcounter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 317 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_direction" = "UP" Info (12134): Parameter "lpm_width" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_o6j.tdf Info (12023): Found entity 1: cntr_o6j File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_o6j.tdf Line: 26 Info (12128): Elaborating entity "cntr_o6j" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:tcounter|cntr_o6j:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:io_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 445 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:io_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 445 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:io_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 445 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "16" Info (12134): Parameter "lpm_direction" = "LEFT" Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:IO_LOOP[1].io_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 464 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:IO_LOOP[1].io_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 464 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_shiftreg:IO_LOOP[1].io_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 464 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "8" Info (12134): Parameter "lpm_direction" = "LEFT" Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:cfg_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 488 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:cfg_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 488 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:cfg_counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 488 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_direction" = "DOWN" Info (12134): Parameter "lpm_width" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_oui.tdf Info (12023): Found entity 1: cntr_oui File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_oui.tdf Line: 26 Info (12128): Elaborating entity "cntr_oui" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:cfg_counter|cntr_oui:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:addr_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 510 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:addr_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 510 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:addr_counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg_micron_altera.v Line: 510 Info (12134): Parameter "lpm_width" = "29" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_c2h.tdf Info (12023): Found entity 1: cntr_c2h File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_c2h.tdf Line: 26 Info (12128): Elaborating entity "cntr_c2h" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera:altera_pfl2_qspi_cfg_micron_altera|lpm_counter:addr_counter|cntr_c2h:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "altera_pfl2_up_converter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 329 Info (10264): Verilog HDL Case Statement information at altera_pfl2_up_converter.v(148): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 148 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 122 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 122 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|lpm_counter:counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 122 Info (12134): Parameter "lpm_width" = "1" Info (12134): Parameter "lpm_direction" = "UP" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_87i.tdf Info (12023): Found entity 1: cntr_87i File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_87i.tdf Line: 26 Info (12128): Elaborating entity "cntr_87i" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|lpm_counter:counter|cntr_87i:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "altera_pfl2_fifo" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_up_converter.v Line: 138 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:write_pointer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 127 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:write_pointer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 127 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:write_pointer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 127 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_width" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_mle.tdf Info (12023): Found entity 1: cntr_mle File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_mle.tdf Line: 26 Info (12128): Elaborating entity "cntr_mle" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:write_pointer|cntr_mle:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:read_pointer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 139 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:read_pointer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 139 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:read_pointer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 139 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_width" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_rtg.tdf Info (12023): Found entity 1: cntr_rtg File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_rtg.tdf Line: 26 Info (12128): Elaborating entity "cntr_rtg" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:read_pointer|cntr_rtg:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:data_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 178 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:data_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 178 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:data_counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 178 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_width" = "2" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_nle.tdf Info (12023): Found entity 1: cntr_nle File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_nle.tdf Line: 26 Info (12128): Elaborating entity "cntr_nle" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|lpm_counter:data_counter|cntr_nle:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "altera_pfl2_cfg_controller" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 381 Info (10264): Verilog HDL Case Statement information at altera_pfl2_cfg_controller.v(547): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 547 Info (12128): Elaborating entity "lpm_counter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 494 Info (12130): Elaborated megafunction instantiation "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 494 Info (12133): Instantiated megafunction "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|lpm_counter:counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 494 Info (12134): Parameter "lpm_width" = "20" Info (12134): Parameter "lpm_direction" = "DOWN" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_50j.tdf Info (12023): Found entity 1: cntr_50j File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_50j.tdf Line: 26 Info (12128): Elaborating entity "cntr_50j" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|lpm_counter:counter|cntr_50j:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "altera_pfl2_glitch" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|altera_pfl2_glitch:nstatus_sync" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 531 Info (12128): Elaborating entity "altera_pfl2_glitch" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|altera_pfl2_glitch:enable_sync" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 533 Info (12128): Elaborating entity "altera_pfl2_data_format_adapter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_data_format_adapter:data_format_adapter_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 420 Info (12128): Elaborating entity "pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_data_format_adapter:data_format_adapter_0|pfl_ii_parallel_flash_loader_2_0_altera_pfl2_data_format_adapter_altera_pfl2_data_format_adapter:altera_pfl2_data_format_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_data_format_adapter.v Line: 26 Info (12128): Elaborating entity "altera_pfl2_timing_adapter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_timing_adapter:timing_adapter_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 431 Info (12128): Elaborating entity "pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_timing_adapter:timing_adapter_0|pfl_ii_parallel_flash_loader_2_0_altera_pfl2_timing_adapter_altera_pfl2_timing_adapter:altera_pfl2_timing_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_timing_adapter.v Line: 26 Info (12128): Elaborating entity "altera_pfl2_cfg_ready_synchronizer" for hierarchy "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_ready_synchronizer:ready_synchronizer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_qspi_cfg.v Line: 442 Info (12128): Elaborating entity "max10_qsys" for hierarchy "max10_qsys:max10_qsys_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 717 Info (12128): Elaborating entity "max10_qsys_adc" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 408 Info (12128): Elaborating entity "altera_modular_adc_control" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 106 Info (12128): Elaborating entity "altera_modular_adc_control_fsm" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 108 Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_std_synchronizer:u_clk_dft_synchronizer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 156 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_std_synchronizer:u_clk_dft_synchronizer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 156 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_std_synchronizer:u_clk_dft_synchronizer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 156 Info (12134): Parameter "depth" = "2" Info (12128): Elaborating entity "altera_modular_adc_control_avrg_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 955 Info (12128): Elaborating entity "scfifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Line: 91 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Line: 91 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_avrg_fifo.v Line: 91 Info (12134): Parameter "add_ram_output_register" = "OFF" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M9K" Info (12134): Parameter "lpm_numwords" = "64" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "12" Info (12134): Parameter "lpm_widthu" = "6" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_ds61.tdf Info (12023): Found entity 1: scfifo_ds61 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/scfifo_ds61.tdf Line: 25 Info (12128): Elaborating entity "scfifo_ds61" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/scfifo.tdf Line: 300 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_3o41.tdf Info (12023): Found entity 1: a_dpfifo_3o41 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_3o41.tdf Line: 29 Info (12128): Elaborating entity "a_dpfifo_3o41" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/scfifo_ds61.tdf Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_c6e.tdf Info (12023): Found entity 1: a_fefifo_c6e File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_fefifo_c6e.tdf Line: 25 Info (12128): Elaborating entity "a_fefifo_c6e" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|a_fefifo_c6e:fifo_state" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_3o41.tdf Line: 41 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_337.tdf Info (12023): Found entity 1: cntr_337 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_337.tdf Line: 26 Info (12128): Elaborating entity "cntr_337" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|a_fefifo_c6e:fifo_state|cntr_337:count_usedw" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_fefifo_c6e.tdf Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rqn1.tdf Info (12023): Found entity 1: altsyncram_rqn1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_rqn1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_3o41.tdf Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_n2b.tdf Info (12023): Found entity 1: cntr_n2b File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_n2b.tdf Line: 26 Info (12128): Elaborating entity "cntr_n2b" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|cntr_n2b:rd_ptr_count" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_3o41.tdf Line: 43 Info (12128): Elaborating entity "fiftyfivenm_adcblock_top_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 152 Info (12128): Elaborating entity "chsel_code_converter_sw_to_hw" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|chsel_code_converter_sw_to_hw:decoder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 173 Info (12128): Elaborating entity "fiftyfivenm_adcblock_primitive_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 191 Info (12128): Elaborating entity "altera_modular_adc_control" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 155 Info (12128): Elaborating entity "altera_modular_adc_control_fsm" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 108 Info (12128): Elaborating entity "fiftyfivenm_adcblock_top_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.v Line: 152 Info (12128): Elaborating entity "chsel_code_converter_sw_to_hw" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|chsel_code_converter_sw_to_hw:decoder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 173 Info (12128): Elaborating entity "fiftyfivenm_adcblock_primitive_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/fiftyfivenm_adcblock_top_wrapper.v Line: 191 Info (12128): Elaborating entity "altera_modular_adc_sequencer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sequencer:sequencer_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 306 Info (12128): Elaborating entity "altera_modular_adc_sequencer_csr" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sequencer:sequencer_internal|altera_modular_adc_sequencer_csr:u_seq_csr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer.v Line: 214 Info (12128): Elaborating entity "altera_modular_adc_sequencer_ctrl" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sequencer:sequencer_internal|altera_modular_adc_sequencer_ctrl:u_seq_ctrl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sequencer.v Line: 304 Info (12128): Elaborating entity "altera_modular_adc_sample_store" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 325 Info (12128): Elaborating entity "altera_modular_adc_sample_store_ram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store.v Line: 175 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Line: 107 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Line: 107 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_sample_store_ram.v Line: 107 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "64" Info (12134): Parameter "numwords_b" = "64" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "M9K" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "widthad_a" = "6" Info (12134): Parameter "widthad_b" = "6" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r5s1.tdf Info (12023): Found entity 1: altsyncram_r5s1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_r5s1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_r5s1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_sample_store:sample_store_internal|altera_modular_adc_sample_store_ram:u_ss_ram|altsyncram:altsyncram_component|altsyncram_r5s1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_modular_adc_conduit_splitter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_conduit_splitter:conduit_splitter_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 333 Info (12128): Elaborating entity "altera_modular_adc_dual_sync" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_dual_sync:dual_sync_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 342 Info (12128): Elaborating entity "altera_modular_adc_response_merge" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_response_merge:response_merge_internal" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_adc.v Line: 362 Info (12128): Elaborating entity "bmc_dma" for hierarchy "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 437 Warning (10763): Verilog HDL warning at bmc_dma.sv(351): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 351 Warning (10958): SystemVerilog warning at bmc_dma.sv(351): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 351 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|altsyncram:dma_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 646 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|altsyncram:dma_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 646 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|altsyncram:dma_buffer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 646 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "indata_reg_b" = "CLOCK0" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_a" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "width_byteena_b" = "1" Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_k3e2.tdf Info (12023): Found entity 1: altsyncram_k3e2 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_k3e2.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_k3e2" for hierarchy "max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|altsyncram:dma_buffer|altsyncram_k3e2:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "crypto_top_wrapper" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 448 Info (12128): Elaborating entity "crypto_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top_wrapper.sv Line: 56 Info (12128): Elaborating entity "sha_unit" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 176 Info (12128): Elaborating entity "sha_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_unit.v Line: 62 Info (12128): Elaborating entity "kt" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|kt:kt_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 108 Info (12128): Elaborating entity "sha_scheduler_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_scheduler_top:msg_schedule_top" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 120 Info (12128): Elaborating entity "sha_scheduler" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_scheduler_top:msg_schedule_top|sha_scheduler:msg_sch_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler_top.v Line: 57 Info (12128): Elaborating entity "csa_64" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_scheduler_top:msg_schedule_top|sha_scheduler:msg_sch_inst|csa_64:csa0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_scheduler.v Line: 72 Info (12128): Elaborating entity "hin_init" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|hin_init:init_state" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 133 Info (12128): Elaborating entity "sha_round_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_top.v Line: 148 Info (12128): Elaborating entity "sha_round" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round_top.v Line: 61 Info (12128): Elaborating entity "maj" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0|maj:fn_maj" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 71 Info (12128): Elaborating entity "Sigma0" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0|Sigma0:fn_Sigma0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 77 Info (12128): Elaborating entity "ch" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0|ch:fn_ch" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 84 Info (12128): Elaborating entity "Sigma1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|sha_unit:u_sha|sha_top:sha_inst|sha_round_top:sha_inst_top|sha_round:sha_rnd_0|Sigma1:fn_Sigma1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/sha_round.v Line: 90 Info (12128): Elaborating entity "ecdsa384_top" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 357 Info (12128): Elaborating entity "multr_all_384x384" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 127 Info (12128): Elaborating entity "crypto_mem3" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 47 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Line: 89 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Line: 89 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem3.v Line: 89 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "2" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "1" Info (12134): Parameter "widthad_b" = "5" Info (12134): Parameter "width_a" = "128" Info (12134): Parameter "width_b" = "8" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_aom1.tdf Info (12023): Found entity 1: altsyncram_aom1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_aom1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_aom1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|crypto_mem3:i_cm31|altsyncram:altsyncram_component|altsyncram_aom1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "mult_384x9" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mult_384x9:i_m384_9" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 55 Info (12128): Elaborating entity "csl_add_sub_393" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|csl_add_sub_393:i_cs411" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 70 Info (12128): Elaborating entity "ocs_ecp384_ad_jpc" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|ocs_ecp384_ad_jpc:i_jpc" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 148 Info (12128): Elaborating entity "crypto_mem2_be" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 150 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Line: 92 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Line: 92 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem2_be.v Line: 92 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "32" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "5" Info (12134): Parameter "widthad_b" = "5" Info (12134): Parameter "width_a" = "128" Info (12134): Parameter "width_b" = "128" Info (12134): Parameter "width_byteena_a" = "16" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_50p1.tdf Info (12023): Found entity 1: altsyncram_50p1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_50p1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_50p1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem2_be:i_mem213|altsyncram:altsyncram_component|altsyncram_50p1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "crypto_mem4_be" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/ecdsa384_top.v Line: 158 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Line: 92 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413|altsyncram:altsyncram_component" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Line: 92 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413|altsyncram:altsyncram_component" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_mem4_be.v Line: 92 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "2" Info (12134): Parameter "numwords_b" = "2" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "1" Info (12134): Parameter "widthad_b" = "1" Info (12134): Parameter "width_a" = "128" Info (12134): Parameter "width_b" = "128" Info (12134): Parameter "width_byteena_a" = "16" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nso1.tdf Info (12023): Found entity 1: altsyncram_nso1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_nso1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_nso1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|crypto_mem4_be:i_mem413|altsyncram:altsyncram_component|altsyncram_nso1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "entropy_source" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 392 Info (12128): Elaborating entity "max10_trng_entropy" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 74 Info (12128): Elaborating entity "max10_trng_entropy_race" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 138 Info (12128): Elaborating entity "max10_trng_entropy_health" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 154 Info (12128): Elaborating entity "max10_trng_entropy_adjust" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 171 Info (12128): Elaborating entity "max10_trng_entropy_race" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 186 Info (12128): Elaborating entity "max10_trng_entropy_adjust" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 219 Info (12128): Elaborating entity "scfifo" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 116 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 116 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/entropy_source.sv Line: 116 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M9K" Info (12134): Parameter "lpm_numwords" = "256" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "32" Info (12134): Parameter "lpm_widthu" = "8" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "OFF" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_3h41.tdf Info (12023): Found entity 1: scfifo_3h41 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/scfifo_3h41.tdf Line: 25 Info (12128): Elaborating entity "scfifo_3h41" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/scfifo.tdf Line: 300 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_pc21.tdf Info (12023): Found entity 1: a_dpfifo_pc21 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 33 Info (12128): Elaborating entity "a_dpfifo_pc21" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/scfifo_3h41.tdf Line: 38 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_kki1.tdf Info (12023): Found entity 1: altsyncram_kki1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_kki1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_kki1" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|altsyncram_kki1:FIFOram" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 46 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_b78.tdf Info (12023): Found entity 1: cmpr_b78 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cmpr_b78.tdf Line: 23 Info (12128): Elaborating entity "cmpr_b78" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cmpr_b78:almost_full_comparer" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 55 Info (12128): Elaborating entity "cmpr_b78" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cmpr_b78:three_comparison" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 56 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_o2b.tdf Info (12023): Found entity 1: cntr_o2b File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_o2b.tdf Line: 26 Info (12128): Elaborating entity "cntr_o2b" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cntr_o2b:rd_ptr_msb" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_537.tdf Info (12023): Found entity 1: cntr_537 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_537.tdf Line: 26 Info (12128): Elaborating entity "cntr_537" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cntr_537:usedw_counter" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_p2b.tdf Info (12023): Found entity 1: cntr_p2b File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_p2b.tdf Line: 26 Info (12128): Elaborating entity "cntr_p2b" for hierarchy "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|scfifo:entropy_fifo|scfifo_3h41:auto_generated|a_dpfifo_pc21:dpfifo|cntr_p2b:wr_ptr" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_dpfifo_pc21.tdf Line: 59 Info (12128): Elaborating entity "altera_dual_boot" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 462 Info (12128): Elaborating entity "alt_dual_boot_avmm" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_dual_boot.v Line: 50 Info (12128): Elaborating entity "alt_dual_boot" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 143 Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:read_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 286 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:read_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 286 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:read_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 286 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "41" Info (12134): Parameter "lpm_direction" = "RIGHT" Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:write_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 324 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:write_reg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 324 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_shiftreg:write_reg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 324 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "41" Info (12134): Parameter "lpm_direction" = "RIGHT" Info (12128): Elaborating entity "lpm_counter" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 339 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_counter:counter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 339 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_counter:counter" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 339 Info (12134): Parameter "lpm_type" = "LPM_COUNTER" Info (12134): Parameter "lpm_direction" = "UP" Info (12134): Parameter "lpm_width" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_d7i.tdf Info (12023): Found entity 1: cntr_d7i File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_d7i.tdf Line: 26 Info (12128): Elaborating entity "cntr_d7i" for hierarchy "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|lpm_counter:counter|cntr_d7i:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "max10_qsys_fpga_flash" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 492 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_csr" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_csr:csr_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 200 Info (12128): Elaborating entity "max10_qsys_fpga_flash_xip_controller" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_xip_controller:xip_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 238 Info (12128): Elaborating entity "avst_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_xip_controller.sv Line: 641 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avst_fifo.v Line: 73 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_addr" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_addr:xip_addr_adaption" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 263 Info (12128): Elaborating entity "max10_qsys_fpga_flash_merlin_demultiplexer_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_merlin_demultiplexer_0:merlin_demultiplexer_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 286 Info (12128): Elaborating entity "max10_qsys_fpga_flash_multiplexer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_multiplexer:multiplexer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 309 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_multiplexer:multiplexer|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_multiplexer.sv Line: 276 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_multiplexer:multiplexer|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_cmd" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 349 Info (12128): Elaborating entity "data_adapter_32_8" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|data_adapter_32_8:data_adapter_32_8_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 645 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(36): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 36 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(40): object "state_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 40 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(42): object "in_ready_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 42 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(61): object "b_startofpacket_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 61 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(67): object "mem_readdata0" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 67 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(72): object "mem_readdata1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 72 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(77): object "mem_readdata2" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 77 Warning (10858): Verilog HDL warning at data_adapter_32_8.sv(84): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 84 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(85): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 85 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(88): object "out_channel" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 88 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(92): object "out_startofpacket" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 92 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(93): object "out_endofpacket" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 93 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(96): object "out_empty" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 96 Warning (10036): Verilog HDL or VHDL warning at data_adapter_32_8.sv(99): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 99 Warning (10230): Verilog HDL assignment warning at data_adapter_32_8.sv(137): truncated value with size 4 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 137 Warning (10230): Verilog HDL assignment warning at data_adapter_32_8.sv(282): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_32_8.sv Line: 282 Info (12128): Elaborating entity "data_adapter_8_32" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|data_adapter_8_32:data_adapter_8_32_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 664 Warning (10036): Verilog HDL or VHDL warning at data_adapter_8_32.sv(41): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 41 Warning (10858): Verilog HDL warning at data_adapter_8_32.sv(86): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 86 Warning (10036): Verilog HDL or VHDL warning at data_adapter_8_32.sv(87): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 87 Warning (10036): Verilog HDL or VHDL warning at data_adapter_8_32.sv(90): object "out_channel" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 90 Warning (10036): Verilog HDL or VHDL warning at data_adapter_8_32.sv(96): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/data_adapter_8_32.sv Line: 96 Info (12128): Elaborating entity "max10_qsys_fpga_flash_qspi_inf_inst" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 385 Info (10264): Verilog HDL Case Statement information at max10_qsys_fpga_flash_qspi_inf_inst.sv(632): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 632 Info (10264): Verilog HDL Case Statement information at max10_qsys_fpga_flash_qspi_inf_inst.sv(889): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 889 Info (12128): Elaborating entity "demultiplexer_12_channels" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|demultiplexer_12_channels:demultiplexer_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 215 Info (12128): Elaborating entity "adapter_8_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|adapter_8_1:adapter_8_1_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 235 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(48): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 48 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(52): object "state_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 52 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(55): object "in_ready_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 55 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(78): object "b_startofpacket_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 78 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(84): object "mem_readdata0" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 84 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(89): object "mem_readdata1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 89 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(94): object "mem_readdata2" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 94 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(99): object "mem_readdata3" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 99 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(104): object "mem_readdata4" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 104 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(109): object "mem_readdata5" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 109 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(114): object "mem_readdata6" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 114 Warning (10858): Verilog HDL warning at adapter_8_1.sv(120): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 120 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(121): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 121 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(123): object "out_empty" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 123 Warning (10036): Verilog HDL or VHDL warning at adapter_8_1.sv(126): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 126 Warning (10230): Verilog HDL assignment warning at adapter_8_1.sv(176): truncated value with size 8 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 176 Warning (10230): Verilog HDL assignment warning at adapter_8_1.sv(402): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_1.sv Line: 402 Info (12128): Elaborating entity "adapter_8_2" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|adapter_8_2:adapter_8_2_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 252 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(46): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 46 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(50): object "state_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 50 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(52): object "in_ready_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 52 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(75): object "b_startofpacket_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 75 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(81): object "mem_readdata0" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 81 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(86): object "mem_readdata1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 86 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(91): object "mem_readdata2" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 91 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(96): object "mem_readdata3" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 96 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(101): object "mem_readdata4" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 101 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(106): object "mem_readdata5" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 106 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(111): object "mem_readdata6" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 111 Warning (10858): Verilog HDL warning at adapter_8_2.sv(118): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 118 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(119): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 119 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(122): object "out_empty" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 122 Warning (10036): Verilog HDL or VHDL warning at adapter_8_2.sv(125): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 125 Warning (10230): Verilog HDL assignment warning at adapter_8_2.sv(174): truncated value with size 8 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 174 Warning (10230): Verilog HDL assignment warning at adapter_8_2.sv(339): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 339 Warning (10230): Verilog HDL assignment warning at adapter_8_2.sv(408): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_2.sv Line: 408 Info (12128): Elaborating entity "adapter_8_4" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|adapter_8_4:adapter_8_4_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 269 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(43): object "state_read_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 43 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(47): object "state_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 47 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(49): object "in_ready_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 49 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(72): object "b_startofpacket_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 72 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(78): object "mem_readdata0" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 78 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(83): object "mem_readdata1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 83 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(88): object "mem_readdata2" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 88 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(93): object "mem_readdata3" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 93 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(98): object "mem_readdata4" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 98 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(103): object "mem_readdata5" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 103 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(108): object "mem_readdata6" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 108 Warning (10858): Verilog HDL warning at adapter_8_4.sv(115): object state_waitrequest used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 115 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(116): object "state_waitrequest_d1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 116 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(119): object "out_empty" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 119 Warning (10036): Verilog HDL or VHDL warning at adapter_8_4.sv(122): object "out_error" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 122 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(172): truncated value with size 8 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 172 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(313): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 313 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(352): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 352 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(391): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 391 Warning (10230): Verilog HDL assignment warning at adapter_8_4.sv(430): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/adapter_8_4.sv Line: 430 Info (12128): Elaborating entity "qspi_inf_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|qspi_inf_mux:qspi_inf_mux_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 302 Info (12128): Elaborating entity "max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|qspi_inf_mux:qspi_inf_mux_inst|max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux:qspi_inf_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/qspi_inf_mux.v Line: 62 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|qspi_inf_mux:qspi_inf_mux_inst|max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux:qspi_inf_mux|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux.sv Line: 335 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|qspi_inf_mux:qspi_inf_mux_inst|max10_qsys_fpga_flash_qspi_inf_inst_qspi_inf_mux_qspi_inf_mux:qspi_inf_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "inf_sc_fifo_ser_data" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|inf_sc_fifo_ser_data:inf_sc_fifo_ser_data_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 324 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|inf_sc_fifo_ser_data:inf_sc_fifo_ser_data_inst|altera_avalon_sc_fifo:inf_sc_fifo_ser_data" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/inf_sc_fifo_ser_data.v Line: 75 Warning (10858): Verilog HDL warning at altera_avalon_sc_fifo.v(109): object wr_ptr used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 109 Warning (10858): Verilog HDL warning at altera_avalon_sc_fifo.v(116): object incremented_rd_ptr used but never assigned File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 116 Warning (10030): Net "wr_ptr" at altera_avalon_sc_fifo.v(109) has no driver or initial value, using a default initial value '0' File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 109 Warning (10030): Net "incremented_rd_ptr" at altera_avalon_sc_fifo.v(116) has no driver or initial value, using a default initial value '0' File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_sc_fifo.v Line: 116 Info (12128): Elaborating entity "scfifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 396 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 396 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 396 Info (12134): Parameter "add_ram_output_register" = "OFF" Info (12134): Parameter "enable_ecc" = "FALSE" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_numwords" = "8" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "10" Info (12134): Parameter "lpm_widthu" = "3" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "OFF" Info (12134): Parameter "use_eab" = "OFF" Info (12128): Elaborating entity "a_fffifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/scfifo.tdf Line: 279 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/scfifo.tdf Line: 279 Info (12128): Elaborating entity "lpm_ff" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_ff:last_data_node[7]" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 102 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_ff:last_data_node[7]", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 102 Info (12128): Elaborating entity "lpm_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 103 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 103 Info (12021): Found 1 design units, including 1 entities, in source file db/mux_l7c.tdf Info (12023): Found entity 1: mux_l7c File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mux_l7c.tdf Line: 23 Info (12128): Elaborating entity "mux_l7c" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_mux:last_row_data_out_mux|mux_l7c:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_mux.tdf Line: 87 Info (12128): Elaborating entity "lpm_counter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 105 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 105 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ole.tdf Info (12023): Found entity 1: cntr_ole File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cntr_ole.tdf Line: 26 Info (12128): Elaborating entity "cntr_ole" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_ole:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (12128): Elaborating entity "a_fefifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 112 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fffifo.tdf Line: 112 Info (12128): Elaborating entity "lpm_compare" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fefifo.tdf Line: 77 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fefifo.tdf Line: 77 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_upf.tdf Info (12023): Found entity 1: cmpr_upf File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cmpr_upf.tdf Line: 23 Info (12128): Elaborating entity "cmpr_upf" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_empty_compare|cmpr_upf:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_compare.tdf Line: 281 Info (12128): Elaborating entity "lpm_compare" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_full_compare" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fefifo.tdf Line: 82 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|a_fefifo:fifo_state|lpm_compare:is_almost_full_compare", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/a_fefifo.tdf Line: 82 Info (12128): Elaborating entity "clk_div" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|clk_div:clk_div_new_inst_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 497 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash.v Line: 448 Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.v Line: 208 Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.v Line: 220 Info (12128): Elaborating entity "hyperram_ctrlr" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 527 Warning (10036): Verilog HDL or VHDL warning at hyperram_ctrlr.sv(129): object "s0_txn_addr_sync" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 129 Warning (10036): Verilog HDL or VHDL warning at hyperram_ctrlr.sv(171): object "hram_rbuf_rden_r1" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 171 Warning (10763): Verilog HDL warning at hyperram_ctrlr.sv(193): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 193 Warning (10958): SystemVerilog warning at hyperram_ctrlr.sv(193): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 193 Warning (10763): Verilog HDL warning at hyperram_ctrlr.sv(369): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 369 Warning (10958): SystemVerilog warning at hyperram_ctrlr.sv(369): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 369 Warning (10230): Verilog HDL assignment warning at hyperram_ctrlr.sv(447): truncated value with size 32 to match size of target (5) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 447 Warning (10230): Verilog HDL assignment warning at hyperram_ctrlr.sv(455): truncated value with size 32 to match size of target (5) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 455 Warning (10230): Verilog HDL assignment warning at hyperram_ctrlr.sv(570): truncated value with size 32 to match size of target (16) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 570 Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|altera_std_synchronizer_nocut:sync_txn_latch" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 315 Info (12128): Elaborating entity "dcfifo" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 336 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 336 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 336 Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_numwords" = "16" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "dcfifo" Info (12134): Parameter "lpm_width" = "36" Info (12134): Parameter "lpm_widthu" = "4" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "rdsync_delaypipe" = "4" Info (12134): Parameter "read_aclr_synch" = "OFF" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "write_aclr_synch" = "OFF" Info (12134): Parameter "wrsync_delaypipe" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_e9h1.tdf Info (12023): Found entity 1: dcfifo_e9h1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 37 Info (12128): Elaborating entity "dcfifo_e9h1" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/dcfifo.tdf Line: 191 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_fg6.tdf Info (12023): Found entity 1: a_graycounter_fg6 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_graycounter_fg6.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_fg6" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|a_graycounter_fg6:rdptr_g1p" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 48 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_bub.tdf Info (12023): Found entity 1: a_graycounter_bub File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/a_graycounter_bub.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_bub" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|a_graycounter_bub:wrptr_g1p" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 49 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_v241.tdf Info (12023): Found entity 1: altsyncram_v241 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_v241.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_v241" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|altsyncram_v241:fifo_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 50 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_snl.tdf Info (12023): Found entity 1: alt_synch_pipe_snl File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_snl.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_snl" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|alt_synch_pipe_snl:rs_dgwp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_dd9.tdf Info (12023): Found entity 1: dffpipe_dd9 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dffpipe_dd9.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_dd9" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe12" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_snl.tdf Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tnl.tdf Info (12023): Found entity 1: alt_synch_pipe_tnl File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_tnl.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_tnl" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|alt_synch_pipe_tnl:ws_dgrp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ed9.tdf Info (12023): Found entity 1: dffpipe_ed9 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dffpipe_ed9.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_ed9" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_ed9:dffpipe15" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_tnl.tdf Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_1h5.tdf Info (12023): Found entity 1: cmpr_1h5 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/cmpr_1h5.tdf Line: 23 Info (12128): Elaborating entity "cmpr_1h5" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_wrfifo|dcfifo_e9h1:auto_generated|cmpr_1h5:rdempty_eq_comp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_e9h1.tdf Line: 59 Info (12128): Elaborating entity "hyperram_io_pads" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 644 Info (12128): Elaborating entity "altera_gpio_lite" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_dq_ddio_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Line: 108 Info (12128): Elaborating entity "altgpio_one_bit" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_dq_ddio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 1115 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 82 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object "oe_outclocken_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 334 Info (12128): Elaborating entity "altera_gpio_lite" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_rwds_ddio_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Line: 162 Info (12128): Elaborating entity "altgpio_one_bit" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_rwds_ddio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 1115 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 82 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object "oe_outclocken_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 334 Info (12128): Elaborating entity "altera_gpio_lite" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_clk_ddio_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_io_pads.sv Line: 218 Info (12128): Elaborating entity "altgpio_one_bit" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hyperram_io_pads:hyperram_io_pads|altera_gpio_lite:hram_clk_ddio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 1115 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 82 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object "oe_outclocken_wire" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_gpio_lite.sv Line: 334 Info (12128): Elaborating entity "dcfifo" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 708 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 708 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 708 Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_numwords" = "16" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "dcfifo" Info (12134): Parameter "lpm_width" = "32" Info (12134): Parameter "lpm_widthu" = "4" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "rdsync_delaypipe" = "4" Info (12134): Parameter "read_aclr_synch" = "OFF" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "write_aclr_synch" = "OFF" Info (12134): Parameter "wrsync_delaypipe" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_b2i1.tdf Info (12023): Found entity 1: dcfifo_b2i1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_b2i1.tdf Line: 37 Info (12128): Elaborating entity "dcfifo_b2i1" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/dcfifo.tdf Line: 191 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_n241.tdf Info (12023): Found entity 1: altsyncram_n241 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_n241.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_n241" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|altsyncram_n241:fifo_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_b2i1.tdf Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_unl.tdf Info (12023): Found entity 1: alt_synch_pipe_unl File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_unl.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_unl" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|alt_synch_pipe_unl:rs_dgwp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_b2i1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_fd9.tdf Info (12023): Found entity 1: dffpipe_fd9 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dffpipe_fd9.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_fd9" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe6" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_unl.tdf Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_vnl.tdf Info (12023): Found entity 1: alt_synch_pipe_vnl File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_vnl.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_vnl" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|alt_synch_pipe_vnl:ws_dgrp" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dcfifo_b2i1.tdf Line: 59 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf Info (12023): Found entity 1: dffpipe_gd9 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/dffpipe_gd9.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_gd9" for hierarchy "max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|dcfifo:s0_rdfifo|dcfifo_b2i1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe9" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/alt_synch_pipe_vnl.tdf Line: 35 Info (12128): Elaborating entity "altera_avalon_i2c" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 552 Info (12128): Elaborating entity "altera_avalon_i2c_csr" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_csr:u_csr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 207 Info (12128): Elaborating entity "altera_avalon_i2c_mstfsm" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_mstfsm:u_mstfsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 262 Info (12128): Elaborating entity "altera_avalon_i2c_rxshifter" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_rxshifter:u_rxshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 291 Info (12128): Elaborating entity "altera_avalon_i2c_txshifter" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_txshifter:u_txshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 320 Info (12128): Elaborating entity "altera_avalon_i2c_spksupp" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_spksupp:u_spksupp" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 331 Info (12128): Elaborating entity "altera_avalon_i2c_condt_det" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_condt_det:u_condt_det" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 359 Info (12128): Elaborating entity "altera_avalon_i2c_condt_gen" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_condt_gen:u_condt_gen" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 397 Info (12128): Elaborating entity "altera_avalon_i2c_clk_cnt" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_clk_cnt:u_clk_cnt" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 443 Info (12128): Elaborating entity "altera_avalon_i2c_txout" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_txout:u_txout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 466 Info (12128): Elaborating entity "altera_avalon_i2c_fifo" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 491 Info (10264): Verilog HDL Case Statement information at altera_avalon_i2c_fifo.v(129): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "power_up_uninitialized" = "TRUE" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "width_a" = "10" Info (12134): Parameter "width_b" = "10" Info (12134): Parameter "widthad_a" = "6" Info (12134): Parameter "widthad_b" = "6" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "numwords_a" = "64" Info (12134): Parameter "numwords_b" = "64" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_n6b1.tdf Info (12023): Found entity 1: altsyncram_n6b1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_n6b1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_n6b1" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram|altsyncram_n6b1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_avalon_i2c_fifo" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c.v Line: 513 Info (10264): Verilog HDL Case Statement information at altera_avalon_i2c_fifo.v(129): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "power_up_uninitialized" = "TRUE" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "width_a" = "8" Info (12134): Parameter "width_b" = "8" Info (12134): Parameter "widthad_a" = "6" Info (12134): Parameter "widthad_b" = "6" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "numwords_a" = "64" Info (12134): Parameter "numwords_b" = "64" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_54b1.tdf Info (12023): Found entity 1: altsyncram_54b1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_54b1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_54b1" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_i2c:i2c_0|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram|altsyncram_54b1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_i2cslave_to_avlmm_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 599 Warning (10230): Verilog HDL assignment warning at altera_i2cslave_to_avlmm_bridge.v(701): truncated value with size 32 to match size of target (2) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 701 Info (12128): Elaborating entity "altr_i2c_spksupp" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_spksupp:i_altr_i2c_spksupp" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 397 Info (12128): Elaborating entity "altr_i2c_condt_det" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_condt_det:i_altr_i2c_condt_det" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 428 Info (12128): Elaborating entity "altr_i2c_databuffer" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_databuffer:tx_databuffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 444 Warning (10230): Verilog HDL assignment warning at altr_i2c_databuffer.v(48): truncated value with size 32 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altr_i2c_databuffer.v Line: 48 Info (12128): Elaborating entity "altr_i2c_slvfsm" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_slvfsm:i_altr_i2c_slvfsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 507 Info (12128): Elaborating entity "altr_i2c_avl_mst_intf_gen" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_avl_mst_intf_gen:i_altr_i2c_avl_mst_intf_gen" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 538 Info (12128): Elaborating entity "altr_i2c_txshifter" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_txshifter:i_altr_i2c_txshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 594 Info (12128): Elaborating entity "altr_i2c_rxshifter" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_rxshifter:i_altr_i2c_rxshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 659 Info (12128): Elaborating entity "altr_i2c_txout" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_txout:i_altr_i2c_txout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 695 Info (12128): Elaborating entity "altr_i2c_clk_cnt" for hierarchy "max10_qsys:max10_qsys_inst|altera_i2cslave_to_avlmm_bridge:i2c_oob_slave|altr_i2c_clk_cnt:i_altr_i2c_clk_cnt" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_i2cslave_to_avlmm_bridge.v Line: 762 Info (12128): Elaborating entity "altera_irq_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_irq_bridge:irq_bridge" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 639 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_mm_bridge:jtag_ctrlr_bridge" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 673 Info (12128): Elaborating entity "max10_qsys_max10_nios" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 695 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios.v Line: 51 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_test_bench" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_test_bench:the_max10_qsys_max10_nios_cpu_test_bench" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 3075 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_ic_data_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 4077 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 61 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 61 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 61 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "1024" Info (12134): Parameter "numwords_b" = "1024" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "10" Info (12134): Parameter "widthad_b" = "10" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_2uc1.tdf Info (12023): Found entity 1: altsyncram_2uc1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_2uc1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_2uc1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_data_module:max10_qsys_max10_nios_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_2uc1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_ic_tag_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 4143 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 129 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 129 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 129 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "128" Info (12134): Parameter "numwords_b" = "128" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "24" Info (12134): Parameter "width_b" = "24" Info (12134): Parameter "widthad_a" = "7" Info (12134): Parameter "widthad_b" = "7" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1lc1.tdf Info (12023): Found entity 1: altsyncram_1lc1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_1lc1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_1lc1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_ic_tag_module:max10_qsys_max10_nios_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_1lc1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_bht_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 4313 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 198 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 198 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 198 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "2" Info (12134): Parameter "width_b" = "2" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_vhc1.tdf Info (12023): Found entity 1: altsyncram_vhc1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_vhc1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_vhc1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_bht_module:max10_qsys_max10_nios_cpu_bht|altsyncram:the_altsyncram|altsyncram_vhc1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_register_bank_a_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 5254 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 264 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 264 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 264 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "32" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "5" Info (12134): Parameter "widthad_b" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5tb1.tdf Info (12023): Found entity 1: altsyncram_5tb1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_5tb1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_5tb1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_a_module:max10_qsys_max10_nios_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_5tb1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_register_bank_b_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_register_bank_b_module:max10_qsys_max10_nios_cpu_register_bank_b" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 5272 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_mult_cell" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 5689 Info (12128): Elaborating entity "altera_mult_add" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Line: 63 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Line: 63 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu_mult_cell.v Line: 63 Info (12134): Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0" Info (12134): Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0" Info (12134): Parameter "addnsub_multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "dedicated_multiplier_circuitry" = "YES" Info (12134): Parameter "input_register_a0" = "UNREGISTERED" Info (12134): Parameter "input_register_b0" = "UNREGISTERED" Info (12134): Parameter "input_source_a0" = "DATAA" Info (12134): Parameter "input_source_b0" = "DATAB" Info (12134): Parameter "lpm_type" = "altera_mult_add" Info (12134): Parameter "multiplier1_direction" = "ADD" Info (12134): Parameter "multiplier_aclr0" = "ACLR0" Info (12134): Parameter "multiplier_register0" = "CLOCK0" Info (12134): Parameter "number_of_multipliers" = "1" Info (12134): Parameter "output_register" = "UNREGISTERED" Info (12134): Parameter "port_addnsub1" = "PORT_UNUSED" Info (12134): Parameter "port_addnsub3" = "PORT_UNUSED" Info (12134): Parameter "representation_a" = "UNSIGNED" Info (12134): Parameter "representation_b" = "UNSIGNED" Info (12134): Parameter "selected_device_family" = "MAX10" Info (12134): Parameter "signed_pipeline_aclr_a" = "ACLR0" Info (12134): Parameter "signed_pipeline_aclr_b" = "ACLR0" Info (12134): Parameter "signed_pipeline_register_a" = "CLOCK0" Info (12134): Parameter "signed_pipeline_register_b" = "CLOCK0" Info (12134): Parameter "signed_register_a" = "UNREGISTERED" Info (12134): Parameter "signed_register_b" = "UNREGISTERED" Info (12134): Parameter "width_a" = "16" Info (12134): Parameter "width_b" = "16" Info (12134): Parameter "width_result" = "32" Info (12021): Found 1 design units, including 1 entities, in source file db/altera_mult_add_bbo2.v Info (12023): Found entity 1: altera_mult_add_bbo2 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altera_mult_add_bbo2.v Line: 29 Info (12128): Elaborating entity "altera_mult_add_bbo2" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add.tdf Line: 455 Info (12128): Elaborating entity "altera_mult_add_rtl" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altera_mult_add_bbo2.v Line: 117 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altera_mult_add_bbo2.v Line: 117 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altera_mult_add_bbo2.v Line: 117 Info (12134): Parameter "accum_direction" = "ADD" Info (12134): Parameter "accum_sload_aclr" = "NONE" Info (12134): Parameter "accum_sload_latency_aclr" = "NONE" Info (12134): Parameter "accum_sload_latency_clock" = "UNREGISTERED" Info (12134): Parameter "accum_sload_latency_sclr" = "NONE" Info (12134): Parameter "accum_sload_register" = "UNREGISTERED" Info (12134): Parameter "accum_sload_sclr" = "NONE" Info (12134): Parameter "accumulator" = "NO" Info (12134): Parameter "adder1_rounding" = "NO" Info (12134): Parameter "adder3_rounding" = "NO" Info (12134): Parameter "addnsub1_round_aclr" = "NONE" Info (12134): Parameter "addnsub1_round_pipeline_aclr" = "NONE" Info (12134): Parameter "addnsub1_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "addnsub1_round_pipeline_sclr" = "NONE" Info (12134): Parameter "addnsub1_round_register" = "UNREGISTERED" Info (12134): Parameter "addnsub1_round_sclr" = "NONE" Info (12134): Parameter "addnsub3_round_aclr" = "NONE" Info (12134): Parameter "addnsub3_round_pipeline_aclr" = "NONE" Info (12134): Parameter "addnsub3_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "addnsub3_round_pipeline_sclr" = "NONE" Info (12134): Parameter "addnsub3_round_register" = "UNREGISTERED" Info (12134): Parameter "addnsub3_round_sclr" = "NONE" Info (12134): Parameter "addnsub_multiplier_aclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_aclr3" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_aclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_aclr3" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_clock1" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_latency_clock3" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_latency_sclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_sclr3" = "NONE" Info (12134): Parameter "addnsub_multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_register3" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_sclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_sclr3" = "NONE" Info (12134): Parameter "chainout_aclr" = "NONE" Info (12134): Parameter "chainout_adder" = "NO" Info (12134): Parameter "chainout_adder_direction" = "ADD" Info (12134): Parameter "chainout_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_aclr" = "NONE" Info (12134): Parameter "chainout_round_output_aclr" = "NONE" Info (12134): Parameter "chainout_round_output_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_output_sclr" = "NONE" Info (12134): Parameter "chainout_round_pipeline_aclr" = "NONE" Info (12134): Parameter "chainout_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_pipeline_sclr" = "NONE" Info (12134): Parameter "chainout_round_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_sclr" = "NONE" Info (12134): Parameter "chainout_rounding" = "NO" Info (12134): Parameter "chainout_saturate_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_output_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_output_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturate_output_sclr" = "NONE" Info (12134): Parameter "chainout_saturate_pipeline_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturate_pipeline_sclr" = "NONE" Info (12134): Parameter "chainout_saturate_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturate_sclr" = "NONE" Info (12134): Parameter "chainout_saturation" = "NO" Info (12134): Parameter "chainout_sclr" = "NONE" Info (12134): Parameter "coef0_0" = "0" Info (12134): Parameter "coef0_1" = "0" Info (12134): Parameter "coef0_2" = "0" Info (12134): Parameter "coef0_3" = "0" Info (12134): Parameter "coef0_4" = "0" Info (12134): Parameter "coef0_5" = "0" Info (12134): Parameter "coef0_6" = "0" Info (12134): Parameter "coef0_7" = "0" Info (12134): Parameter "coef1_0" = "0" Info (12134): Parameter "coef1_1" = "0" Info (12134): Parameter "coef1_2" = "0" Info (12134): Parameter "coef1_3" = "0" Info (12134): Parameter "coef1_4" = "0" Info (12134): Parameter "coef1_5" = "0" Info (12134): Parameter "coef1_6" = "0" Info (12134): Parameter "coef1_7" = "0" Info (12134): Parameter "coef2_0" = "0" Info (12134): Parameter "coef2_1" = "0" Info (12134): Parameter "coef2_2" = "0" Info (12134): Parameter "coef2_3" = "0" Info (12134): Parameter "coef2_4" = "0" Info (12134): Parameter "coef2_5" = "0" Info (12134): Parameter "coef2_6" = "0" Info (12134): Parameter "coef2_7" = "0" Info (12134): Parameter "coef3_0" = "0" Info (12134): Parameter "coef3_1" = "0" Info (12134): Parameter "coef3_2" = "0" Info (12134): Parameter "coef3_3" = "0" Info (12134): Parameter "coef3_4" = "0" Info (12134): Parameter "coef3_5" = "0" Info (12134): Parameter "coef3_6" = "0" Info (12134): Parameter "coef3_7" = "0" Info (12134): Parameter "coefsel0_aclr" = "NONE" Info (12134): Parameter "coefsel0_latency_aclr" = "NONE" Info (12134): Parameter "coefsel0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel0_latency_sclr" = "NONE" Info (12134): Parameter "coefsel0_register" = "UNREGISTERED" Info (12134): Parameter "coefsel0_sclr" = "NONE" Info (12134): Parameter "coefsel1_aclr" = "NONE" Info (12134): Parameter "coefsel1_latency_aclr" = "NONE" Info (12134): Parameter "coefsel1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel1_latency_sclr" = "NONE" Info (12134): Parameter "coefsel1_register" = "UNREGISTERED" Info (12134): Parameter "coefsel1_sclr" = "NONE" Info (12134): Parameter "coefsel2_aclr" = "NONE" Info (12134): Parameter "coefsel2_latency_aclr" = "NONE" Info (12134): Parameter "coefsel2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel2_latency_sclr" = "NONE" Info (12134): Parameter "coefsel2_register" = "UNREGISTERED" Info (12134): Parameter "coefsel2_sclr" = "NONE" Info (12134): Parameter "coefsel3_aclr" = "NONE" Info (12134): Parameter "coefsel3_latency_aclr" = "NONE" Info (12134): Parameter "coefsel3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel3_latency_sclr" = "NONE" Info (12134): Parameter "coefsel3_register" = "UNREGISTERED" Info (12134): Parameter "coefsel3_sclr" = "NONE" Info (12134): Parameter "dedicated_multiplier_circuitry" = "YES" Info (12134): Parameter "double_accum" = "NO" Info (12134): Parameter "dsp_block_balancing" = "Auto" Info (12134): Parameter "extra_latency" = "0" Info (12134): Parameter "input_a0_latency_aclr" = "NONE" Info (12134): Parameter "input_a0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a0_latency_sclr" = "NONE" Info (12134): Parameter "input_a1_latency_aclr" = "NONE" Info (12134): Parameter "input_a1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a1_latency_sclr" = "NONE" Info (12134): Parameter "input_a2_latency_aclr" = "NONE" Info (12134): Parameter "input_a2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a2_latency_sclr" = "NONE" Info (12134): Parameter "input_a3_latency_aclr" = "NONE" Info (12134): Parameter "input_a3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a3_latency_sclr" = "NONE" Info (12134): Parameter "input_aclr_a0" = "NONE" Info (12134): Parameter "input_aclr_a1" = "NONE" Info (12134): Parameter "input_aclr_a2" = "NONE" Info (12134): Parameter "input_aclr_a3" = "NONE" Info (12134): Parameter "input_aclr_b0" = "NONE" Info (12134): Parameter "input_aclr_b1" = "NONE" Info (12134): Parameter "input_aclr_b2" = "NONE" Info (12134): Parameter "input_aclr_b3" = "NONE" Info (12134): Parameter "input_aclr_c0" = "NONE" Info (12134): Parameter "input_aclr_c1" = "NONE" Info (12134): Parameter "input_aclr_c2" = "NONE" Info (12134): Parameter "input_aclr_c3" = "NONE" Info (12134): Parameter "input_b0_latency_aclr" = "NONE" Info (12134): Parameter "input_b0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b0_latency_sclr" = "NONE" Info (12134): Parameter "input_b1_latency_aclr" = "NONE" Info (12134): Parameter "input_b1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b1_latency_sclr" = "NONE" Info (12134): Parameter "input_b2_latency_aclr" = "NONE" Info (12134): Parameter "input_b2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b2_latency_sclr" = "NONE" Info (12134): Parameter "input_b3_latency_aclr" = "NONE" Info (12134): Parameter "input_b3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b3_latency_sclr" = "NONE" Info (12134): Parameter "input_c0_latency_aclr" = "NONE" Info (12134): Parameter "input_c0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c0_latency_sclr" = "NONE" Info (12134): Parameter "input_c1_latency_aclr" = "NONE" Info (12134): Parameter "input_c1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c1_latency_sclr" = "NONE" Info (12134): Parameter "input_c2_latency_aclr" = "NONE" Info (12134): Parameter "input_c2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c2_latency_sclr" = "NONE" Info (12134): Parameter "input_c3_latency_aclr" = "NONE" Info (12134): Parameter "input_c3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c3_latency_sclr" = "NONE" Info (12134): Parameter "input_register_a0" = "UNREGISTERED" Info (12134): Parameter "input_register_a1" = "UNREGISTERED" Info (12134): Parameter "input_register_a2" = "UNREGISTERED" Info (12134): Parameter "input_register_a3" = "UNREGISTERED" Info (12134): Parameter "input_register_b0" = "UNREGISTERED" Info (12134): Parameter "input_register_b1" = "UNREGISTERED" Info (12134): Parameter "input_register_b2" = "UNREGISTERED" Info (12134): Parameter "input_register_b3" = "UNREGISTERED" Info (12134): Parameter "input_register_c0" = "UNREGISTERED" Info (12134): Parameter "input_register_c1" = "UNREGISTERED" Info (12134): Parameter "input_register_c2" = "UNREGISTERED" Info (12134): Parameter "input_register_c3" = "UNREGISTERED" Info (12134): Parameter "input_sclr_a0" = "NONE" Info (12134): Parameter "input_sclr_a1" = "NONE" Info (12134): Parameter "input_sclr_a2" = "NONE" Info (12134): Parameter "input_sclr_a3" = "NONE" Info (12134): Parameter "input_sclr_b0" = "NONE" Info (12134): Parameter "input_sclr_b1" = "NONE" Info (12134): Parameter "input_sclr_b2" = "NONE" Info (12134): Parameter "input_sclr_b3" = "NONE" Info (12134): Parameter "input_sclr_c0" = "NONE" Info (12134): Parameter "input_sclr_c1" = "NONE" Info (12134): Parameter "input_sclr_c2" = "NONE" Info (12134): Parameter "input_sclr_c3" = "NONE" Info (12134): Parameter "input_source_a0" = "DATAA" Info (12134): Parameter "input_source_a1" = "DATAA" Info (12134): Parameter "input_source_a2" = "DATAA" Info (12134): Parameter "input_source_a3" = "DATAA" Info (12134): Parameter "input_source_b0" = "DATAB" Info (12134): Parameter "input_source_b1" = "DATAB" Info (12134): Parameter "input_source_b2" = "DATAB" Info (12134): Parameter "input_source_b3" = "DATAB" Info (12134): Parameter "latency" = "0" Info (12134): Parameter "loadconst_control_aclr" = "NONE" Info (12134): Parameter "loadconst_control_register" = "UNREGISTERED" Info (12134): Parameter "loadconst_control_sclr" = "NONE" Info (12134): Parameter "loadconst_value" = "64" Info (12134): Parameter "mult01_round_aclr" = "NONE" Info (12134): Parameter "mult01_round_register" = "UNREGISTERED" Info (12134): Parameter "mult01_round_sclr" = "NONE" Info (12134): Parameter "mult01_saturation_aclr" = "ACLR0" Info (12134): Parameter "mult01_saturation_register" = "UNREGISTERED" Info (12134): Parameter "mult01_saturation_sclr" = "ACLR0" Info (12134): Parameter "mult23_round_aclr" = "NONE" Info (12134): Parameter "mult23_round_register" = "UNREGISTERED" Info (12134): Parameter "mult23_round_sclr" = "NONE" Info (12134): Parameter "mult23_saturation_aclr" = "NONE" Info (12134): Parameter "mult23_saturation_register" = "UNREGISTERED" Info (12134): Parameter "mult23_saturation_sclr" = "NONE" Info (12134): Parameter "multiplier01_rounding" = "NO" Info (12134): Parameter "multiplier01_saturation" = "NO" Info (12134): Parameter "multiplier1_direction" = "ADD" Info (12134): Parameter "multiplier23_rounding" = "NO" Info (12134): Parameter "multiplier23_saturation" = "NO" Info (12134): Parameter "multiplier3_direction" = "ADD" Info (12134): Parameter "multiplier_aclr0" = "ACLR0" Info (12134): Parameter "multiplier_aclr1" = "NONE" Info (12134): Parameter "multiplier_aclr2" = "NONE" Info (12134): Parameter "multiplier_aclr3" = "NONE" Info (12134): Parameter "multiplier_register0" = "CLOCK0" Info (12134): Parameter "multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "multiplier_register2" = "UNREGISTERED" Info (12134): Parameter "multiplier_register3" = "UNREGISTERED" Info (12134): Parameter "multiplier_sclr0" = "NONE" Info (12134): Parameter "multiplier_sclr1" = "NONE" Info (12134): Parameter "multiplier_sclr2" = "NONE" Info (12134): Parameter "multiplier_sclr3" = "NONE" Info (12134): Parameter "negate_aclr" = "NONE" Info (12134): Parameter "negate_latency_aclr" = "NONE" Info (12134): Parameter "negate_latency_clock" = "UNREGISTERED" Info (12134): Parameter "negate_latency_sclr" = "NONE" Info (12134): Parameter "negate_register" = "UNREGISTERED" Info (12134): Parameter "negate_sclr" = "NONE" Info (12134): Parameter "number_of_multipliers" = "1" Info (12134): Parameter "output_aclr" = "NONE" Info (12134): Parameter "output_register" = "UNREGISTERED" Info (12134): Parameter "output_round_aclr" = "NONE" Info (12134): Parameter "output_round_pipeline_aclr" = "NONE" Info (12134): Parameter "output_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "output_round_pipeline_sclr" = "NONE" Info (12134): Parameter "output_round_register" = "UNREGISTERED" Info (12134): Parameter "output_round_sclr" = "NONE" Info (12134): Parameter "output_round_type" = "NEAREST_INTEGER" Info (12134): Parameter "output_rounding" = "NO" Info (12134): Parameter "output_saturate_aclr" = "NONE" Info (12134): Parameter "output_saturate_pipeline_aclr" = "NONE" Info (12134): Parameter "output_saturate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "output_saturate_pipeline_sclr" = "NONE" Info (12134): Parameter "output_saturate_register" = "UNREGISTERED" Info (12134): Parameter "output_saturate_sclr" = "NONE" Info (12134): Parameter "output_saturate_type" = "ASYMMETRIC" Info (12134): Parameter "output_saturation" = "NO" Info (12134): Parameter "output_sclr" = "NONE" Info (12134): Parameter "port_addnsub1" = "PORT_UNUSED" Info (12134): Parameter "port_addnsub3" = "PORT_UNUSED" Info (12134): Parameter "port_chainout_sat_is_overflow" = "PORT_UNUSED" Info (12134): Parameter "port_negate" = "PORT_UNUSED" Info (12134): Parameter "port_output_is_overflow" = "PORT_UNUSED" Info (12134): Parameter "port_signa" = "PORT_UNUSED" Info (12134): Parameter "port_signb" = "PORT_UNUSED" Info (12134): Parameter "preadder_direction_0" = "ADD" Info (12134): Parameter "preadder_direction_1" = "ADD" Info (12134): Parameter "preadder_direction_2" = "ADD" Info (12134): Parameter "preadder_direction_3" = "ADD" Info (12134): Parameter "preadder_mode" = "SIMPLE" Info (12134): Parameter "representation_a" = "UNSIGNED" Info (12134): Parameter "representation_b" = "UNSIGNED" Info (12134): Parameter "rotate_aclr" = "NONE" Info (12134): Parameter "rotate_output_aclr" = "NONE" Info (12134): Parameter "rotate_output_register" = "UNREGISTERED" Info (12134): Parameter "rotate_output_sclr" = "NONE" Info (12134): Parameter "rotate_pipeline_aclr" = "NONE" Info (12134): Parameter "rotate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "rotate_pipeline_sclr" = "NONE" Info (12134): Parameter "rotate_register" = "UNREGISTERED" Info (12134): Parameter "rotate_sclr" = "NONE" Info (12134): Parameter "scanouta_aclr" = "NONE" Info (12134): Parameter "scanouta_register" = "UNREGISTERED" Info (12134): Parameter "scanouta_sclr" = "NONE" Info (12134): Parameter "selected_device_family" = "MAX 10" Info (12134): Parameter "shift_mode" = "NO" Info (12134): Parameter "shift_right_aclr" = "NONE" Info (12134): Parameter "shift_right_output_aclr" = "NONE" Info (12134): Parameter "shift_right_output_register" = "UNREGISTERED" Info (12134): Parameter "shift_right_output_sclr" = "NONE" Info (12134): Parameter "shift_right_pipeline_aclr" = "NONE" Info (12134): Parameter "shift_right_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "shift_right_pipeline_sclr" = "NONE" Info (12134): Parameter "shift_right_register" = "UNREGISTERED" Info (12134): Parameter "shift_right_sclr" = "NONE" Info (12134): Parameter "signed_aclr_a" = "NONE" Info (12134): Parameter "signed_aclr_b" = "NONE" Info (12134): Parameter "signed_latency_aclr_a" = "NONE" Info (12134): Parameter "signed_latency_aclr_b" = "NONE" Info (12134): Parameter "signed_latency_clock_a" = "UNREGISTERED" Info (12134): Parameter "signed_latency_clock_b" = "UNREGISTERED" Info (12134): Parameter "signed_latency_sclr_a" = "NONE" Info (12134): Parameter "signed_latency_sclr_b" = "NONE" Info (12134): Parameter "signed_register_a" = "UNREGISTERED" Info (12134): Parameter "signed_register_b" = "UNREGISTERED" Info (12134): Parameter "signed_sclr_a" = "NONE" Info (12134): Parameter "signed_sclr_b" = "NONE" Info (12134): Parameter "systolic_aclr1" = "NONE" Info (12134): Parameter "systolic_aclr3" = "NONE" Info (12134): Parameter "systolic_delay1" = "UNREGISTERED" Info (12134): Parameter "systolic_delay3" = "UNREGISTERED" Info (12134): Parameter "systolic_sclr1" = "NONE" Info (12134): Parameter "systolic_sclr3" = "NONE" Info (12134): Parameter "use_sload_accum_port" = "NO" Info (12134): Parameter "use_subnadd" = "NO" Info (12134): Parameter "width_a" = "16" Info (12134): Parameter "width_b" = "16" Info (12134): Parameter "width_c" = "22" Info (12134): Parameter "width_chainin" = "1" Info (12134): Parameter "width_coef" = "18" Info (12134): Parameter "width_msb" = "17" Info (12134): Parameter "width_result" = "32" Info (12134): Parameter "width_saturate_sign" = "1" Info (12134): Parameter "zero_chainout_output_aclr" = "NONE" Info (12134): Parameter "zero_chainout_output_register" = "UNREGISTERED" Info (12134): Parameter "zero_chainout_output_sclr" = "NONE" Info (12134): Parameter "zero_loopback_aclr" = "NONE" Info (12134): Parameter "zero_loopback_output_aclr" = "NONE" Info (12134): Parameter "zero_loopback_output_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_output_sclr" = "NONE" Info (12134): Parameter "zero_loopback_pipeline_aclr" = "NONE" Info (12134): Parameter "zero_loopback_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_pipeline_sclr" = "NONE" Info (12134): Parameter "zero_loopback_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_sclr" = "NONE" Info (12134): Parameter "lpm_type" = "altera_mult_add_rtl" Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:signa_reg_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 907 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:signa_reg_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 907 Info (12128): Elaborating entity "ama_data_split_reg_ext_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1023 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1023 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_register_function:data_register_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1989 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_register_function:data_register_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1989 Info (12128): Elaborating entity "ama_dynamic_signed_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_dynamic_signed_function:data0_signed_extension_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2145 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_dynamic_signed_function:data0_signed_extension_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2145 Info (12128): Elaborating entity "ama_data_split_reg_ext_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1113 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1113 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_register_function:data_register_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1989 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_register_function:data_register_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1989 Info (12128): Elaborating entity "ama_dynamic_signed_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_dynamic_signed_function:data0_signed_extension_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2145 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_dynamic_signed_function:data0_signed_extension_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2145 Info (12128): Elaborating entity "ama_preadder_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1265 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1265 Info (12128): Elaborating entity "ama_adder_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3264 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3264 Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:first_adder_ext_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2705 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:first_adder_ext_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2705 Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:second_adder_ext_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2738 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:second_adder_ext_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2738 Info (12128): Elaborating entity "ama_multiplier_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1309 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1309 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3060 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3060 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3074 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_1", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 3074 Info (12128): Elaborating entity "ama_adder_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1350 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1350 Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:first_adder_ext_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2705 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:first_adder_ext_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2705 Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:second_adder_ext_block_0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2738 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:second_adder_ext_block_0", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2738 Info (12128): Elaborating entity "ama_register_function" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:output_reg_block" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1490 Info (12131): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:output_reg_block", which is child of megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 1490 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_dc_tag_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 6111 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 396 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 396 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 396 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "128" Info (12134): Parameter "numwords_b" = "128" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "19" Info (12134): Parameter "width_b" = "19" Info (12134): Parameter "widthad_a" = "7" Info (12134): Parameter "widthad_b" = "7" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_v0c1.tdf Info (12023): Found entity 1: altsyncram_v0c1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_v0c1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_v0c1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_tag_module:max10_qsys_max10_nios_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_v0c1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_dc_data_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 6177 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 465 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 465 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 465 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "1024" Info (12134): Parameter "numwords_b" = "1024" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "10" Info (12134): Parameter "widthad_b" = "10" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ote1.tdf Info (12023): Found entity 1: altsyncram_ote1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_ote1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_ote1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_data_module:max10_qsys_max10_nios_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_ote1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_max10_nios_cpu_dc_victim_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 6289 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 534 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 534 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 534 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "8" Info (12134): Parameter "numwords_b" = "8" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "3" Info (12134): Parameter "widthad_b" = "3" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_hec1.tdf Info (12023): Found entity 1: altsyncram_hec1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_hec1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_hec1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_dc_victim_module:max10_qsys_max10_nios_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_hec1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_nios2_gen2_rtl_module" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|altera_nios2_gen2_rtl_module:the_nios2_rtl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_max10_nios_cpu.v Line: 6861 Info (12128): Elaborating entity "mctp_pcievdm_buffer" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 733 Warning (10763): Verilog HDL warning at mctp_pcievdm_buffer.sv(406): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 406 Warning (10958): SystemVerilog warning at mctp_pcievdm_buffer.sv(406): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 406 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:ingress_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 539 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:ingress_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 539 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:ingress_buffer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 539 Info (12134): Parameter "address_aclr_b" = "NONE" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_etm1.tdf Info (12023): Found entity 1: altsyncram_etm1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_etm1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_etm1" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:ingress_buffer|altsyncram_etm1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:egress_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 590 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:egress_buffer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 590 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:egress_buffer" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mctp_pcievdm_buffer.sv Line: 590 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "indata_reg_b" = "CLOCK0" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_aclr_b" = "NONE" Info (12134): Parameter "outdata_reg_a" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "width_byteena_b" = "1" Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_m3e2.tdf Info (12023): Found entity 1: altsyncram_m3e2 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_m3e2.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_m3e2" for hierarchy "max10_qsys:max10_qsys_inst|mctp_pcievdm_buffer:mctp_pcievdm_buffer|altsyncram:egress_buffer|altsyncram_m3e2:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_mm_bridge:mctp_smbus_req_bridge" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 767 Info (12128): Elaborating entity "max10_qsys_mctp_smbus_req_ram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 780 Info (12128): Elaborating entity "altsyncram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Line: 63 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram|altsyncram:the_altsyncram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Line: 63 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram|altsyncram:the_altsyncram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mctp_smbus_req_ram.v Line: 63 Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "1024" Info (12134): Parameter "numwords_a" = "1024" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "DONT_CARE" Info (12134): Parameter "width_a" = "8" Info (12134): Parameter "widthad_a" = "10" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fv91.tdf Info (12023): Found entity 1: altsyncram_fv91 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_fv91.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_fv91" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_req_ram:mctp_smbus_req_ram|altsyncram:the_altsyncram|altsyncram_fv91:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "max10_qsys_mctp_smbus_resp_ram" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mctp_smbus_resp_ram:mctp_smbus_resp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 827 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "max10_qsys:max10_qsys_inst|altera_avalon_mm_bridge:mlb_csr_bridge" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 861 Info (12128): Elaborating entity "max10_qsys_nios_flash" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 888 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_addr" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|intel_generic_serial_flash_interface_addr:xip_addr_adaption" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash.v Line: 260 Info (12128): Elaborating entity "max10_qsys_nios_flash_qspi_inf_inst" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_nios_flash_qspi_inf_inst:qspi_inf_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash.v Line: 379 Info (10264): Verilog HDL Case Statement information at max10_qsys_nios_flash_qspi_inf_inst.sv(629): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Line: 629 Info (10264): Verilog HDL Case Statement information at max10_qsys_nios_flash_qspi_inf_inst.sv(886): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Line: 886 Info (12128): Elaborating entity "intel_generic_serial_flash_interface_gpio" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_nios_flash_qspi_inf_inst:qspi_inf_inst|intel_generic_serial_flash_interface_gpio:dedicated_interface" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_nios_flash_qspi_inf_inst.sv Line: 950 Info (12128): Elaborating entity "altera_onchip_flash" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 953 Info (12128): Elaborating entity "altera_onchip_flash_avmm_csr_controller" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Line: 203 Info (12128): Elaborating entity "altera_onchip_flash_avmm_data_controller" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Line: 282 Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 569 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 569 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 569 Info (12134): Parameter "depth" = "2" Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1182 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1182 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1182 Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG" Info (12134): Parameter "lpm_width" = "32" Info (12134): Parameter "lpm_direction" = "LEFT" Info (12128): Elaborating entity "altera_onchip_flash_address_range_check" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1192 Info (12128): Elaborating entity "altera_onchip_flash_convert_address" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1203 Info (12128): Elaborating entity "altera_onchip_flash_a_address_write_protection_check" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1245 Info (12128): Elaborating entity "altera_onchip_flash_s_address_write_protection_check" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_s_address_write_protection_check:sector_address_write_protection_checker" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1255 Info (12128): Elaborating entity "altera_onchip_flash_convert_sector" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_sector:sector_convertor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1266 Info (12128): Elaborating entity "altera_onchip_flash_block" for hierarchy "max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_block:altera_onchip_flash_block" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.v Line: 327 Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /home/admin/otc/ofs-bmc/rtl/max10/build/max10_onchip_flash.hex -- setting all initial values to 0 Info (12128): Elaborating entity "max10_reboot_ctrl" for hierarchy "max10_qsys:max10_qsys_inst|max10_reboot_ctrl:reboot_ctrl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 976 Info (10264): Verilog HDL Case Statement information at max10_reboot_ctrl.v(253): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_reboot_ctrl.v Line: 253 Info (12128): Elaborating entity "avmms_2_spim_bridge" for hierarchy "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1012 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(223): truncated value with size 32 to match size of target (3) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 223 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(224): truncated value with size 32 to match size of target (16) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 224 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(243): truncated value with size 32 to match size of target (8) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 243 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(244): truncated value with size 32 to match size of target (8) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 244 Warning (10763): Verilog HDL warning at avmms_2_spim_bridge.sv(443): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 443 Warning (10958): SystemVerilog warning at avmms_2_spim_bridge.sv(443): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 443 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(523): truncated value with size 32 to match size of target (11) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 523 Warning (10230): Verilog HDL assignment warning at avmms_2_spim_bridge.sv(528): truncated value with size 32 to match size of target (21) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 528 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_sc_fifo:avst_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 425 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes" for hierarchy "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_st_packets_to_bytes:pkts_to_bytes" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 788 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets" for hierarchy "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_st_bytes_to_packets:bytes_to_pkts" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/avmms_2_spim_bridge.sv Line: 808 Info (12128): Elaborating entity "SPISlaveToAvalonMasterBridge" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1031 Info (12128): Elaborating entity "altera_avalon_packets_to_master_inst_for_spichain_in_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain_in_stream_arbitrator:the_altera_avalon_packets_to_master_inst_for_spichain_in_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 818 Info (12128): Elaborating entity "altera_avalon_packets_to_master_inst_for_spichain_out_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain_out_stream_arbitrator:the_altera_avalon_packets_to_master_inst_for_spichain_out_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 831 Info (12128): Elaborating entity "altera_avalon_packets_to_master_inst_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain:the_altera_avalon_packets_to_master_inst_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 855 Info (12128): Elaborating entity "altera_avalon_packets_to_master" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain:the_altera_avalon_packets_to_master_inst_for_spichain|altera_avalon_packets_to_master:the_altera_avalon_packets_to_master" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master_inst_for_spichain.v Line: 114 Info (12128): Elaborating entity "packets_to_master" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_packets_to_master_inst_for_spichain:the_altera_avalon_packets_to_master_inst_for_spichain|altera_avalon_packets_to_master:the_altera_avalon_packets_to_master|packets_to_master:p2m" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_packets_to_master.v Line: 137 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_arbitrator:the_altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 867 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_arbitrator:the_altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 881 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets_inst_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_bytes_to_packets_inst_for_spichain:the_altera_avalon_st_bytes_to_packets_inst_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 896 Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_bytes_to_packets_inst_for_spichain:the_altera_avalon_st_bytes_to_packets_inst_for_spichain|altera_avalon_st_bytes_to_packets:the_altera_avalon_st_bytes_to_packets" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_bytes_to_packets_inst_for_spichain.v Line: 83 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes_inst_for_spichain_in_packets_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_packets_to_bytes_inst_for_spichain_in_packets_stream_arbitrator:the_altera_avalon_st_packets_to_bytes_inst_for_spichain_in_packets_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 915 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_arbitrator:the_altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 925 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes_inst_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_packets_to_bytes_inst_for_spichain:the_altera_avalon_st_packets_to_bytes_inst_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 940 Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|altera_avalon_st_packets_to_bytes_inst_for_spichain:the_altera_avalon_st_packets_to_bytes_inst_for_spichain|altera_avalon_st_packets_to_bytes:the_altera_avalon_st_packets_to_bytes" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_packets_to_bytes_inst_for_spichain.v Line: 80 Info (12128): Elaborating entity "channel_adapter_btop_for_spichain_in_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_btop_for_spichain_in_arbitrator:the_channel_adapter_btop_for_spichain_in" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 959 Info (12128): Elaborating entity "channel_adapter_btop_for_spichain_out_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_btop_for_spichain_out_arbitrator:the_channel_adapter_btop_for_spichain_out" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 971 Info (12128): Elaborating entity "channel_adapter_btop_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_btop_for_spichain:the_channel_adapter_btop_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 988 Warning (10036): Verilog HDL or VHDL warning at channel_adapter_btop_for_spichain.v(40): object "out_channel" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_btop_for_spichain.v Line: 40 Warning (10230): Verilog HDL assignment warning at channel_adapter_btop_for_spichain.v(52): truncated value with size 8 to match size of target (1) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/channel_adapter_btop_for_spichain.v Line: 52 Info (12128): Elaborating entity "channel_adapter_ptob_for_spichain_in_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_ptob_for_spichain_in_arbitrator:the_channel_adapter_ptob_for_spichain_in" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1005 Info (12128): Elaborating entity "channel_adapter_ptob_for_spichain_out_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_ptob_for_spichain_out_arbitrator:the_channel_adapter_ptob_for_spichain_out" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1018 Info (12128): Elaborating entity "channel_adapter_ptob_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|channel_adapter_ptob_for_spichain:the_channel_adapter_ptob_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1035 Info (12128): Elaborating entity "spislave_inst_for_spichain_avalon_streaming_sink_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain_avalon_streaming_sink_arbitrator:the_spislave_inst_for_spichain_avalon_streaming_sink" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1047 Info (12128): Elaborating entity "spislave_inst_for_spichain_avalon_streaming_source_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain_avalon_streaming_source_arbitrator:the_spislave_inst_for_spichain_avalon_streaming_source" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1058 Info (12128): Elaborating entity "spislave_inst_for_spichain" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1074 Info (12128): Elaborating entity "SPIPhy" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spislave_inst_for_spichain.v Line: 86 Info (12128): Elaborating entity "MOSIctl" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|MOSIctl:SPIPhy_MOSIctl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 137 Info (12128): Elaborating entity "MISOctl" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|MISOctl:SPIPhy_MISOctl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 157 Info (12128): Elaborating entity "spi_phy_internal_altera_avalon_st_idle_remover" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|spi_phy_internal_altera_avalon_st_idle_remover:SPIPhy_altera_avalon_st_idle_remover" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 178 Info (12128): Elaborating entity "single_output_pipeline_stage" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|single_output_pipeline_stage:SPIPhy_single_output_pipeline_stage" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 191 Info (12128): Elaborating entity "spi_phy_internal_altera_avalon_st_idle_inserter" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|spi_phy_internal_altera_avalon_st_idle_inserter:SPIPhy_altera_avalon_st_idle_inserter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 209 Info (12128): Elaborating entity "SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module" for hierarchy "max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module:SPISlaveToAvalonMasterBridge_reset_clk_domain_synch" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 1084 Info (12128): Elaborating entity "max10_qsys_timer_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_timer_0:timer_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1076 Info (12128): Elaborating entity "max10_qsys_uart_console" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1102 Info (12128): Elaborating entity "max10_qsys_uart_console_tx" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console|max10_qsys_uart_console_tx:the_max10_qsys_uart_console_tx" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 867 Info (12128): Elaborating entity "max10_qsys_uart_console_rx" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console|max10_qsys_uart_console_rx:the_max10_qsys_uart_console_rx" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 885 Info (12128): Elaborating entity "max10_qsys_uart_console_rx_stimulus_source" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console|max10_qsys_uart_console_rx:the_max10_qsys_uart_console_rx|max10_qsys_uart_console_rx_stimulus_source:the_max10_qsys_uart_console_rx_stimulus_source" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 366 Info (12128): Elaborating entity "max10_qsys_uart_console_regs" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_uart_console:uart_console|max10_qsys_uart_console_regs:the_max10_qsys_uart_console_regs" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_uart_console.v Line: 916 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1132 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:spi_slave_avalon_master_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 252 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:mctp_pcievdm_buffer_avmm_ingr_slv_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 316 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:mlb_csr_bridge_s0_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 380 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:spi_slave_avalon_master_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 461 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:mctp_pcievdm_buffer_avmm_ingr_slv_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 545 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:mctp_pcievdm_buffer_avmm_ingr_slv_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:mctp_pcievdm_buffer_avmm_ingr_slv_agent_rsp_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 586 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_router" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_router:router" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 727 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_router_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_router:router|max10_qsys_mm_interconnect_0_router_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router.sv Line: 180 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_router_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_router_001:router_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 743 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_router_001_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_router_001:router_001|max10_qsys_mm_interconnect_0_router_001_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_router_001.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:spi_slave_avalon_master_limiter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 809 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_cmd_demux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_cmd_demux:cmd_demux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 832 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_cmd_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_cmd_mux:cmd_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 849 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_rsp_demux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_rsp_demux:rsp_demux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 883 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_rsp_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_rsp_mux:rsp_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 923 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_rsp_mux.sv Line: 310 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_avalon_st_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0.v Line: 952 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_0:mm_interconnect_0|max10_qsys_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|max10_qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_0_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_1:mm_interconnect_1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1153 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:mctp_pcievdm_buffer_avmm_egrs_mstr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_1.v Line: 100 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:spi_master_avmm_dir_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_1.v Line: 164 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_2" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_2:mm_interconnect_2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1173 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:reboot_ctrl_avmm_master_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_2.v Line: 99 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:dual_boot_avalon_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_2.v Line: 163 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1375 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:bmc_dma_avmm_mstr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 1955 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:max10_nios_data_master_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2015 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:max10_nios_instruction_master_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2075 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:mctp_smbus_resp_bridge_m0_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2135 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:nios_flash_avl_mem_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2259 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:fpga_flash_avl_mem_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2323 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:hyper_ram_avmm_s0_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2387 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:onchip_flash_data_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2451 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:nios_flash_avl_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2515 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:crypto_384_avmm_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2643 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:spi_master_avmm_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2707 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:bmc_dma_avmm_nios_slv_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2835 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:onchip_flash_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2899 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:i2c_1_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 2963 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:jtag_ctrlr_bridge_s0_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3155 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:timer_0_s1_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3219 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:uart_console_s1_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3347 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:mctp_smbus_req_ram_s1_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3411 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:adc_sample_store_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3539 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:adc_sequencer_csr_translator" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3603 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:bmc_dma_avmm_mstr_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3684 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:max10_nios_data_master_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3765 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:max10_nios_instruction_master_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3846 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:mctp_smbus_resp_bridge_m0_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 3927 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_agent:mctp_smbus_req_bridge_m0_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4008 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:nios_flash_avl_mem_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4092 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:nios_flash_avl_mem_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:nios_flash_avl_mem_agent_rsp_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4133 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:hyper_ram_avmm_s0_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4342 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:hyper_ram_avmm_s0_agent_rsp_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4383 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:nios_flash_avl_csr_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4592 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:crypto_384_avmm_csr_agent_rdata_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 4924 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:mctp_smbus_req_ram_s1_agent" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6383 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:mctp_smbus_req_ram_s1_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:mctp_smbus_req_ram_s1_agent_rsp_fifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6424 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router:router" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6815 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router:router|max10_qsys_mm_interconnect_3_router_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router.sv Line: 180 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_001:router_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6831 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_001_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_001:router_001|max10_qsys_mm_interconnect_3_router_001_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_001.sv Line: 200 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_002" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_002:router_002" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6847 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_002_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_002:router_002|max10_qsys_mm_interconnect_3_router_002_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_002.sv Line: 181 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_003" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_003:router_003" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6863 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_003_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_003:router_003|max10_qsys_mm_interconnect_3_router_003_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_003.sv Line: 174 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_004" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_004:router_004" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6879 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_004_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_004:router_004|max10_qsys_mm_interconnect_3_router_004_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_004.sv Line: 174 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_005" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_005:router_005" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6895 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_005_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_005:router_005|max10_qsys_mm_interconnect_3_router_005_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_005.sv Line: 178 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_006" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_006:router_006" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6911 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_006_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_006:router_006|max10_qsys_mm_interconnect_3_router_006_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_006.sv Line: 173 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_007" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_007:router_007" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6927 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_007_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_007:router_007|max10_qsys_mm_interconnect_3_router_007_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_007.sv Line: 178 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_009" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_009:router_009" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 6959 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_009_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_009:router_009|max10_qsys_mm_interconnect_3_router_009_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_009.sv Line: 173 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_023" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_023:router_023" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7183 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_023_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_023:router_023|max10_qsys_mm_interconnect_3_router_023_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_023.sv Line: 173 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_024" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_024:router_024" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7199 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_router_024_default_decode" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_router_024:router_024|max10_qsys_mm_interconnect_3_router_024_default_decode:the_default_decode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_router_024.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_traffic_limiter:bmc_dma_avmm_mstr_limiter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7281 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_traffic_limiter:max10_nios_data_master_limiter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7331 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_traffic_limiter:max10_nios_instruction_master_limiter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7381 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7431 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778 Info (12128): Elaborating entity "altera_merlin_burst_adapter_burstwrap_increment" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 979 Info (12128): Elaborating entity "altera_merlin_burst_adapter_min" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 1004 Info (12128): Elaborating entity "altera_merlin_burst_adapter_subtractor" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 157 Info (12128): Elaborating entity "altera_merlin_burst_adapter_adder" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 88 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:fpga_flash_avl_mem_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7481 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:fpga_flash_avl_mem_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:hyper_ram_avmm_s0_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7531 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:hyper_ram_avmm_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_csr_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 7631 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:nios_flash_avl_csr_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:mctp_smbus_req_ram_s1_burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8331 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:mctp_smbus_req_ram_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:mctp_smbus_req_ram_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778 Warning (10230): Verilog HDL assignment warning at altera_merlin_address_alignment.sv(155): truncated value with size 4 to match size of target (2) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv Line: 155 Warning (10230): Verilog HDL assignment warning at altera_merlin_address_alignment.sv(259): truncated value with size 34 to match size of target (32) File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_address_alignment.sv Line: 259 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_demux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_demux:cmd_demux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8504 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_demux_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_demux_001:cmd_demux_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8647 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_demux_002" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_demux_002:cmd_demux_002" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8676 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_demux_003" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_demux_003:cmd_demux_003" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8693 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux:cmd_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8739 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux.sv Line: 301 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_mux_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux_001:cmd_mux_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8762 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_cmd_mux_001.sv Line: 287 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_mux_004" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux_004:cmd_mux_004" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 8825 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_cmd_mux_018" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_cmd_mux_018:cmd_mux_018" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9069 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux:rsp_demux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9155 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux_001:rsp_demux_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9178 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux_004" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux_004:rsp_demux_004" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9241 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux_006" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux_006:rsp_demux_006" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9275 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_demux_018" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_demux_018:rsp_demux_018" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9485 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_mux" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux:rsp_mux" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9565 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_mux_001" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_001:rsp_mux_001" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9708 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_001.sv Line: 630 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_001:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_mux_002" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_002:rsp_mux_002" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9737 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_002:rsp_mux_002|altera_merlin_arbitrator:arb" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_rsp_mux_002.sv Line: 326 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_rsp_mux_003" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_rsp_mux_003:rsp_mux_003" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9754 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_width_adapter:max10_nios_data_master_to_mctp_smbus_req_ram_s1_cmd_width_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9837 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_merlin_width_adapter:mctp_smbus_req_ram_s1_to_max10_nios_data_master_rsp_width_adapter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 9969 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Line: 742 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_merlin_width_adapter.sv Line: 743 Info (12128): Elaborating entity "altera_avalon_st_handshake_clock_crosser" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 10069 Info (12128): Elaborating entity "altera_avalon_st_clock_crosser" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 149 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_avalon_st_adapter_018" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_avalon_st_adapter_018:avalon_st_adapter_018" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3.v Line: 10654 Info (12128): Elaborating entity "max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_mm_interconnect_3:mm_interconnect_3|max10_qsys_mm_interconnect_3_avalon_st_adapter_018:avalon_st_adapter_018|max10_qsys_mm_interconnect_3_avalon_st_adapter_018_error_adapter_0:error_adapter_0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_mm_interconnect_3_avalon_st_adapter_018.v Line: 200 Info (12128): Elaborating entity "max10_qsys_irq_mapper" for hierarchy "max10_qsys:max10_qsys_inst|max10_qsys_irq_mapper:irq_mapper" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/max10_qsys.v Line: 1389 Info (12128): Elaborating entity "fpga_flash_if_ctrl" for hierarchy "fpga_flash_if_ctrl:fpga_flash_if_ctrl_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 811 Info (12128): Elaborating entity "fpga_qspi_filter" for hierarchy "fpga_flash_if_ctrl:fpga_flash_if_ctrl_inst|fpga_qspi_filter:fpga_qspi_filter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_flash_if_ctrl.sv Line: 157 Info (12128): Elaborating entity "bmc_sync" for hierarchy "fpga_flash_if_ctrl:fpga_flash_if_ctrl_inst|bmc_sync:error_sync" File: /home/admin/otc/ofs-bmc/rtl/max10/design/fpga_flash_if_ctrl/fpga_flash_if_ctrl.sv Line: 320 Info (12128): Elaborating entity "mctp_over_smbus" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 857 Info (12128): Elaborating entity "pldm_over_mctp_top_controller" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_over_smbus.sv Line: 263 Info (12128): Elaborating entity "mctp_slow_clk_pulse" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_slow_clk_pulse:slow_clk_pulse_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 472 Info (12128): Elaborating entity "mctp_debouncer" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 491 Info (12128): Elaborating entity "smbus_arp_controller" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 721 Warning (10036): Verilog HDL or VHDL warning at smbus_arp_controller.v(153): object "smbus_scl_cycle_start" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 153 Info (12128): Elaborating entity "smbus_crc" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_crc:crc8_calc_arp_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 2115 Info (12128): Elaborating entity "pldm_over_mctp_req_ctrl" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 804 Warning (10036): Verilog HDL or VHDL warning at pldm_over_mctp_req_ctrl.v(158): object "mm_bridge_req_s0_readdata" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 158 Warning (10036): Verilog HDL or VHDL warning at pldm_over_mctp_req_ctrl.v(159): object "mm_bridge_req_s0_readdatavalid" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 159 Info (12128): Elaborating entity "pldm_over_mctp_resp_ctrl" for hierarchy "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 867 Info (10264): Verilog HDL Case Statement information at pldm_over_mctp_resp_ctrl.v(1327): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 1327 Info (12128): Elaborating entity "svid_controller" for hierarchy "svid_controller:svid_ctrlr_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 883 Warning (10763): Verilog HDL warning at svid_controller.sv(257): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 257 Warning (10958): SystemVerilog warning at svid_controller.sv(257): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 257 Info (12128): Elaborating entity "bmc_sync" for hierarchy "svid_controller:svid_ctrlr_inst|bmc_sync:sdm_pmbus_alert" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 201 Info (12128): Elaborating entity "lpm_mult" for hierarchy "svid_controller:svid_ctrlr_inst|lpm_mult:vout_mult_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 484 Info (12130): Elaborated megafunction instantiation "svid_controller:svid_ctrlr_inst|lpm_mult:vout_mult_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 484 Info (12133): Instantiated megafunction "svid_controller:svid_ctrlr_inst|lpm_mult:vout_mult_inst" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 484 Info (12134): Parameter "lpm_hint" = "INPUT_B_IS_CONSTANT=YES,DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5" Info (12134): Parameter "lpm_pipeline" = "2" Info (12134): Parameter "lpm_representation" = "UNSIGNED" Info (12134): Parameter "lpm_type" = "LPM_MULT" Info (12134): Parameter "lpm_widtha" = "18" Info (12134): Parameter "lpm_widthb" = "18" Info (12134): Parameter "lpm_widthp" = "36" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_2ru.tdf Info (12023): Found entity 1: mult_2ru File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mult_2ru.tdf Line: 29 Info (12128): Elaborating entity "mult_2ru" for hierarchy "svid_controller:svid_ctrlr_inst|lpm_mult:vout_mult_inst|mult_2ru:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_mult.tdf Line: 377 Info (12128): Elaborating entity "svid_i2c_wrapper" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_controller.sv Line: 594 Warning (10763): Verilog HDL warning at svid_i2c_wrapper.sv(107): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Line: 107 Warning (10958): SystemVerilog warning at svid_i2c_wrapper.sv(107): unique or priority keyword makes case statement complete File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Line: 107 Info (12128): Elaborating entity "svid_i2c_master" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/svid_ctlr/svid_i2c_wrapper.sv Line: 277 Info (12128): Elaborating entity "altera_avalon_i2c" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/svid_i2c_master.v Line: 54 Info (12128): Elaborating entity "altera_avalon_i2c_csr" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_csr:u_csr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 212 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(257): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 257 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(258): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 258 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(259): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 259 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(269): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 269 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(270): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 270 Warning (10230): Verilog HDL assignment warning at altera_avalon_i2c_csr.v(271): truncated value with size 32 to match size of target (4) File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_csr.v Line: 271 Info (12128): Elaborating entity "altera_avalon_i2c_mstfsm" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_mstfsm:u_mstfsm" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 267 Info (12128): Elaborating entity "altera_avalon_i2c_rxshifter" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_rxshifter:u_rxshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 296 Info (12128): Elaborating entity "altera_avalon_i2c_txshifter" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_txshifter:u_txshifter" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 325 Info (12128): Elaborating entity "altera_avalon_i2c_spksupp" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_spksupp:u_spksupp" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 336 Info (12128): Elaborating entity "altera_avalon_i2c_condt_det" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_condt_det:u_condt_det" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 364 Info (12128): Elaborating entity "altera_avalon_i2c_condt_gen" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_condt_gen:u_condt_gen" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 402 Info (12128): Elaborating entity "altera_avalon_i2c_clk_cnt" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_clk_cnt:u_clk_cnt" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 448 Info (12128): Elaborating entity "altera_avalon_i2c_txout" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_txout:u_txout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 471 Info (12128): Elaborating entity "altera_avalon_i2c_fifo" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 496 Info (10264): Verilog HDL Case Statement information at altera_avalon_i2c_fifo.v(129): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12130): Elaborated megafunction instantiation "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12133): Instantiated megafunction "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "power_up_uninitialized" = "TRUE" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "width_a" = "10" Info (12134): Parameter "width_b" = "10" Info (12134): Parameter "widthad_a" = "3" Info (12134): Parameter "widthad_b" = "3" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "numwords_a" = "8" Info (12134): Parameter "numwords_b" = "8" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_d3b1.tdf Info (12023): Found entity 1: altsyncram_d3b1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_d3b1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_d3b1" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_txfifo|altsyncram:the_dp_ram|altsyncram_d3b1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_avalon_i2c_fifo" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c.v Line: 518 Info (10264): Verilog HDL Case Statement information at altera_avalon_i2c_fifo.v(129): all case item expressions in this case statement are onehot File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12130): Elaborated megafunction instantiation "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12133): Instantiated megafunction "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/svid_i2c_master/svid_i2c_master/synthesis/submodules/altera_avalon_i2c_fifo.v Line: 99 Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "power_up_uninitialized" = "TRUE" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "width_a" = "8" Info (12134): Parameter "width_b" = "8" Info (12134): Parameter "widthad_a" = "3" Info (12134): Parameter "widthad_b" = "3" Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "numwords_a" = "8" Info (12134): Parameter "numwords_b" = "8" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r0b1.tdf Info (12023): Found entity 1: altsyncram_r0b1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_r0b1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_r0b1" for hierarchy "svid_controller:svid_ctrlr_inst|svid_i2c_wrapper:svid_i2c_wrapper_inst|svid_i2c_master:i2cm|altera_avalon_i2c:i2cm|altera_avalon_i2c_fifo:u_rxfifo|altsyncram:the_dp_ram|altsyncram_r0b1:auto_generated" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "top_misc_interconnect" for hierarchy "top_misc_interconnect:top_misc_inst" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 996 Warning (10036): Verilog HDL or VHDL warning at top_misc_interconnect.sv(172): object "dummy_assign" assigned a value but never read File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 172 Info (12128): Elaborating entity "bmc_sync" for hierarchy "top_misc_interconnect:top_misc_inst|bmc_sync:i2c_sync" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 574 Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following RAM node(s): Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 40 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 70 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 100 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 130 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 160 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 190 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 220 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 250 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 280 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 310 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 340 Warning (14320): Synthesized away node "max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_rqn1.tdf Line: 370 Info (13014): Ignored 8 buffer(s) Info (13016): Ignored 8 CARRY_SUM buffer(s) Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13049): Converted tri-state buffer "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|flash_ncs[0]" feeding internal logic into a wire File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Line: 105 Warning (13049): Converted tri-state buffer "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|flash_sck[0]" feeding internal logic into a wire File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_parallel_flash_loader_2.v Line: 104 Info (276014): Found 1 instances of uninferred RAM logic Info (276004): RAM logic "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_up_converter:altera_pfl2_up_converter|altera_pfl2_fifo:compressed_fifo|data_array" is uninferred due to inappropriate RAM size File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_fifo.v Line: 76 Info (19000): Inferred 3 megafunctions from design logic Info (276029): Inferred altsyncram megafunction from the following design logic: "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_sc_fifo:avst_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 34 Info (286033): Parameter WIDTHAD_A set to 8 Info (286033): Parameter NUMWORDS_A set to 256 Info (286033): Parameter WIDTH_B set to 34 Info (286033): Parameter WIDTHAD_B set to 8 Info (286033): Parameter NUMWORDS_B set to 256 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (276029): Inferred altsyncram megafunction from the following design logic: "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 33 Info (286033): Parameter WIDTHAD_A set to 6 Info (286033): Parameter NUMWORDS_A set to 64 Info (286033): Parameter WIDTH_B set to 33 Info (286033): Parameter WIDTHAD_B set to 6 Info (286033): Parameter NUMWORDS_B set to 64 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (276029): Inferred altsyncram megafunction from the following design logic: "max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 33 Info (286033): Parameter WIDTHAD_A set to 6 Info (286033): Parameter NUMWORDS_A set to 64 Info (286033): Parameter WIDTH_B set to 33 Info (286033): Parameter WIDTHAD_B set to 6 Info (286033): Parameter NUMWORDS_B set to 64 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA Info (278001): Inferred 4 megafunctions from design logic Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p3|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mult_384x9:i_m384_9|Mult0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Line: 21 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_sc_fifo:avst_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|avmms_2_spim_bridge:spi_master|altera_avalon_sc_fifo:avst_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "34" Info (12134): Parameter "WIDTHAD_A" = "8" Info (12134): Parameter "NUMWORDS_A" = "256" Info (12134): Parameter "WIDTH_B" = "34" Info (12134): Parameter "WIDTHAD_B" = "8" Info (12134): Parameter "NUMWORDS_B" = "256" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_uag1.tdf Info (12023): Found entity 1: altsyncram_uag1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_uag1.tdf Line: 28 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_fpga_flash_xip_controller:xip_controller|avst_fifo:avst_fifo_inst|altera_avalon_sc_fifo:avst_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "33" Info (12134): Parameter "WIDTHAD_A" = "6" Info (12134): Parameter "NUMWORDS_A" = "64" Info (12134): Parameter "WIDTH_B" = "33" Info (12134): Parameter "WIDTHAD_B" = "6" Info (12134): Parameter "NUMWORDS_B" = "64" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_i7g1.tdf Info (12023): Found entity 1: altsyncram_i7g1 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/altsyncram_i7g1.tdf Line: 28 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" with the following parameter: File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (12134): Parameter "LPM_WIDTHA" = "17" Info (12134): Parameter "LPM_WIDTHB" = "17" Info (12134): Parameter "LPM_WIDTHP" = "34" Info (12134): Parameter "LPM_WIDTHR" = "34" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_9401.tdf Info (12023): Found entity 1: mult_9401 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mult_9401.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|max10_qsys_max10_nios:max10_nios|max10_qsys_max10_nios_cpu:cpu|max10_qsys_max10_nios_cpu_mult_cell:the_max10_qsys_max10_nios_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_bbo2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" with the following parameter: File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/altera_mult_add_rtl.v Line: 2969 Info (12134): Parameter "LPM_WIDTHA" = "16" Info (12134): Parameter "LPM_WIDTHB" = "16" Info (12134): Parameter "LPM_WIDTHP" = "32" Info (12134): Parameter "LPM_WIDTHR" = "32" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_9b01.tdf Info (12023): Found entity 1: mult_9b01 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mult_9b01.tdf Line: 29 Info (12130): Elaborated megafunction instantiation "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mult_384x9:i_m384_9|lpm_mult:Mult0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Line: 21 Info (12133): Instantiated megafunction "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mult_384x9:i_m384_9|lpm_mult:Mult0" with the following parameter: File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/mult_384x9.v Line: 21 Info (12134): Parameter "LPM_WIDTHA" = "384" Info (12134): Parameter "LPM_WIDTHB" = "8" Info (12134): Parameter "LPM_WIDTHP" = "392" Info (12134): Parameter "LPM_WIDTHR" = "392" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "5" Info (12134): Parameter "DEDICATED_MULTIPLIER_CIRCUITRY" = "YES" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_mu01.tdf Info (12023): Found entity 1: mult_mu01 File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/mult_mu01.tdf Line: 31 Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (13014): Ignored 916 buffer(s) Info (13019): Ignored 916 SOFT buffer(s) Warning (13050): Open-drain buffer(s) that do not directly drive top-level pin(s) are removed Warning (13051): Converted the fanout from the open-drain buffer "flow_control_top:flow_ctrl_top_inst|pfl_ii:pfl_ii_inst|altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_qspi_cfg:altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller:altera_pfl2_cfg_controller|nconfig_opndrn" to the node "flow_control_top:flow_ctrl_top_inst|fpga_config_ctrl:fpga_config_ctrl_inst|bmc_sync:sync_nconfig|altera_std_synchronizer_nocut:sync_loop[0].sync_nocut|din_s1" into a wire File: /home/admin/otc/ofs-bmc/rtl/max10/design/IPs/pfl_ii/pfl_ii/synthesis/submodules/altera_pfl2_cfg_controller.v Line: 543 Warning (13051): Converted the fanout from the open-drain buffer "flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|csr_pwr_seq.debug_pwr_sequencer_sts_2[23]" to the node "csr_top:csr_top_inst|Mux40" into a wire File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 43 Info (13000): Registers with preset signals will power-up high File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_qsys_fpga_flash_qspi_inf_inst.sv Line: 706 Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "hram_ck_n" is stuck at VCC File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 86 Info (286030): Timing-Driven Synthesis is running Info (17049): 1736 registers lost all their fanouts during netlist optimizations. Info (17016): Found the following redundant logic cells in design Info (17048): Logic cell "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_shiftnld" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 358 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_regin" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 293 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_scl_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 240 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_scl_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 242 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 244 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_sda_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 241 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_sda_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 243 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_sda_oe" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 245 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_interrupt_n" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 289 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div4_cnt[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 275 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_scl_clock_cycle_div2_cnt[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 274 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_idle_assert" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 266 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_idle_assert" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 280 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_multi_pkt_msg_flag" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 287 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_multi_pkt" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 321 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_mctp_message_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 338 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_slow_clk_pulse:slow_clk_pulse_inst0|ctr_bit8" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_slow_clk_pulse.v Line: 14 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|scl_in_valid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 238 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_packet_valid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 282 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_multi_pkt_msg_flag_exded" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 288 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_smbus_scl_cycle_cnt[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 271 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_valid_config" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 330 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_valid_received" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 283 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_valid_debug_mode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 329 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|cmd_crc8_gen[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 230 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[127]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|mctp_slave_address[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 164 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_payload_buffer_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 168 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_crc8_gen[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_message_flag_to_expected" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 167 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_headers_debug_mode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 328 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_message_interrupt_clr" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 169 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p0[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 298 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p0[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 294 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_slave_addr[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 302 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_packet_num[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 293 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_multi_pkt_timeout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 310 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_packet_num[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 293 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_state_timeout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 309 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_state_timeout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 267 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_message_receive_ready" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 165 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_packet_num[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 322 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_packet_num[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 322 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_ready" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 320 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|sda_in" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 229 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|scl_in" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 228 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_rd[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_targeted_slave_addr_wr[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[126]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[119]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_req_ctrl:pldm_over_mctp_req_ctrl_inst0|req_message_flag_to_config" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_req_ctrl.v Line: 170 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p2[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 325 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p1[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 324 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p0[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 323 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_payload_num_p3[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 326 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_pld_total_byte_num[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 292 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_current_state[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 339 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p1[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 295 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_fsm_current_state[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 279 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p1[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 299 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_slave_addr[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 303 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p2[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 296 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_des_eid_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 304 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_fsm_current_state[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 265 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_packet_num[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 293 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pkt_smbus_pec_valid" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 308 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p2[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 300 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_fsm_state_timeout" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 341 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_extra_debug_scopes[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 311 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_extra_debug_scopes[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 342 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_pec_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 307 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_src_eid_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 305 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_payload_num_p3[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 301 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_message_completion_code_p3[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 297 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_cmd_extra_debug_scopes[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 268 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[125]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[118]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[111]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_cmd_busy" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 214 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_assigned_address[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 257 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_mctp_packet_busy_pos" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 337 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[124]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[117]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_device_address_type[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 133 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[110]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[103]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[120]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[121]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[122]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[123]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[116]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[109]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[102]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[95]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[112]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[113]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[114]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_capabilities[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 136 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[115]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_message_flag_to" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 131 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_sda|clk_div[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_debouncer:debouncer_scl|clk_div[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/mctp_debouncer.v Line: 19 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[108]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[101]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[94]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[87]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[104]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[105]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[106]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_version_revision[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 137 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[107]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_message_flag_to_debug_mode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 130 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_crc8_gen[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 226 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_tag[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 129 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[100]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[93]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[86]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[79]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[96]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[97]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[98]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[99]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_flag_to_debug_mode" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 327 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_tag[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 129 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 332 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 331 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_flag_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 128 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_slave_addr_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 316 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_slave_addr_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 315 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_2|flush1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 45 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_2|flush0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 46 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_1|flush1" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 45 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_1|flush0" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 46 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[92]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[85]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[78]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[71]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[88]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[89]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[90]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_vendor_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 138 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[91]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|pldm_over_mctp_resp_ctrl:pldm_over_mctp_resp_ctrl_inst0|resp_msg_tag[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_resp_ctrl.v Line: 129 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_src_eid_byte_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 334 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_des_eid_byte_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 333 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_tag_debug[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 335 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_msg_flag_byte[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 306 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[84]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[77]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[70]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[63]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[80]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[81]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[82]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[83]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_tag_debug[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 335 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_msg_flag_byte[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 306 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_2|flush2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 44 Info (17048): Logic cell "max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_race:u_trng_entropy_race_1|flush2" File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 44 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[76]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[69]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[62]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[55]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[72]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[73]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[74]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_device_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 139 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[75]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|resp_message_tag_debug[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 335 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|req_msg_flag_byte[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 306 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[68]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[61]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[54]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[47]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[64]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[65]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[66]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[67]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[60]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[53]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[46]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[39]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[56]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[57]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[58]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_interface[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 140 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[59]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[52]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[45]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[38]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[48]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[49]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[50]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[51]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[44]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[37]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[31]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[40]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[41]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[42]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_vendor_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 141 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[43]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[36]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[30]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[23]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[32]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[33]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[34]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[35]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[29]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[22]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[15]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_subsys_device_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 142 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[28]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[21]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[14]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[7]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[24]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[25]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[26]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[27]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[20]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[13]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[6]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[16]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[17]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[18]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[19]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[12]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[5]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[8]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[9]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[10]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[11]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_assigned[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 144 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[4]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[0]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[1]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[2]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (17048): Logic cell "mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|smbus_arp_controller:smbus_arp_controller_inst0|smbus_udid_valid_vdr_spec_id[3]" File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/smbus_arp_controller.v Line: 143 Info (128000): Starting physical synthesis optimizations for speed Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_b2i1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_gd9:dffpipe9|dffe10a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a* Info (332165): Entity dcfifo_e9h1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a* Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.sdc' Info (332104): Reading SDC File: 'acadp_bmc_max10.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[2]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[4]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|dataa" Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 19 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 100.000 clk_10m Info (332111): 40.000 clk_25m Info (332111): 20.000 clk_50m Info (332111): 10.000 clk_100m Info (332111): 10.000 clk_100m_p90 Info (332111): 40.000 egrs_spi_clk Info (332111): 40.000 egrs_spi_clk_int Info (332111): 40.000 flash_se_neg_reg Info (332111): 20.000 fpga_avst_clk Info (332111): 40.000 fpga_qspi_clk Info (332111): 10.000 hram_clk Info (332111): 10.000 hram_rwds_clk Info (332111): 10.000 hram_rwds_virt Info (332111): 40.000 ingrs_spi_clk Info (332111): 10.000 m10_clk_100m Info (332111): 181.818 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332111): 40.000 nqspi_sclk Info (332111): 40.000 nqspi_sclk_int Info (332111): 40.000 ru_clk Info (128002): Starting physical synthesis algorithm register retiming Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:15 Info (144001): Generated suppressed messages file /home/admin/otc/ofs-bmc/rtl/max10/build/output_files_retail/acadp_bmc_max10_retail.map.smsg Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 1 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "hps_cold_reset_n" File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 124 Info (21057): Implemented 51850 device resources after synthesis - the final resource count might be different Info (21058): Implemented 64 input pins Info (21059): Implemented 63 output pins Info (21060): Implemented 30 bidirectional pins Info (21061): Implemented 49570 logic cells Info (21064): Implemented 2047 RAM segments Info (21065): Implemented 1 PLLs Info (21062): Implemented 51 DSP elements Info (21070): Implemented 1 User Flash Memory blocks Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 186 warnings Info: Peak virtual memory: 1543 megabytes Info: Processing ended: Wed Apr 3 13:58:37 2024 Info: Elapsed time: 00:04:44 Info: Total CPU time (on all processors): 00:04:49 ............................................................................................... 2024-04-03 13:58:37 :: Building with seed = 1 2024-04-03 13:58:37 :: Running Fitter... Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 13:58:37 2024 Info: Command: quartus_fit acadp_bmc_max10 --rev=acadp_bmc_max10_retail --seed=1 Info: qfit2_default_script.tcl version: #1 Info: Project = acadp_bmc_max10 Info: Revision = acadp_bmc_max10_retail Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (119006): Selected device 10M50DAF256I6G for design "acadp_bmc_max10_retail" Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (15535): Implemented PLL "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|pll1" as MAX 10 PLL type File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (15099): Implementing clock multiplication of 1, clock division of 2, and phase shift of 0 degrees (0 ps) for max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|dual_boot_int_clk port File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (15099): Implementing clock multiplication of 1, clock division of 4, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of 120 degrees (3333 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[3] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 10, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[4] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device 10M16DAF256I6G is compatible Info (176445): Device 10M25DAF256I6G is compatible Info (176445): Device 10M40DAF256I6G is compatible Info (176445): Device 10M40DAF256I6GVM is compatible Info (169124): Fitter converted 3 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_JTAGEN~ is reserved at location G6 Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location F8 Info (169125): Pin ~ALTERA_CRC_ERROR~ is reserved at location C5 Info (169141): DATA[0] dual-purpose pin not reserved Info (12825): Data[1]/ASDO dual-purpose pin not reserved Info (12825): nCSO dual-purpose pin not reserved Info (12825): DCLK dual-purpose pin not reserved Info (169124): Fitter converted 16 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_ADC1IN1~ is reserved at location F5 Info (169125): Pin ~ALTERA_ADC2IN1~ is reserved at location C4 Info (169125): Pin ~ALTERA_ADC1IN2~ is reserved at location F4 Info (169125): Pin ~ALTERA_ADC2IN8~ is reserved at location C3 Info (169125): Pin ~ALTERA_ADC1IN3~ is reserved at location H5 Info (169125): Pin ~ALTERA_ADC2IN3~ is reserved at location E3 Info (169125): Pin ~ALTERA_ADC1IN4~ is reserved at location G5 Info (169125): Pin ~ALTERA_ADC2IN4~ is reserved at location F2 Info (169125): Pin ~ALTERA_ADC1IN5~ is reserved at location G2 Info (169125): Pin ~ALTERA_ADC2IN5~ is reserved at location C2 Info (169125): Pin ~ALTERA_ADC1IN6~ is reserved at location F1 Info (169125): Pin ~ALTERA_ADC2IN6~ is reserved at location B2 Info (169125): Pin ~ALTERA_ADC1IN7~ is reserved at location E1 Info (169125): Pin ~ALTERA_ADC2IN7~ is reserved at location B1 Info (169125): Pin ~ALTERA_ADC1IN8~ is reserved at location D1 Info (169125): Pin ~ALTERA_ADC2IN2~ is reserved at location C1 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_b2i1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_gd9:dffpipe9|dffe10a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a* Info (332165): Entity dcfifo_e9h1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a* Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.sdc' Info (332104): Reading SDC File: 'acadp_bmc_max10.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[2]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[4]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|dataa" Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 19 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 100.000 clk_10m Info (332111): 40.000 clk_25m Info (332111): 20.000 clk_50m Info (332111): 10.000 clk_100m Info (332111): 10.000 clk_100m_p90 Info (332111): 40.000 egrs_spi_clk Info (332111): 40.000 egrs_spi_clk_int Info (332111): 40.000 flash_se_neg_reg Info (332111): 20.000 fpga_avst_clk Info (332111): 40.000 fpga_qspi_clk Info (332111): 10.000 hram_clk Info (332111): 10.000 hram_rwds_clk Info (332111): 10.000 hram_rwds_virt Info (332111): 40.000 ingrs_spi_clk Info (332111): 10.000 m10_clk_100m Info (332111): 181.818 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332111): 40.000 nqspi_sclk Info (332111): 40.000 nqspi_sclk_int Info (332111): 40.000 ru_clk Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C3 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[3] (placed in counter C4 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 Info (176353): Automatically promoted node m10_clk_100m~input (placed in PIN P8 (CLK6p, DIFFIO_TX_RX_B18p, DIFFOUT_B18p, High_Speed)) File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 25 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|dual_boot_int_clk (placed in counter C1 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 Info (176353): Automatically promoted node ingrs_spi_clk~input (placed in PIN L3 (CLK0p, DIFFIO_RX_L28p, DIFFOUT_L28p, High_Speed)) File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 98 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_block:altera_onchip_flash_block|osc File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/altera_onchip_flash_block.v Line: 147 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_waitrequest~2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 180 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|next_state.STATE_SAME~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 127 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~31 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~33 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|write_operation~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 80 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~42 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~44 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|always9~0 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|rst_sync_50m[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 56 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|fpga_pwr_dwn File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 154 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|cvl_pwr_dwn File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 155 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[3] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[4] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[5] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node top_misc_interconnect:top_misc_inst|cfg_qspi0_rst_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 107 Info (176357): Destination node top_misc_interconnect:top_misc_inst|ptp_clk_rst_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 105 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|crypto_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 136 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[4] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[3] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|rflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|done File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|aflag[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|aflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|rflag[9] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|last_word_detect File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 118 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_ole:auto_generated|_~0 File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|comb~0 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|last_word_detect File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 118 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_nios_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_ole:auto_generated|_~0 File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|comb~0 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|in_t2_sel.01~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 32 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|dma_reset_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 105 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_resp_reset_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 348 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module:SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 654 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|MISOctl:SPIPhy_MISOctl|spi_domain_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 544 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 139 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_1|adjusting File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Line: 27 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_2|adjusting File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Line: 27 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|entropy_sel File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 60 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|consecutive_zeros File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|consecutive_ones File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 21 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|repeated_bits File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 22 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|consecutive_zeros File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|consecutive_ones File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 21 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|repeated_bits File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 22 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|race2_ok_i File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 59 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hbus_rwds_rst File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 156 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hbus_rwds_rst~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 156 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|locked File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 40 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|Selector1~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|Selector1~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|Selector0~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|Selector0~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|rst_sync_100m[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 129 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176218): Packed 134 registers into blocks of type Block RAM Extra Info (176218): Packed 48 registers into blocks of type Embedded multiplier block Extra Info (176218): Packed 64 registers into blocks of type Embedded multiplier output Extra Info (176218): Packed 6 registers into blocks of type I/O Input Buffer Extra Info (176218): Packed 7 registers into blocks of type I/O Output Buffer Extra Info (176220): Created 55 register duplicates Warning (15064): PLL "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "fpga_avst_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (128000): Starting physical synthesis optimizations for speed Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:14 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:54 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:16 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:02:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 28% of the available device resources Info (170196): Router estimated peak interconnect usage is 59% of the available device resources in the region that extends from location X56_Y33 to location X66_Y43 Info (170194): Fitter routing operations ending: elapsed time is 00:02:27 Info (11888): Total time spent on timing analysis during the Fitter is 142.20 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:33 Warning (169177): 42 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin bmc_smclk uses I/O standard 3.3-V LVCMOS at N5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 28 Info (169178): Pin bmc_smdat uses I/O standard 3.3-V LVCMOS at R1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 29 Info (169178): Pin m10_i2c_3v3_scl uses I/O standard 3.3-V LVCMOS at P4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 34 Info (169178): Pin m10_i2c_3v3_sda uses I/O standard 3.3-V LVCMOS at P2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 35 Info (169178): Pin pm_scl_3v3 uses I/O standard 3.3-V LVCMOS at R3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 38 Info (169178): Pin pm_sda_3v3 uses I/O standard 3.3-V LVCMOS at L7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 39 Info (169178): Pin vid_scl_3v3 uses I/O standard 3.3-V LVCMOS at A9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 44 Info (169178): Pin vid_sda_3v3 uses I/O standard 3.3-V LVCMOS at B8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 45 Info (169178): Pin gf_pcie_perst_n uses I/O standard 3.3-V LVCMOS at M9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 133 Info (169178): Pin m10_clk_100m uses I/O standard 3.3-V LVCMOS at P8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 25 Info (169178): Pin pg_vtt_0v6 uses I/O standard 3.3-V LVCMOS at B7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 168 Info (169178): Pin pg_vcc_3v3 uses I/O standard 3.3-V LVCMOS at A11 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 184 Info (169178): Pin pg_vcc_5v uses I/O standard 3.3-V LVCMOS at C10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 183 Info (169178): Pin pg_vcch_0v9 uses I/O standard 3.3-V LVCMOS at A3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 179 Info (169178): Pin pg_vccl_fpga_vid uses I/O standard 3.3-V LVCMOS at A5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 178 Info (169178): Pin pg_vcca_1v8 uses I/O standard 3.3-V LVCMOS at B9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 169 Info (169178): Pin pg_vcch_gxer_1v1 uses I/O standard 3.3-V LVCMOS at A12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 188 Info (169178): Pin pg_vcc_1v2 uses I/O standard 3.3-V LVCMOS at A2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 180 Info (169178): Pin pg_vcc_1v1_cvl uses I/O standard 3.3-V LVCMOS at C6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 174 Info (169178): Pin pg_avddh_1v1_cvl uses I/O standard 3.3-V LVCMOS at A6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 175 Info (169178): Pin pg_avdd_pcie_0v9_cvl uses I/O standard 3.3-V LVCMOS at B4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 177 Info (169178): Pin pg_avdd_eth_0v9_cvl uses I/O standard 3.3-V LVCMOS at B5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 176 Info (169178): Pin pg_vdd_0v8_cvl uses I/O standard 3.3-V LVCMOS at A7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 173 Info (169178): Pin qsfpa_modpres uses I/O standard 3.3-V LVCMOS at D12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 142 Info (169178): Pin qsfpb_modpres uses I/O standard 3.3-V LVCMOS at C13 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 143 Info (169178): Pin pcie_clk_los uses I/O standard 3.3-V LVCMOS at B10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 192 Info (169178): Pin pg_12v_aux_efuse uses I/O standard 3.3-V LVCMOS at B3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 181 Info (169178): Pin pg_12v_pcie_efuse uses I/O standard 3.3-V LVCMOS at A4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 182 Info (169178): Pin vcc_3v3_pcie_uv uses I/O standard 3.3-V LVCMOS at M8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 165 Info (169178): Pin vcc_12v_pcie_uv uses I/O standard 3.3-V LVCMOS at R9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 164 Info (169178): Pin edge_pwr_shdn uses I/O standard 3.3-V LVCMOS at T2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 57 Info (169178): Pin pg_pwr_qsfp0n uses I/O standard 3.3-V LVCMOS at A8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 171 Info (169178): Pin pg_pwr_qsfp1n uses I/O standard 3.3-V LVCMOS at B6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 172 Info (169178): Pin pm_alertn_3v3 uses I/O standard 3.3-V LVCMOS at R4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 41 Info (169178): Pin fpga_therm_alertn uses I/O standard 3.3-V LVCMOS at A15 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 53 Info (169178): Pin vr_vid_alertn uses I/O standard 3.3-V LVCMOS at T3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 48 Info (169178): Pin edge_pwr_warn uses I/O standard 3.3-V LVCMOS at P5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 56 Info (169178): Pin si5392_lol uses I/O standard 3.3-V LVCMOS at A10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 195 Info (169178): Pin ptp_clk_lol uses I/O standard 3.3-V LVCMOS at R6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 193 Info (169178): Pin alert_power2 uses I/O standard 3.3-V LVCMOS at E10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 202 Info (169178): Pin io_expndr_int_n uses I/O standard 3.3-V LVCMOS at R5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 199 Info (169178): Pin nios_uart_rx uses I/O standard 3.3-V LVCMOS at F12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 207 Critical Warning (16248): Pin m10_jtag_tck is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 72 Critical Warning (16248): Pin m10_jtag_tms is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 73 Critical Warning (16248): Pin m10_jtag_tdi is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 74 Critical Warning (16248): Pin strap_1_pclass1 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 197 Critical Warning (16248): Pin strap_3_cvl_prsnt0_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 141 Critical Warning (16248): Pin pg_vpp_2v5 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 170 Critical Warning (16248): Pin fpga_therm_shdn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 51 Critical Warning (16248): Pin m10_jtag_tdo is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 75 Critical Warning (16248): Pin m10_jtagen_sw is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 76 Critical Warning (16248): Pin fpga_qspi_cs_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 94 Critical Warning (16248): Pin ingrs_spi_csn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 99 Critical Warning (16248): Pin egrs_spi_csn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 103 Critical Warning (16248): Pin fpga_fabric_reset_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 136 Critical Warning (16248): Pin m10_status_led_g is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 127 Critical Warning (16248): Pin en_avdd_eth_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 155 Critical Warning (16248): Pin en_avdd_pcie_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 156 Critical Warning (16248): Pin en_vccl_fpga_vid is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 157 Critical Warning (16248): Pin en_vcc_1v2 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 158 Critical Warning (16248): Pin vid_scl_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 44 Critical Warning (16248): Pin vid_sda_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 45 Critical Warning (16248): Pin pg_vtt_0v6 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 168 Critical Warning (16248): Pin pg_vcc_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 184 Critical Warning (16248): Pin pg_vcc_5v is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 183 Critical Warning (16248): Pin pg_vcch_0v9 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 179 Critical Warning (16248): Pin pg_vccl_fpga_vid is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 178 Critical Warning (16248): Pin pg_vcca_1v8 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 169 Critical Warning (16248): Pin pg_vcch_gxer_1v1 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 188 Critical Warning (16248): Pin pg_vcc_1v2 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 180 Critical Warning (16248): Pin pg_vcc_1v1_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 174 Critical Warning (16248): Pin pg_avddh_1v1_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 175 Critical Warning (16248): Pin pg_avdd_pcie_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 177 Critical Warning (16248): Pin pg_avdd_eth_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 176 Critical Warning (16248): Pin pg_vdd_0v8_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 173 Critical Warning (16248): Pin pcie_clk_los is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 192 Critical Warning (16248): Pin pg_12v_aux_efuse is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 181 Critical Warning (16248): Pin pg_12v_pcie_efuse is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 182 Critical Warning (16248): Pin pg_pwr_qsfp0n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 171 Critical Warning (16248): Pin pg_pwr_qsfp1n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 172 Critical Warning (16248): Pin si5392_lol is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 195 Warning (169202): Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs. Info (144001): Generated suppressed messages file /home/admin/otc/ofs-bmc/rtl/max10/build/output_files_retail/acadp_bmc_max10_retail.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 56 warnings Info: Peak virtual memory: 3126 megabytes Info: Processing ended: Wed Apr 3 14:05:21 2024 Info: Elapsed time: 00:06:44 Info: Total CPU time (on all processors): 00:18:05 2024-04-03 14:05:22 :: Running Timing Analyzer... Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 14:05:22 2024 Info: Command: quartus_sta acadp_bmc_max10 --rev=acadp_bmc_max10_retail Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_b2i1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_gd9:dffpipe9|dffe10a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a* Info (332165): Entity dcfifo_e9h1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a* Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.sdc' Info (332104): Reading SDC File: 'acadp_bmc_max10.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[2]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[4]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|datad" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|datad" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|datad" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|datad" Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 100C Model Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Info (332146): Worst-case setup slack is 0.159 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.159 0.000 hram_clk Info (332119): 0.692 0.000 hram_rwds_clk Info (332119): 1.063 0.000 clk_100m Info (332119): 1.152 0.000 clk_50m Info (332119): 1.845 0.000 n/a Info (332119): 3.067 0.000 clk_100m_p90 Info (332119): 5.424 0.000 fpga_avst_clk Info (332119): 7.402 0.000 nqspi_sclk Info (332119): 7.541 0.000 egrs_spi_clk Info (332119): 7.742 0.000 m10_clk_100m Info (332119): 9.277 0.000 clk_25m Info (332119): 10.532 0.000 ingrs_spi_clk Info (332119): 12.941 0.000 fpga_qspi_clk Info (332119): 13.397 0.000 flash_se_neg_reg Info (332146): Worst-case hold slack is 0.208 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.208 0.000 clk_50m Info (332119): 0.227 0.000 hram_rwds_clk Info (332119): 0.331 0.000 ingrs_spi_clk Info (332119): 0.332 0.000 m10_clk_100m Info (332119): 0.344 0.000 clk_100m Info (332119): 0.354 0.000 clk_25m Info (332119): 0.368 0.000 fpga_qspi_clk Info (332119): 0.691 0.000 egrs_spi_clk Info (332119): 0.918 0.000 hram_clk Info (332119): 2.516 0.000 clk_100m_p90 Info (332119): 2.793 0.000 fpga_avst_clk Info (332119): 2.942 0.000 n/a Info (332119): 3.907 0.000 flash_se_neg_reg Info (332119): 4.495 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 3.821 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.821 0.000 clk_100m Info (332119): 4.687 0.000 clk_50m Info (332119): 5.390 0.000 ingrs_spi_clk Info (332119): 6.644 0.000 clk_100m_p90 Info (332119): 6.679 0.000 hram_rwds_clk Info (332119): 15.737 0.000 fpga_qspi_clk Info (332119): 34.237 0.000 clk_25m Info (332146): Worst-case removal slack is 0.955 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.955 0.000 clk_50m Info (332119): 1.372 0.000 clk_100m Info (332119): 1.936 0.000 hram_rwds_clk Info (332119): 2.293 0.000 ingrs_spi_clk Info (332119): 2.776 0.000 fpga_qspi_clk Info (332119): 3.019 0.000 clk_100m_p90 Info (332119): 3.305 0.000 clk_25m Info (332146): Worst-case minimum pulse width slack is 4.577 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.577 0.000 m10_clk_100m Info (332119): 4.672 0.000 hram_rwds_clk Info (332119): 4.674 0.000 clk_100m Info (332119): 4.733 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.702 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.706 0.000 flash_se_neg_reg Info (332119): 19.636 0.000 clk_25m Info (332119): 19.655 0.000 fpga_qspi_clk Info (332119): 19.687 0.000 ingrs_spi_clk Info (332119): 19.861 0.000 egrs_spi_clk_int Info (332119): 19.966 0.000 nqspi_sclk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.246 0.000 clk_10m Info (332119): 90.660 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 15.005 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info: Analyzing Slow 1200mV -40C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -0.010 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -0.010 -0.010 hram_clk Info (332119): 1.123 0.000 hram_rwds_clk Info (332119): 1.471 0.000 clk_100m Info (332119): 2.442 0.000 clk_50m Info (332119): 2.712 0.000 n/a Info (332119): 3.228 0.000 clk_100m_p90 Info (332119): 6.514 0.000 fpga_avst_clk Info (332119): 7.225 0.000 egrs_spi_clk Info (332119): 7.263 0.000 nqspi_sclk Info (332119): 8.029 0.000 m10_clk_100m Info (332119): 10.425 0.000 ingrs_spi_clk Info (332119): 13.586 0.000 clk_25m Info (332119): 13.887 0.000 fpga_qspi_clk Info (332119): 14.227 0.000 flash_se_neg_reg Info (332146): Worst-case hold slack is 0.159 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.159 0.000 clk_50m Info (332119): 0.231 0.000 hram_rwds_clk Info (332119): 0.276 0.000 clk_100m Info (332119): 0.285 0.000 clk_25m Info (332119): 0.287 0.000 ingrs_spi_clk Info (332119): 0.288 0.000 m10_clk_100m Info (332119): 0.319 0.000 fpga_qspi_clk Info (332119): 1.064 0.000 hram_clk Info (332119): 1.103 0.000 egrs_spi_clk Info (332119): 2.281 0.000 fpga_avst_clk Info (332119): 2.412 0.000 clk_100m_p90 Info (332119): 2.629 0.000 n/a Info (332119): 3.311 0.000 flash_se_neg_reg Info (332119): 4.359 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 4.639 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.639 0.000 clk_100m Info (332119): 5.359 0.000 clk_50m Info (332119): 6.682 0.000 ingrs_spi_clk Info (332119): 6.793 0.000 clk_100m_p90 Info (332119): 7.118 0.000 hram_rwds_clk Info (332119): 16.261 0.000 fpga_qspi_clk Info (332119): 35.033 0.000 clk_25m Info (332146): Worst-case removal slack is 0.802 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.802 0.000 clk_50m Info (332119): 1.173 0.000 clk_100m Info (332119): 1.779 0.000 hram_rwds_clk Info (332119): 2.070 0.000 ingrs_spi_clk Info (332119): 2.360 0.000 fpga_qspi_clk Info (332119): 2.816 0.000 clk_25m Info (332119): 2.860 0.000 clk_100m_p90 Info (332146): Worst-case minimum pulse width slack is 4.584 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.584 0.000 m10_clk_100m Info (332119): 4.617 0.000 hram_rwds_clk Info (332119): 4.700 0.000 clk_100m Info (332119): 4.713 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.603 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.678 0.000 flash_se_neg_reg Info (332119): 19.666 0.000 clk_25m Info (332119): 19.706 0.000 ingrs_spi_clk Info (332119): 19.728 0.000 fpga_qspi_clk Info (332119): 19.934 0.000 egrs_spi_clk_int Info (332119): 19.939 0.000 nqspi_sclk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.255 0.000 clk_10m Info (332119): 90.660 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 15.421 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info: Analyzing Fast 1200mV -40C Model Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 0.072 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.072 0.000 hram_rwds_clk Info (332119): 0.259 0.000 hram_clk Info (332119): 2.519 0.000 clk_100m Info (332119): 4.146 0.000 clk_100m_p90 Info (332119): 5.679 0.000 clk_50m Info (332119): 6.012 0.000 n/a Info (332119): 7.745 0.000 nqspi_sclk Info (332119): 8.356 0.000 egrs_spi_clk Info (332119): 8.510 0.000 fpga_avst_clk Info (332119): 8.963 0.000 m10_clk_100m Info (332119): 10.388 0.000 ingrs_spi_clk Info (332119): 16.642 0.000 fpga_qspi_clk Info (332119): 16.651 0.000 flash_se_neg_reg Info (332119): 25.780 0.000 clk_25m Info (332146): Worst-case hold slack is 0.088 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.088 0.000 hram_rwds_clk Info (332119): 0.097 0.000 clk_50m Info (332119): 0.139 0.000 ingrs_spi_clk Info (332119): 0.140 0.000 m10_clk_100m Info (332119): 0.158 0.000 fpga_qspi_clk Info (332119): 0.163 0.000 clk_100m Info (332119): 0.177 0.000 clk_25m Info (332119): 0.578 0.000 egrs_spi_clk Info (332119): 0.694 0.000 fpga_avst_clk Info (332119): 0.905 0.000 hram_clk Info (332119): 1.049 0.000 flash_se_neg_reg Info (332119): 1.410 0.000 n/a Info (332119): 1.987 0.000 clk_100m_p90 Info (332119): 4.179 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 6.992 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 6.992 0.000 clk_100m Info (332119): 7.399 0.000 clk_50m Info (332119): 7.573 0.000 clk_100m_p90 Info (332119): 8.216 0.000 hram_rwds_clk Info (332119): 10.301 0.000 ingrs_spi_clk Info (332119): 17.740 0.000 fpga_qspi_clk Info (332119): 37.140 0.000 clk_25m Info (332146): Worst-case removal slack is 0.433 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.433 0.000 clk_50m Info (332119): 0.601 0.000 clk_100m Info (332119): 0.932 0.000 ingrs_spi_clk Info (332119): 0.962 0.000 hram_rwds_clk Info (332119): 1.235 0.000 fpga_qspi_clk Info (332119): 1.602 0.000 clk_25m Info (332119): 2.227 0.000 clk_100m_p90 Info (332146): Worst-case minimum pulse width slack is 3.532 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.532 0.000 m10_clk_100m Info (332119): 4.599 0.000 hram_rwds_clk Info (332119): 4.727 0.000 clk_100m Info (332119): 4.743 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.890 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.965 0.000 flash_se_neg_reg Info (332119): 19.700 0.000 fpga_qspi_clk Info (332119): 19.715 0.000 clk_25m Info (332119): 19.756 0.000 ingrs_spi_clk Info (332119): 19.963 0.000 nqspi_sclk_int Info (332119): 19.973 0.000 egrs_spi_clk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.904 0.000 clk_10m Info (332119): 90.688 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 17.403 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info (332101): Design is fully constrained for setup requirements Info (332101): Design is fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 14 warnings Info: Peak virtual memory: 1276 megabytes Info: Processing ended: Wed Apr 3 14:05:44 2024 Info: Elapsed time: 00:00:22 Info: Total CPU time (on all processors): 00:01:10 ....................BEGIN CRITICAL warnings (if any)........................................... Critical Warning (332148): Timing requirements not met ....................END CRITICAL warnings (if any)............................................. ............................................................................................... 2024-04-03 14:05:44 :: Building with seed = 2 2024-04-03 14:05:44 :: Running Fitter... Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 14:05:44 2024 Info: Command: quartus_fit acadp_bmc_max10 --rev=acadp_bmc_max10_retail --seed=2 Info: qfit2_default_script.tcl version: #1 Info: Project = acadp_bmc_max10 Info: Revision = acadp_bmc_max10_retail Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (119006): Selected device 10M50DAF256I6G for design "acadp_bmc_max10_retail" Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (15535): Implemented PLL "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|pll1" as MAX 10 PLL type File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (15099): Implementing clock multiplication of 1, clock division of 2, and phase shift of 0 degrees (0 ps) for max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|dual_boot_int_clk port File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (15099): Implementing clock multiplication of 1, clock division of 4, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of 120 degrees (3333 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[3] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (15099): Implementing clock multiplication of 1, clock division of 10, and phase shift of 0 degrees (0 ps) for clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[4] port File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 51 Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device 10M16DAF256I6G is compatible Info (176445): Device 10M25DAF256I6G is compatible Info (176445): Device 10M40DAF256I6G is compatible Info (176445): Device 10M40DAF256I6GVM is compatible Info (169124): Fitter converted 3 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_JTAGEN~ is reserved at location G6 Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location F8 Info (169125): Pin ~ALTERA_CRC_ERROR~ is reserved at location C5 Info (169141): DATA[0] dual-purpose pin not reserved Info (12825): Data[1]/ASDO dual-purpose pin not reserved Info (12825): nCSO dual-purpose pin not reserved Info (12825): DCLK dual-purpose pin not reserved Info (169124): Fitter converted 16 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_ADC1IN1~ is reserved at location F5 Info (169125): Pin ~ALTERA_ADC2IN1~ is reserved at location C4 Info (169125): Pin ~ALTERA_ADC1IN2~ is reserved at location F4 Info (169125): Pin ~ALTERA_ADC2IN8~ is reserved at location C3 Info (169125): Pin ~ALTERA_ADC1IN3~ is reserved at location H5 Info (169125): Pin ~ALTERA_ADC2IN3~ is reserved at location E3 Info (169125): Pin ~ALTERA_ADC1IN4~ is reserved at location G5 Info (169125): Pin ~ALTERA_ADC2IN4~ is reserved at location F2 Info (169125): Pin ~ALTERA_ADC1IN5~ is reserved at location G2 Info (169125): Pin ~ALTERA_ADC2IN5~ is reserved at location C2 Info (169125): Pin ~ALTERA_ADC1IN6~ is reserved at location F1 Info (169125): Pin ~ALTERA_ADC2IN6~ is reserved at location B2 Info (169125): Pin ~ALTERA_ADC1IN7~ is reserved at location E1 Info (169125): Pin ~ALTERA_ADC2IN7~ is reserved at location B1 Info (169125): Pin ~ALTERA_ADC1IN8~ is reserved at location D1 Info (169125): Pin ~ALTERA_ADC2IN2~ is reserved at location C1 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_b2i1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_gd9:dffpipe9|dffe10a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a* Info (332165): Entity dcfifo_e9h1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a* Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.sdc' Info (332104): Reading SDC File: 'acadp_bmc_max10.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[2]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[4]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|dataa" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|dataa" Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 19 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 100.000 clk_10m Info (332111): 40.000 clk_25m Info (332111): 20.000 clk_50m Info (332111): 10.000 clk_100m Info (332111): 10.000 clk_100m_p90 Info (332111): 40.000 egrs_spi_clk Info (332111): 40.000 egrs_spi_clk_int Info (332111): 40.000 flash_se_neg_reg Info (332111): 20.000 fpga_avst_clk Info (332111): 40.000 fpga_qspi_clk Info (332111): 10.000 hram_clk Info (332111): 10.000 hram_rwds_clk Info (332111): 10.000 hram_rwds_virt Info (332111): 40.000 ingrs_spi_clk Info (332111): 10.000 m10_clk_100m Info (332111): 181.818 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332111): 40.000 nqspi_sclk Info (332111): 40.000 nqspi_sclk_int Info (332111): 40.000 ru_clk Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C3 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|wire_pll1_clk[3] (placed in counter C4 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 Info (176353): Automatically promoted node m10_clk_100m~input (placed in PIN P8 (CLK6p, DIFFIO_TX_RX_B18p, DIFFOUT_B18p, High_Speed)) File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 25 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|dual_boot_int_clk (placed in counter C1 of PLL_1) File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 93 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 Info (176353): Automatically promoted node ingrs_spi_clk~input (placed in PIN L3 (CLK0p, DIFFIO_RX_L28p, DIFFOUT_L28p, High_Speed)) File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 98 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_block:altera_onchip_flash_block|osc File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/altera_onchip_flash_block.v Line: 147 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_waitrequest~2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 180 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|next_state.STATE_SAME~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 127 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~31 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~33 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|write_operation~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 80 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~42 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_dual_boot:dual_boot|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state~44 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot.v Line: 126 Info (176357): Destination node max10_qsys:max10_qsys_inst|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|always9~0 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|rst_sync_50m[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 56 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|fpga_pwr_dwn File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 154 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|cvl_pwr_dwn File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 155 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[3] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[4] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node flow_control_top:flow_ctrl_top_inst|power_sequencer:power_sequencer_inst|rpc_stg1_cntr[5] File: /home/admin/otc/ofs-bmc/rtl/max10/design/power_sequencer/power_sequencer.sv Line: 805 Info (176357): Destination node top_misc_interconnect:top_misc_inst|cfg_qspi0_rst_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 107 Info (176357): Destination node top_misc_interconnect:top_misc_inst|ptp_clk_rst_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/top_misc_interconnect.sv Line: 105 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|crypto_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 136 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[4] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[3] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|mflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|rflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|done File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|aflag[1] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|aflag[0] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|rflag[9] File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 93 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|last_word_detect File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 118 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|max10_qsys_fpga_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_ole:auto_generated|_~0 File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_fpga_flash:fpga_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|comb~0 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|last_word_detect File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/intel_generic_serial_flash_interface_cmd.sv Line: 118 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|max10_qsys_nios_flash_qspi_inf_inst:qspi_inf_inst|scfifo:sideband_buf|a_fffifo:subfifo|lpm_counter:rd_ptr|cntr_ole:auto_generated|_~0 File: /home/admin/intelFPGA/23.1std/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_nios_flash:nios_flash|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|comb~0 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_synchronizer.v Line: 62 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|ecdsa384_top:u_ecdsa|multr_all_384x384:i_ma384|in_t2_sel.01~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/multr_all_384x384.v Line: 32 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|bmc_dma:bmc_dma|dma_reset_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/bmc_dma.sv Line: 105 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node mctp_over_smbus:mctp_over_smbus_inst|pldm_over_mctp_top_controller:mctp_o_smbus_ctrlr_inst|mctp_resp_reset_n File: /home/admin/otc/ofs-bmc/rtl/max10/design/mctp_over_smbus/pldm_over_mctp_top_controller.v Line: 348 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module:SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/SPISlaveToAvalonMasterBridge.v Line: 654 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|SPISlaveToAvalonMasterBridge:spi_slave|spislave_inst_for_spichain:the_spislave_inst_for_spichain|SPIPhy:the_SPIPhy|MISOctl:SPIPhy_MISOctl|spi_domain_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.v Line: 544 Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_reset File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/crypto_top.sv Line: 139 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_1|adjusting File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Line: 27 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_adjust:u_trng_entropy_adjust_2|adjusting File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_adjust.v Line: 27 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|entropy_sel File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 60 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|consecutive_zeros File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|consecutive_ones File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 21 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_1|repeated_bits File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 22 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|consecutive_zeros File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 20 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|consecutive_ones File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 21 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|max10_trng_entropy_health:u_trng_entropy_health_2|repeated_bits File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_health.v Line: 22 Info (176357): Destination node max10_qsys:max10_qsys_inst|crypto_top_wrapper:crypto_384|crypto_top:crypto_384|entropy_source:u_entropy_source|max10_trng_entropy:entropy_source_inst|race2_ok_i File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy.v Line: 59 Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hbus_rwds_rst File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 156 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|hyperram_ctrlr:hyper_ram|hbus_rwds_rst~0 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/hyperram_ctrlr.sv Line: 156 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|locked File: /home/admin/otc/ofs-bmc/rtl/max10/build/db/system_pll_altpll.v Line: 40 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|Selector1~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|Selector1~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|Selector0~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176357): Destination node max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|altera_modular_adc_control_fsm:u_control_fsm|Selector0~1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control_fsm.v Line: 243 Info (176353): Automatically promoted node clk_rst_top:clk_rst_inst|rst_sync_100m[2] File: /home/admin/otc/ofs-bmc/rtl/max10/design/clock_reset/clk_rst_top.sv Line: 129 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176218): Packed 134 registers into blocks of type Block RAM Extra Info (176218): Packed 48 registers into blocks of type Embedded multiplier block Extra Info (176218): Packed 64 registers into blocks of type Embedded multiplier output Extra Info (176218): Packed 6 registers into blocks of type I/O Input Buffer Extra Info (176218): Packed 7 registers into blocks of type I/O Output Buffer Extra Info (176220): Created 55 register duplicates Warning (15064): PLL "clk_rst_top:clk_rst_inst|system_pll:inst_sys_pll|altpll:altpll_component|system_pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "fpga_avst_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/rtl/alt_dual_boot_avmm.v Line: 43 Info (128000): Starting physical synthesis optimizations for speed Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:13 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:56 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:18 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:02:03 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 30% of the available device resources Info (170196): Router estimated peak interconnect usage is 62% of the available device resources in the region that extends from location X11_Y22 to location X21_Y32 Info (170194): Fitter routing operations ending: elapsed time is 00:02:34 Info (11888): Total time spent on timing analysis during the Fitter is 146.94 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:33 Warning (169177): 42 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin bmc_smclk uses I/O standard 3.3-V LVCMOS at N5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 28 Info (169178): Pin bmc_smdat uses I/O standard 3.3-V LVCMOS at R1 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 29 Info (169178): Pin m10_i2c_3v3_scl uses I/O standard 3.3-V LVCMOS at P4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 34 Info (169178): Pin m10_i2c_3v3_sda uses I/O standard 3.3-V LVCMOS at P2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 35 Info (169178): Pin pm_scl_3v3 uses I/O standard 3.3-V LVCMOS at R3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 38 Info (169178): Pin pm_sda_3v3 uses I/O standard 3.3-V LVCMOS at L7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 39 Info (169178): Pin vid_scl_3v3 uses I/O standard 3.3-V LVCMOS at A9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 44 Info (169178): Pin vid_sda_3v3 uses I/O standard 3.3-V LVCMOS at B8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 45 Info (169178): Pin gf_pcie_perst_n uses I/O standard 3.3-V LVCMOS at M9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 133 Info (169178): Pin m10_clk_100m uses I/O standard 3.3-V LVCMOS at P8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 25 Info (169178): Pin pg_vtt_0v6 uses I/O standard 3.3-V LVCMOS at B7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 168 Info (169178): Pin pg_vcc_3v3 uses I/O standard 3.3-V LVCMOS at A11 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 184 Info (169178): Pin pg_vcc_5v uses I/O standard 3.3-V LVCMOS at C10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 183 Info (169178): Pin pg_vcch_0v9 uses I/O standard 3.3-V LVCMOS at A3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 179 Info (169178): Pin pg_vccl_fpga_vid uses I/O standard 3.3-V LVCMOS at A5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 178 Info (169178): Pin pg_vcca_1v8 uses I/O standard 3.3-V LVCMOS at B9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 169 Info (169178): Pin pg_vcch_gxer_1v1 uses I/O standard 3.3-V LVCMOS at A12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 188 Info (169178): Pin pg_vcc_1v2 uses I/O standard 3.3-V LVCMOS at A2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 180 Info (169178): Pin pg_vcc_1v1_cvl uses I/O standard 3.3-V LVCMOS at C6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 174 Info (169178): Pin pg_avddh_1v1_cvl uses I/O standard 3.3-V LVCMOS at A6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 175 Info (169178): Pin pg_avdd_pcie_0v9_cvl uses I/O standard 3.3-V LVCMOS at B4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 177 Info (169178): Pin pg_avdd_eth_0v9_cvl uses I/O standard 3.3-V LVCMOS at B5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 176 Info (169178): Pin pg_vdd_0v8_cvl uses I/O standard 3.3-V LVCMOS at A7 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 173 Info (169178): Pin qsfpa_modpres uses I/O standard 3.3-V LVCMOS at D12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 142 Info (169178): Pin qsfpb_modpres uses I/O standard 3.3-V LVCMOS at C13 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 143 Info (169178): Pin pcie_clk_los uses I/O standard 3.3-V LVCMOS at B10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 192 Info (169178): Pin pg_12v_aux_efuse uses I/O standard 3.3-V LVCMOS at B3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 181 Info (169178): Pin pg_12v_pcie_efuse uses I/O standard 3.3-V LVCMOS at A4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 182 Info (169178): Pin vcc_3v3_pcie_uv uses I/O standard 3.3-V LVCMOS at M8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 165 Info (169178): Pin vcc_12v_pcie_uv uses I/O standard 3.3-V LVCMOS at R9 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 164 Info (169178): Pin edge_pwr_shdn uses I/O standard 3.3-V LVCMOS at T2 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 57 Info (169178): Pin pg_pwr_qsfp0n uses I/O standard 3.3-V LVCMOS at A8 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 171 Info (169178): Pin pg_pwr_qsfp1n uses I/O standard 3.3-V LVCMOS at B6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 172 Info (169178): Pin pm_alertn_3v3 uses I/O standard 3.3-V LVCMOS at R4 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 41 Info (169178): Pin fpga_therm_alertn uses I/O standard 3.3-V LVCMOS at A15 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 53 Info (169178): Pin vr_vid_alertn uses I/O standard 3.3-V LVCMOS at T3 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 48 Info (169178): Pin edge_pwr_warn uses I/O standard 3.3-V LVCMOS at P5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 56 Info (169178): Pin si5392_lol uses I/O standard 3.3-V LVCMOS at A10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 195 Info (169178): Pin ptp_clk_lol uses I/O standard 3.3-V LVCMOS at R6 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 193 Info (169178): Pin alert_power2 uses I/O standard 3.3-V LVCMOS at E10 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 202 Info (169178): Pin io_expndr_int_n uses I/O standard 3.3-V LVCMOS at R5 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 199 Info (169178): Pin nios_uart_rx uses I/O standard 3.3-V LVCMOS at F12 File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 207 Critical Warning (16248): Pin m10_jtag_tck is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 72 Critical Warning (16248): Pin m10_jtag_tms is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 73 Critical Warning (16248): Pin m10_jtag_tdi is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 74 Critical Warning (16248): Pin strap_1_pclass1 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 197 Critical Warning (16248): Pin strap_3_cvl_prsnt0_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 141 Critical Warning (16248): Pin pg_vpp_2v5 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 170 Critical Warning (16248): Pin fpga_therm_shdn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 51 Critical Warning (16248): Pin m10_jtag_tdo is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 75 Critical Warning (16248): Pin m10_jtagen_sw is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 76 Critical Warning (16248): Pin fpga_qspi_cs_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 94 Critical Warning (16248): Pin ingrs_spi_csn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 99 Critical Warning (16248): Pin egrs_spi_csn is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 103 Critical Warning (16248): Pin fpga_fabric_reset_n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 136 Critical Warning (16248): Pin m10_status_led_g is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 127 Critical Warning (16248): Pin en_avdd_eth_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 155 Critical Warning (16248): Pin en_avdd_pcie_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 156 Critical Warning (16248): Pin en_vccl_fpga_vid is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 157 Critical Warning (16248): Pin en_vcc_1v2 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 158 Critical Warning (16248): Pin vid_scl_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 44 Critical Warning (16248): Pin vid_sda_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 45 Critical Warning (16248): Pin pg_vtt_0v6 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 168 Critical Warning (16248): Pin pg_vcc_3v3 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 184 Critical Warning (16248): Pin pg_vcc_5v is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 183 Critical Warning (16248): Pin pg_vcch_0v9 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 179 Critical Warning (16248): Pin pg_vccl_fpga_vid is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 178 Critical Warning (16248): Pin pg_vcca_1v8 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 169 Critical Warning (16248): Pin pg_vcch_gxer_1v1 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 188 Critical Warning (16248): Pin pg_vcc_1v2 is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 180 Critical Warning (16248): Pin pg_vcc_1v1_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 174 Critical Warning (16248): Pin pg_avddh_1v1_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 175 Critical Warning (16248): Pin pg_avdd_pcie_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 177 Critical Warning (16248): Pin pg_avdd_eth_0v9_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 176 Critical Warning (16248): Pin pg_vdd_0v8_cvl is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 173 Critical Warning (16248): Pin pcie_clk_los is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 192 Critical Warning (16248): Pin pg_12v_aux_efuse is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 181 Critical Warning (16248): Pin pg_12v_pcie_efuse is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 182 Critical Warning (16248): Pin pg_pwr_qsfp0n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 171 Critical Warning (16248): Pin pg_pwr_qsfp1n is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 172 Critical Warning (16248): Pin si5392_lol is placed too close with ADC pins. I/O pins place too near to ADC pins will cause performance degradation on ADC sampling. Please reassign the pin assignment further away from ADC pins and re-run the compilation again. File: /home/admin/otc/ofs-bmc/rtl/max10/design/top/acadp_bmc_max10_top.sv Line: 195 Warning (169202): Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs. Info (144001): Generated suppressed messages file /home/admin/otc/ofs-bmc/rtl/max10/build/output_files_retail/acadp_bmc_max10_retail.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 56 warnings Info: Peak virtual memory: 3195 megabytes Info: Processing ended: Wed Apr 3 14:12:45 2024 Info: Elapsed time: 00:07:01 Info: Total CPU time (on all processors): 00:17:18 2024-04-03 14:12:45 :: Running Timing Analyzer... Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 14:12:45 2024 Info: Command: quartus_sta acadp_bmc_max10 --rev=acadp_bmc_max10_retail Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_b2i1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_gd9:dffpipe9|dffe10a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a* Info (332165): Entity dcfifo_e9h1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a* Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/spiphyslave.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_onchip_flash.sdc' Info (332104): Reading SDC File: '../design/max10_qsys/max10_qsys/synthesis/submodules/altera_modular_adc_control.sdc' Info (332104): Reading SDC File: 'acadp_bmc_max10.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 181.818 -name {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} {max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[2]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[3]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332099): You called derive_pll_clocks. User-defined clock found on pll: clk_rst_inst|inst_sys_pll|altpll_component|auto_generated|pll1|clk[4]. Original clock has priority over derived pll clocks. No clocks added to this pll. Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|b_wins_latch|datad" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_2|a_wins_latch|datad" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 40 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|b_wins_latch|datad" Warning (332125): Found combinational loop of 2 nodes File: /home/admin/otc/ofs-bmc/rtl/max10/design/max10_qsys/max10_qsys/synthesis/submodules/max10_trng_entropy_race.v Line: 39 Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|combout" Warning (332126): Node "max10_qsys_inst|crypto_384|crypto_384|u_entropy_source|entropy_source_inst|u_trng_entropy_race_1|a_wins_latch|datad" Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 100C Model Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Info (332146): Worst-case setup slack is 0.182 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.182 0.000 hram_clk Info (332119): 1.085 0.000 clk_100m Info (332119): 1.188 0.000 hram_rwds_clk Info (332119): 1.473 0.000 clk_50m Info (332119): 1.849 0.000 n/a Info (332119): 3.215 0.000 clk_100m_p90 Info (332119): 4.884 0.000 fpga_avst_clk Info (332119): 5.994 0.000 egrs_spi_clk Info (332119): 7.304 0.000 nqspi_sclk Info (332119): 7.450 0.000 m10_clk_100m Info (332119): 8.955 0.000 clk_25m Info (332119): 9.387 0.000 ingrs_spi_clk Info (332119): 11.329 0.000 fpga_qspi_clk Info (332119): 14.007 0.000 flash_se_neg_reg Info (332146): Worst-case hold slack is 0.215 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.215 0.000 clk_50m Info (332119): 0.289 0.000 fpga_qspi_clk Info (332119): 0.295 0.000 clk_25m Info (332119): 0.332 0.000 ingrs_spi_clk Info (332119): 0.332 0.000 m10_clk_100m Info (332119): 0.368 0.000 hram_rwds_clk Info (332119): 0.380 0.000 clk_100m Info (332119): 0.610 0.000 hram_clk Info (332119): 0.997 0.000 egrs_spi_clk Info (332119): 2.744 0.000 clk_100m_p90 Info (332119): 2.808 0.000 fpga_avst_clk Info (332119): 2.986 0.000 n/a Info (332119): 3.054 0.000 flash_se_neg_reg Info (332119): 4.383 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 3.955 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.955 0.000 clk_100m Info (332119): 5.106 0.000 clk_50m Info (332119): 5.266 0.000 ingrs_spi_clk Info (332119): 5.749 0.000 clk_100m_p90 Info (332119): 6.865 0.000 hram_rwds_clk Info (332119): 15.487 0.000 fpga_qspi_clk Info (332119): 34.957 0.000 clk_25m Info (332146): Worst-case removal slack is 0.957 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.957 0.000 clk_50m Info (332119): 1.599 0.000 clk_100m Info (332119): 1.834 0.000 hram_rwds_clk Info (332119): 2.285 0.000 ingrs_spi_clk Info (332119): 2.894 0.000 fpga_qspi_clk Info (332119): 3.549 0.000 clk_25m Info (332119): 3.851 0.000 clk_100m_p90 Info (332146): Worst-case minimum pulse width slack is 4.577 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.577 0.000 m10_clk_100m Info (332119): 4.671 0.000 hram_rwds_clk Info (332119): 4.673 0.000 clk_100m Info (332119): 4.733 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.705 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.705 0.000 flash_se_neg_reg Info (332119): 19.645 0.000 clk_25m Info (332119): 19.669 0.000 fpga_qspi_clk Info (332119): 19.686 0.000 ingrs_spi_clk Info (332119): 19.861 0.000 egrs_spi_clk_int Info (332119): 19.961 0.000 nqspi_sclk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.246 0.000 clk_10m Info (332119): 90.667 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 14.672 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info: Analyzing Slow 1200mV -40C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 0.283 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.283 0.000 hram_clk Info (332119): 1.200 0.000 hram_rwds_clk Info (332119): 1.525 0.000 clk_100m Info (332119): 2.718 0.000 n/a Info (332119): 2.775 0.000 clk_50m Info (332119): 3.362 0.000 clk_100m_p90 Info (332119): 6.034 0.000 fpga_avst_clk Info (332119): 6.526 0.000 egrs_spi_clk Info (332119): 7.180 0.000 nqspi_sclk Info (332119): 7.800 0.000 m10_clk_100m Info (332119): 9.469 0.000 ingrs_spi_clk Info (332119): 12.503 0.000 fpga_qspi_clk Info (332119): 13.145 0.000 clk_25m Info (332119): 14.666 0.000 flash_se_neg_reg Info (332146): Worst-case hold slack is 0.167 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.167 0.000 clk_50m Info (332119): 0.231 0.000 clk_25m Info (332119): 0.266 0.000 fpga_qspi_clk Info (332119): 0.287 0.000 ingrs_spi_clk Info (332119): 0.288 0.000 m10_clk_100m Info (332119): 0.293 0.000 clk_100m Info (332119): 0.319 0.000 hram_rwds_clk Info (332119): 1.064 0.000 hram_clk Info (332119): 1.384 0.000 egrs_spi_clk Info (332119): 2.290 0.000 fpga_avst_clk Info (332119): 2.497 0.000 flash_se_neg_reg Info (332119): 2.586 0.000 clk_100m_p90 Info (332119): 2.680 0.000 n/a Info (332119): 4.562 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 4.749 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.749 0.000 clk_100m Info (332119): 5.716 0.000 clk_50m Info (332119): 6.021 0.000 clk_100m_p90 Info (332119): 6.766 0.000 ingrs_spi_clk Info (332119): 7.269 0.000 hram_rwds_clk Info (332119): 16.104 0.000 fpga_qspi_clk Info (332119): 35.628 0.000 clk_25m Info (332146): Worst-case removal slack is 0.801 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.801 0.000 clk_50m Info (332119): 1.378 0.000 clk_100m Info (332119): 1.683 0.000 hram_rwds_clk Info (332119): 2.142 0.000 ingrs_spi_clk Info (332119): 2.510 0.000 fpga_qspi_clk Info (332119): 3.055 0.000 clk_25m Info (332119): 3.598 0.000 clk_100m_p90 Info (332146): Worst-case minimum pulse width slack is 4.584 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 4.584 0.000 m10_clk_100m Info (332119): 4.609 0.000 hram_rwds_clk Info (332119): 4.699 0.000 clk_100m Info (332119): 4.712 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.605 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.680 0.000 flash_se_neg_reg Info (332119): 19.667 0.000 clk_25m Info (332119): 19.712 0.000 ingrs_spi_clk Info (332119): 19.727 0.000 fpga_qspi_clk Info (332119): 19.935 0.000 egrs_spi_clk_int Info (332119): 19.947 0.000 nqspi_sclk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.255 0.000 clk_10m Info (332119): 90.662 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 15.160 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info: Analyzing Fast 1200mV -40C Model Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): From: max10_qsys_inst|adc|control_internal_2|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal_2|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): From: max10_qsys_inst|adc|control_internal|adc_inst|adcblock_instance|primitive_instance|clkin_from_pll_c0 to: max10_qsys:max10_qsys_inst|max10_qsys_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|eoc Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_clk_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332098): Cell: max10_qsys_inst|hyper_ram|hyperram_io_pads|hram_rwds_ddio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio from: muxsel to: dataout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332146): Worst-case setup slack is 0.117 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.117 0.000 hram_rwds_clk Info (332119): 0.441 0.000 hram_clk Info (332119): 2.540 0.000 clk_100m Info (332119): 4.233 0.000 clk_100m_p90 Info (332119): 5.886 0.000 clk_50m Info (332119): 6.015 0.000 n/a Info (332119): 7.627 0.000 nqspi_sclk Info (332119): 7.967 0.000 egrs_spi_clk Info (332119): 8.246 0.000 fpga_avst_clk Info (332119): 8.834 0.000 m10_clk_100m Info (332119): 9.783 0.000 ingrs_spi_clk Info (332119): 15.759 0.000 fpga_qspi_clk Info (332119): 16.969 0.000 flash_se_neg_reg Info (332119): 25.624 0.000 clk_25m Info (332146): Worst-case hold slack is 0.102 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.102 0.000 clk_50m Info (332119): 0.119 0.000 fpga_qspi_clk Info (332119): 0.140 0.000 ingrs_spi_clk Info (332119): 0.140 0.000 m10_clk_100m Info (332119): 0.144 0.000 clk_25m Info (332119): 0.157 0.000 hram_rwds_clk Info (332119): 0.179 0.000 clk_100m Info (332119): 0.630 0.000 flash_se_neg_reg Info (332119): 0.680 0.000 fpga_avst_clk Info (332119): 0.726 0.000 egrs_spi_clk Info (332119): 0.905 0.000 hram_clk Info (332119): 1.436 0.000 n/a Info (332119): 2.129 0.000 clk_100m_p90 Info (332119): 4.297 0.000 nqspi_sclk Info (332146): Worst-case recovery slack is 7.019 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 7.019 0.000 clk_100m Info (332119): 7.117 0.000 clk_100m_p90 Info (332119): 7.600 0.000 clk_50m Info (332119): 8.263 0.000 hram_rwds_clk Info (332119): 10.247 0.000 ingrs_spi_clk Info (332119): 17.652 0.000 fpga_qspi_clk Info (332119): 37.518 0.000 clk_25m Info (332146): Worst-case removal slack is 0.433 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.433 0.000 clk_50m Info (332119): 0.721 0.000 clk_100m Info (332119): 0.888 0.000 ingrs_spi_clk Info (332119): 0.920 0.000 hram_rwds_clk Info (332119): 1.271 0.000 fpga_qspi_clk Info (332119): 1.723 0.000 clk_25m Info (332119): 2.611 0.000 clk_100m_p90 Info (332146): Worst-case minimum pulse width slack is 3.532 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.532 0.000 m10_clk_100m Info (332119): 4.593 0.000 hram_rwds_clk Info (332119): 4.728 0.000 clk_100m Info (332119): 4.743 0.000 clk_100m_p90 Info (332119): 6.667 0.000 hram_clk Info (332119): 7.958 0.000 clk_50m Info (332119): 16.000 0.000 fpga_avst_clk Info (332119): 17.964 0.000 flash_se_neg_reg Info (332119): 19.712 0.000 fpga_qspi_clk Info (332119): 19.721 0.000 clk_25m Info (332119): 19.750 0.000 ingrs_spi_clk Info (332119): 19.963 0.000 nqspi_sclk_int Info (332119): 19.973 0.000 egrs_spi_clk_int Info (332119): 36.000 0.000 egrs_spi_clk Info (332119): 36.667 0.000 nqspi_sclk Info (332119): 44.904 0.000 clk_10m Info (332119): 90.690 0.000 max10_qsys_inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc Info (332114): Report Metastability: Found 81 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 81 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.296 Info (332114): Worst Case Available Settling Time: 17.273 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.9 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 Info (332101): Design is fully constrained for setup requirements Info (332101): Design is fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 13 warnings Info: Peak virtual memory: 1274 megabytes Info: Processing ended: Wed Apr 3 14:13:07 2024 Info: Elapsed time: 00:00:22 Info: Total CPU time (on all processors): 00:01:12 ....................BEGIN CRITICAL warnings (if any)........................................... ....................END CRITICAL warnings (if any)............................................. 2024-04-03 14:13:07 :: Timing OK 2024-04-03 14:13:07 :: Generating programming file... Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 14:13:08 2024 Info: Command: quartus_asm acadp_bmc_max10 --rev=acadp_bmc_max10_retail Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 814 megabytes Info: Processing ended: Wed Apr 3 14:13:13 2024 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 2024-04-03 14:13:13 :: - done 2024-04-03 14:13:13 :: Archiving project... Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 14:13:13 2024 Info: Command: quartus_sh --archive -output output_files_retail/acadp_bmc_max10_retail -include_output acadp_bmc_max10.qpf Info: Quartus(args): -qar -output output_files_retail/acadp_bmc_max10_retail -include_output acadp_bmc_max10.qpf Info: qar.tcl version #1 Info: File Set 'Compilation database and output' contains: Info: Project source and settings files Info: Automatically detected source files Info: Report files Info: Programming output files Info: Version-incompatible compilation database files Info: Incremental compilation and Rapid Recompile database files (version-incompatible) Warning: Hierarchical Platform Designer systems and custom IP components(_hw.tcl and associated files) are not archived by the Quartus Archiver Info: Archive will store files relative to the closest common parent directory Info (13213): Using common directory /home/admin/otc/ofs-bmc/ Info: ---------------------------------------------------------- Info: ---------------------------------------------------------- Info: Generated archive 'output_files_retail/acadp_bmc_max10_retail.qar' Info: ---------------------------------------------------------- Info: ---------------------------------------------------------- Info: Generated report 'acadp_bmc_max10_retail.archive.rpt' Info (23030): Evaluation of Tcl script /home/admin/intelFPGA/23.1std/quartus/common/tcl/apps/qpm/qar.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 1 warning Info: Peak virtual memory: 1010 megabytes Info: Processing ended: Wed Apr 3 14:13:19 2024 Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:05 2024-04-03 14:13:19 :: - done 2024-04-03 14:13:19 :: copy: output_files_factory/acadp_bmc_max10_factory.sof -> AC_BMC_RTL_factory_retail_3.15.0.sof 2024-04-03 14:13:19 :: copy: output_files_retail/acadp_bmc_max10_retail.sof -> AC_BMC_RTL_user_retail_3.15.0.sof ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 14:13:19 :: generate .pof files ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: 2024-04-03 14:13:19 :: Generating output files... Info: ******************************************************************* Info: Running Quartus Prime Convert_programming_file Info: Version 23.1std.0 Build 991 11/28/2023 SC Standard Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Apr 3 14:13:19 2024 Info: Command: quartus_cpf -c /home/admin/otc/ofs-bmc/scripts/pof_create_retail.cof Warning (18385): Programming Object File contains dual images, with different JTAG user codes 0x01F2E107 and 0x01F07F44. If you require a common JTAG user code for both images, change the JTAG user code in the General tab of the Device and Pin Options dialog box. Info (210033): Memory Map File acadp_bmc_max10_retail.map contains memory usage information for file acadp_bmc_max10_retail.pof Critical Warning (18093): Memory depth (1048576) in the Memory Initialization File "../../../fw/max10/max10_bootloader/design/bmc_bootloader/mem_init/ufm_onchip_flash.hex" is larger than the flash memory depth (65536). Truncated remaining initial content value to fit flash memory. If you do not want the remaining initial content value to be truncated, make sure the Memory Initialization File contains the same memory depth values for the flash memory. Info: Quartus Prime Convert_programming_file was successful. 0 errors, 2 warnings Info: Peak virtual memory: 358 megabytes Info: Processing ended: Wed Apr 3 14:13:20 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Started....... 0x3d340 0xa8000 0xa8080 done ! Started....... 0x3d340 0xa8000 0xa8080 done ! ~/otc/ofs-bmc/build 2024-04-03 14:13:22 :: Following output files have been generated: ............................................................................................... /home/admin/otc/ofs-bmc/build_files/rev_3.15.0/: AC_BMC_FW_factory_retail_3.15.0.bin AC_BMC_FW_user_retail_3.15.0.bin AC_BMC_Max10_bootloader_0x0B+factory_retail+user_retail_3.15.0.pof AC_BMC_RSU_user_retail_3.15.0_unsigned.rsu ............................................................................................... ~/otc/ofs-bmc/build ~/otc/ofs-bmc/build 2024-04-03 14:13:22 :: Prepare for final backup... 2024-04-03 14:13:22 :: pwd:/home/admin/otc/ofs-bmc 2024-04-03 14:13:22 :: Backup filename:backup240403-1338_3.15.0_result ~/otc/ofs-bmc/build 2024-04-03 14:13:49 :: 2024-04-03 14:13:49 :: Normal script execution ended. Total execution time until now is: 0hrs 35min 20sec 2024-04-03 14:13:49 :: 2024-04-03 14:13:49 :: This job was run on: localhost.localdomain, and the total execution time was: 0hrs 35min 20sec 2024-04-03 14:13:49 :: build.sh end :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::