ADC_test |

2018.11.08.11:30:11 | Datasheet

Overview

clk_0 | ADC_test

Processor
CPU_ADC Nios II 16.1
All Components
CPU_ADC altera_nios2_gen2 16.1
LEDs altera_avalon_pio 16.1
SW altera_avalon_pio 16.1
adc_0 altera_up_avalon_adc 16.1
jtag_uart_0 altera_avalon_jtag_uart 16.1
main_mem altera_avalon_onchip_memory2 16.1
Memory Map

| CPU_ADC
data_master | instruction_master
CPU_ADC |  |
debug_mem_slave | 0x00040800 | 0x00040800
LEDs |  |
s1 | 0x00041020 |
SW |  |
s1 | 0x00041030 |
adc_0 |  |
adc_slave | 0x00041000 |
jtag_uart_0 |  |
avalon_jtag_slave | 0x00041040 |
main_mem |  |
s1 | 0x00020000 | 0x00020000

## CPU_ADC

altera_nios2_gen2 v16.1

pll_0 | outclk0 | CPU_ADC
clk
clk_0 | clk_reset
reset
|  | data_master | adc_0
|  | adc_slave
|  | data_master | jtag_uart_0
|  | avalon_jtag_slave
|  | irq
|  | irq
|  | data_master | main_mem
|  | s1
|  | instruction_master
|  | s1
|  | data_master | SW
|  | s1
|  | data_master | LEDs
|  | s1

## Parameters
tmr_enabled | false
setting_disable_tmr_inj | false
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_preciseIllegalMemAccessException | false
setting_exportPCB | false
setting_exportdebuginfo | false
setting_clearXBitsLDNonBypass | true
setting_bigEndian | false
setting_export_large_RAMs | false
setting_asic_enabled | false
register_file_por | false
setting_asic_synopsys_translate_on_off | false
setting_asic_third_party_synthesis | false
setting_asic_add_scan_mode_input | false
setting_oci_version | 1
setting_fast_register_read | false
setting_exportHostDebugPort | false
setting_oci_export_jtag_signals | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
io_regionbase | 0
io_regionsize | 0
setting_support31bitdcachebypass | true
setting_activateTrace | false
setting_allow_break_inst | false
setting_activateTestEndChecker | false
setting_ecc_sim_test_ports | false
setting_disableocitrace | false
setting_activateMonitors | true
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
setting_breakslaveoveride | false
mpu_useLimit | false
mpu_enabled | false
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
cpuReset | false
resetrequest_enabled | true
setting_removeRAMinit | false
setting_tmr_output_disable | false
setting_shadowRegisterSets | 0
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mmu_TLBMissExcOffset | 0
resetOffset | 0
exceptionOffset | 32
cpuID | 0
breakOffset | 32
userDefinedSettings |
tracefilename |
resetSlave | main_mem.s1
mmu_TLBMissExcSlave | None
exceptionSlave | main_mem.s1
breakSlave | None
setting_interruptControllerType | Internal
setting_branchpredictiontype | Dynamic
setting_bhtPtrSz | 8
cpuArchRev | 1
stratix_dspblock_shift_mul | false
shifterType | fast_le_shift
multiplierType | mul_fast32
mul_shift_choice | 0
mul_32_impl | 2
mul_64_impl | 0
shift_rot_impl | 1
dividerType | no_div
mpu_minInstRegionSize | 12
mpu_minDataRegionSize | 12
mmu_uitlbNumEntries | 4
mmu_udtlbNumEntries | 6
mmu_tlbPtrSz | 7
mmu_tlbNumWays | 16
mmu_processIDNumBits | 8
impl | Fast
icache_size | 4096
fa_cache_line | 2
fa_cache_linesize | 0
icache_tagramBlockType | Automatic
icache_ramBlockType | Automatic
icache_numTCIM | 0
icache_burstType | None
dcache_bursts | false
dcache_victim_buf_impl | ram
dcache_size | 2048
dcache_tagramBlockType | Automatic
dcache_ramBlockType | Automatic
dcache_numTCDM | 0
setting_exportvectors | false
setting_usedesignware | false
setting_ecc_present | false
setting_ic_ecc_present | true
setting_rf_ecc_present | true
setting_mmu_ecc_present | true
setting_dc_ecc_present | true
setting_itcm_ecc_present | true
setting_dtcm_ecc_present | true
regfile_ramBlockType | Automatic
ocimem_ramBlockType | Automatic
ocimem_ramInit | false
mmu_ramBlockType | Automatic
bht_ramBlockType | Automatic
cdx_enabled | false
mpx_enabled | false
debug_enabled | true
debug_triggerArming | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_jtagInstanceID | 0
debug_OCIOnchipTrace | _128
debug_hwbreakpoint | 0
debug_datatrigger | 0
debug_traceType | none
debug_traceStorage | onchip_trace
master_addr_map | false
instruction_master_paddr_base | 0
instruction_master_paddr_size | 0
flash_instruction_master_paddr_base | 0
flash_instruction_master_paddr_size | 0
data_master_paddr_base | 0
data_master_paddr_size | 0
tightly_coupled_instruction_master_0_paddr_base | 0
tightly_coupled_instruction_master_0_paddr_size | 0
tightly_coupled_instruction_master_1_paddr_base | 0
tightly_coupled_instruction_master_1_paddr_size | 0
tightly_coupled_instruction_master_2_paddr_base | 0
tightly_coupled_instruction_master_2_paddr_size | 0
tightly_coupled_instruction_master_3_paddr_base | 0
tightly_coupled_instruction_master_3_paddr_size | 0
tightly_coupled_data_master_0_paddr_base | 0
tightly_coupled_data_master_0_paddr_size | 0
tightly_coupled_data_master_1_paddr_base | 0
tightly_coupled_data_master_1_paddr_size | 0
tightly_coupled_data_master_2_paddr_base | 0
tightly_coupled_data_master_2_paddr_size | 0
tightly_coupled_data_master_3_paddr_base | 0
tightly_coupled_data_master_3_paddr_size | 0
instruction_master_high_performance_paddr_base | 0
instruction_master_high_performance_paddr_size | 0
data_master_high_performance_paddr_base | 0
data_master_high_performance_paddr_size | 0
resetAbsoluteAddr | 131072
exceptionAbsoluteAddr | 131104
breakAbsoluteAddr | 264224
mmu_TLBMissExcAbsAddr | 0
dcache_bursts_derived | false
dcache_size_derived | 2048
breakSlave_derived | CPU_ADC.debug_mem_slave
dcache_lineSize_derived | 32
setting_ioregionBypassDCache | false
setting_bit31BypassDCache | true
translate_on | "synthesis translate_on"
translate_off | "synthesis translate_off"
debug_onchiptrace | false
debug_offchiptrace | false
debug_insttrace | false
debug_datatrace | false
instAddrWidth | 19
faAddrWidth | 1
dataAddrWidth | 19
tightlyCoupledDataMaster0AddrWidth | 1
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster3AddrWidth | 1
dataMasterHighPerformanceAddrWidth | 1
instructionMasterHighPerformanceAddrWidth | 1
instSlaveMapParam | <address-map><slave name='main_mem.s1' start='0x20000' end='0x3F400' type='altera_avalon_onchip_memory2.s1' /><slave name='CPU_ADC.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>
faSlaveMapParam |
dataSlaveMapParam | <address-map><slave name='main_mem.s1' start='0x20000' end='0x3F400' type='altera_avalon_onchip_memory2.s1' /><slave name='CPU_ADC.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='adc_0.adc_slave' start='0x41000' end='0x41020' type='altera_up_avalon_adc.adc_slave' /><slave name='LEDs.s1' start='0x41020' end='0x41030' type='altera_avalon_pio.s1' /><slave name='SW.s1' start='0x41030' end='0x41040' type='altera_avalon_pio.s1' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x41040' end='0x41048' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster3MapParam |
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster3MapParam |
dataMasterHighPerformanceMapParam |
instructionMasterHighPerformanceMapParam |
clockFrequency | 50000000
deviceFamilyName | CYCLONEV
internalIrqMaskSystemInfo | 1
customInstSlavesSystemInfo | <info/>
customInstSlavesSystemInfo_nios_a | <info/>
customInstSlavesSystemInfo_nios_b | <info/>
customInstSlavesSystemInfo_nios_c | <info/>
deviceFeaturesSystemInfo | ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
AUTO_DEVICE | 5CSEMA4U23C6
AUTO_DEVICE_SPEEDGRADE | 6
AUTO_CLK_CLOCK_DOMAIN | 3
AUTO_CLK_RESET_DOMAIN | 3
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BIG_ENDIAN | 0
BREAK_ADDR | 0x00040820
CPU_ARCH_NIOS2_R1 |
CPU_FREQ | 50000000u
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x00000000
CPU_IMPLEMENTATION | "fast"
DATA_ADDR_WIDTH | 19
DCACHE_BYPASS_MASK | 0x80000000
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
EXCEPTION_ADDR | 0x00020020
FLASH_ACCELERATOR_LINES | 0
FLASH_ACCELERATOR_LINE_SIZE | 0
FLUSHDA_SUPPORTED |
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
HAS_DEBUG_CORE | 1
HAS_DEBUG_STUB |
HAS_EXTRA_EXCEPTION_INFO |
HAS_ILLEGAL_INSTRUCTION_EXCEPTION |
HAS_JMPI_INSTRUCTION |
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
INITDA_SUPPORTED |
INST_ADDR_WIDTH | 19
NUM_OF_SHADOW_REG_SETS | 0
OCI_VERSION | 1
RESET_ADDR | 0x00020000

## LEDs

altera_avalon_pio v16.1

CPU_ADC | data_master | LEDs
s1
pll_0 | outclk0
clk
clk_0 | clk_reset
reset

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 8
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 8
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## SW

altera_avalon_pio v16.1

CPU_ADC | data_master | SW
s1
pll_0 | outclk0
clk
clk_0 | clk_reset
reset

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 4
clockRate | 50000000
derived_has_tri | false
derived_has_out | false
derived_has_in | true
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## adc_0

altera_up_avalon_adc v16.1

CPU_ADC | data_master | adc_0
adc_slave
pll_0 | outclk1
clk
clk_0 | clk_reset
reset

## Parameters
board | DE0-Nano-SoC
board_rev | Autodetect
sclk_freq | 12.5
tsclk | 1
numch_ | 8
numch | 7
AUTO_DEVICE_FAMILY | CYCLONEV
AUTO_CLK_CLOCK_RATE | 12500000
deviceFamily | Cyclone V
generateLegacySim | false

## Software Assignments (none)

## clk_0

clock_source v16.1

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## jtag_uart_0

altera_avalon_jtag_uart v16.1

CPU_ADC | data_master | jtag_uart_0
avalon_jtag_slave
irq
irq
pll_0 | outclk0
clk
clk_0 | clk_reset
reset

## Parameters
allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | NO_INTERACTIVE_WINDOWS
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
clkFreq | 50000000
avalonSpec | 2.0
legacySignalAllow | false
enableInteractiveInput | false
enableInteractiveOutput | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
READ_DEPTH | 64
READ_THRESHOLD | 8
WRITE_DEPTH | 64
WRITE_THRESHOLD | 8

## main_mem

altera_avalon_onchip_memory2 v16.1

CPU_ADC | data_master | main_mem
s1
instruction_master
s1
pll_0 | outclk0
clk1
clk_0 | clk_reset
reset1

## Parameters
allowInSystemMemoryContentEditor | false
blockType | AUTO
dataWidth | 32
dataWidth2 | 32
dualPort | false
enableDiffWidth | false
derived_enableDiffWidth | false
initMemContent | true
initializationFileName | onchip_mem.hex
enPRInitMode | false
instanceID | NONE
memorySize | 128000
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
derived_singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
copyInitFile | false
useShallowMemBlocks | false
writable | true
ecc_enabled | false
resetrequest_enabled | true
autoInitializationFileName | ADC_test_main_mem
deviceFamily | CYCLONEV
deviceFeatures | ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width | 15
derived_set_addr_width2 | 15
derived_set_data_width | 32
derived_set_data_width2 | 32
derived_gui_ram_block_type | Automatic
derived_is_hardcopy | false
derived_init_file_name | ADC_test_main_mem.hex
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | ADC_test_main_mem
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 128000
WRITABLE | 1

## pll_0

altera_pll v16.1

clk_0 | clk | pll_0
refclk
clk_reset
reset
|  | outclk0 | CPU_ADC
|  | clk
|  | outclk0 | SW
|  | clk
|  | outclk0 | LEDs
|  | clk
|  | outclk0 | jtag_uart_0
|  | clk
|  | outclk0 | main_mem
|  | clk1
|  | outclk1 | adc_0
|  | clk

## Parameters
debug_print_output | false
debug_use_rbc_taf_method | false
device_family | CYCLONEV
device | 5CSEMA4U23C6
gui_device_speed_grade | 1
gui_pll_mode | Integer-N PLL
fractional_vco_multiplier | false
gui_reference_clock_frequency | 50.0
reference_clock_frequency | 50.0 MHz
gui_channel_spacing | 0.0
gui_operation_mode | direct
gui_feedback_clock | Global Clock
gui_fractional_cout | 32
pll_fractional_cout | 32
gui_dsm_out_sel | 1st_order
pll_dsm_out_sel | 1st_order
operation_mode | direct
gui_use_locked | false
gui_en_adv_params | false
gui_number_of_clocks | 2
number_of_clocks | 2
number_of_cascade_counters | 0
gui_multiply_factor | 1
gui_frac_multiply_factor | 1
gui_divide_factor_n | 1
gui_cascade_counter0 | false
gui_output_clock_frequency0 | 50.0
gui_divide_factor_c0 | 1
gui_actual_multiply_factor0 | 6
gui_actual_frac_multiply_factor0 | 1
gui_actual_divide_factor0 | 6
gui_actual_output_clock_frequency0 | 0 MHz
gui_ps_units0 | ps
gui_phase_shift0 | 0
gui_phase_shift_deg0 | 0.0
gui_actual_phase_shift0 | 0
gui_duty_cycle0 | 50
gui_cascade_counter1 | false
gui_output_clock_frequency1 | 12.5
gui_divide_factor_c1 | 1
gui_actual_multiply_factor1 | 6
gui_actual_frac_multiply_factor1 | 1
gui_actual_divide_factor1 | 24
gui_actual_output_clock_frequency1 | 0 MHz
gui_ps_units1 | ps
gui_phase_shift1 | 0
gui_phase_shift_deg1 | 0.0
gui_actual_phase_shift1 | 0
gui_duty_cycle1 | 50
gui_cascade_counter2 | false
gui_output_clock_frequency2 | 100.0
gui_divide_factor_c2 | 1
gui_actual_multiply_factor2 | 1
gui_actual_frac_multiply_factor2 | 1
gui_actual_divide_factor2 | 1
gui_actual_output_clock_frequency2 | 0 MHz
gui_ps_units2 | ps
gui_phase_shift2 | 0
gui_phase_shift_deg2 | 0.0
gui_actual_phase_shift2 | 0
gui_duty_cycle2 | 50
gui_cascade_counter3 | false
gui_output_clock_frequency3 | 100.0
gui_divide_factor_c3 | 1
gui_actual_multiply_factor3 | 1
gui_actual_frac_multiply_factor3 | 1
gui_actual_divide_factor3 | 1
gui_actual_output_clock_frequency3 | 0 MHz
gui_ps_units3 | ps
gui_phase_shift3 | 0
gui_phase_shift_deg3 | 0.0
gui_actual_phase_shift3 | 0
gui_duty_cycle3 | 50
gui_cascade_counter4 | false
gui_output_clock_frequency4 | 100.0
gui_divide_factor_c4 | 1
gui_actual_multiply_factor4 | 1
gui_actual_frac_multiply_factor4 | 1
gui_actual_divide_factor4 | 1
gui_actual_output_clock_frequency4 | 0 MHz
gui_ps_units4 | ps
gui_phase_shift4 | 0
gui_phase_shift_deg4 | 0.0
gui_actual_phase_shift4 | 0
gui_duty_cycle4 | 50
gui_cascade_counter5 | false
gui_output_clock_frequency5 | 100.0
gui_divide_factor_c5 | 1
gui_actual_multiply_factor5 | 1
gui_actual_frac_multiply_factor5 | 1
gui_actual_divide_factor5 | 1
gui_actual_output_clock_frequency5 | 0 MHz
gui_ps_units5 | ps
gui_phase_shift5 | 0
gui_phase_shift_deg5 | 0.0
gui_actual_phase_shift5 | 0
gui_duty_cycle5 | 50
gui_cascade_counter6 | false
gui_output_clock_frequency6 | 100.0
gui_divide_factor_c6 | 1
gui_actual_multiply_factor6 | 1
gui_actual_frac_multiply_factor6 | 1
gui_actual_divide_factor6 | 1
gui_actual_output_clock_frequency6 | 0 MHz
gui_ps_units6 | ps
gui_phase_shift6 | 0
gui_phase_shift_deg6 | 0.0
gui_actual_phase_shift6 | 0
gui_duty_cycle6 | 50
gui_cascade_counter7 | false
gui_output_clock_frequency7 | 100.0
gui_divide_factor_c7 | 1
gui_actual_multiply_factor7 | 1
gui_actual_frac_multiply_factor7 | 1
gui_actual_divide_factor7 | 1
gui_actual_output_clock_frequency7 | 0 MHz
gui_ps_units7 | ps
gui_phase_shift7 | 0
gui_phase_shift_deg7 | 0.0
gui_actual_phase_shift7 | 0
gui_duty_cycle7 | 50
gui_cascade_counter8 | false
gui_output_clock_frequency8 | 100.0
gui_divide_factor_c8 | 1
gui_actual_multiply_factor8 | 1
gui_actual_frac_multiply_factor8 | 1
gui_actual_divide_factor8 | 1
gui_actual_output_clock_frequency8 | 0 MHz
gui_ps_units8 | ps
gui_phase_shift8 | 0
gui_phase_shift_deg8 | 0.0
gui_actual_phase_shift8 | 0
gui_duty_cycle8 | 50
gui_cascade_counter9 | false
gui_output_clock_frequency9 | 100.0
gui_divide_factor_c9 | 1
gui_actual_multiply_factor9 | 1
gui_actual_frac_multiply_factor9 | 1
gui_actual_divide_factor9 | 1
gui_actual_output_clock_frequency9 | 0 MHz
gui_ps_units9 | ps
gui_phase_shift9 | 0
gui_phase_shift_deg9 | 0.0
gui_actual_phase_shift9 | 0
gui_duty_cycle9 | 50
gui_cascade_counter10 | false
gui_output_clock_frequency10 | 100.0
gui_divide_factor_c10 | 1
gui_actual_multiply_factor10 | 1
gui_actual_frac_multiply_factor10 | 1
gui_actual_divide_factor10 | 1
gui_actual_output_clock_frequency10 | 0 MHz
gui_ps_units10 | ps
gui_phase_shift10 | 0
gui_phase_shift_deg10 | 0.0
gui_actual_phase_shift10 | 0
gui_duty_cycle10 | 50
gui_cascade_counter11 | false
gui_output_clock_frequency11 | 100.0
gui_divide_factor_c11 | 1
gui_actual_multiply_factor11 | 1
gui_actual_frac_multiply_factor11 | 1
gui_actual_divide_factor11 | 1
gui_actual_output_clock_frequency11 | 0 MHz
gui_ps_units11 | ps
gui_phase_shift11 | 0
gui_phase_shift_deg11 | 0.0
gui_actual_phase_shift11 | 0
gui_duty_cycle11 | 50
gui_cascade_counter12 | false
gui_output_clock_frequency12 | 100.0
gui_divide_factor_c12 | 1
gui_actual_multiply_factor12 | 1
gui_actual_frac_multiply_factor12 | 1
gui_actual_divide_factor12 | 1
gui_actual_output_clock_frequency12 | 0 MHz
gui_ps_units12 | ps
gui_phase_shift12 | 0
gui_phase_shift_deg12 | 0.0
gui_actual_phase_shift12 | 0
gui_duty_cycle12 | 50
gui_cascade_counter13 | false
gui_output_clock_frequency13 | 100.0
gui_divide_factor_c13 | 1
gui_actual_multiply_factor13 | 1
gui_actual_frac_multiply_factor13 | 1
gui_actual_divide_factor13 | 1
gui_actual_output_clock_frequency13 | 0 MHz
gui_ps_units13 | ps
gui_phase_shift13 | 0
gui_phase_shift_deg13 | 0.0
gui_actual_phase_shift13 | 0
gui_duty_cycle13 | 50
gui_cascade_counter14 | false
gui_output_clock_frequency14 | 100.0
gui_divide_factor_c14 | 1
gui_actual_multiply_factor14 | 1
gui_actual_frac_multiply_factor14 | 1
gui_actual_divide_factor14 | 1
gui_actual_output_clock_frequency14 | 0 MHz
gui_ps_units14 | ps
gui_phase_shift14 | 0
gui_phase_shift_deg14 | 0.0
gui_actual_phase_shift14 | 0
gui_duty_cycle14 | 50
gui_cascade_counter15 | false
gui_output_clock_frequency15 | 100.0
gui_divide_factor_c15 | 1
gui_actual_multiply_factor15 | 1
gui_actual_frac_multiply_factor15 | 1
gui_actual_divide_factor15 | 1
gui_actual_output_clock_frequency15 | 0 MHz
gui_ps_units15 | ps
gui_phase_shift15 | 0
gui_phase_shift_deg15 | 0.0
gui_actual_phase_shift15 | 0
gui_duty_cycle15 | 50
gui_cascade_counter16 | false
gui_output_clock_frequency16 | 100.0
gui_divide_factor_c16 | 1
gui_actual_multiply_factor16 | 1
gui_actual_frac_multiply_factor16 | 1
gui_actual_divide_factor16 | 1
gui_actual_output_clock_frequency16 | 0 MHz
gui_ps_units16 | ps
gui_phase_shift16 | 0
gui_phase_shift_deg16 | 0.0
gui_actual_phase_shift16 | 0
gui_duty_cycle16 | 50
gui_cascade_counter17 | false
gui_output_clock_frequency17 | 100.0
gui_divide_factor_c17 | 1
gui_actual_multiply_factor17 | 1
gui_actual_frac_multiply_factor17 | 1
gui_actual_divide_factor17 | 1
gui_actual_output_clock_frequency17 | 0 MHz
gui_ps_units17 | ps
gui_phase_shift17 | 0
gui_phase_shift_deg17 | 0.0
gui_actual_phase_shift17 | 0
gui_duty_cycle17 | 50
output_clock_frequency0 | 50.000000 MHz
phase_shift0 | 0 ps
duty_cycle0 | 50
output_clock_frequency1 | 12.500000 MHz
phase_shift1 | 0 ps
duty_cycle1 | 50
output_clock_frequency2 | 0 MHz
phase_shift2 | 0 ps
duty_cycle2 | 50
output_clock_frequency3 | 0 MHz
phase_shift3 | 0 ps
duty_cycle3 | 50
output_clock_frequency4 | 0 MHz
phase_shift4 | 0 ps
duty_cycle4 | 50
output_clock_frequency5 | 0 MHz
phase_shift5 | 0 ps
duty_cycle5 | 50
output_clock_frequency6 | 0 MHz
phase_shift6 | 0 ps
duty_cycle6 | 50
output_clock_frequency7 | 0 MHz
phase_shift7 | 0 ps
duty_cycle7 | 50
output_clock_frequency8 | 0 MHz
phase_shift8 | 0 ps
duty_cycle8 | 50
output_clock_frequency9 | 0 MHz
phase_shift9 | 0 ps
duty_cycle9 | 50
output_clock_frequency10 | 0 MHz
phase_shift10 | 0 ps
duty_cycle10 | 50
output_clock_frequency11 | 0 MHz
phase_shift11 | 0 ps
duty_cycle11 | 50
output_clock_frequency12 | 0 MHz
phase_shift12 | 0 ps
duty_cycle12 | 50
output_clock_frequency13 | 0 MHz
phase_shift13 | 0 ps
duty_cycle13 | 50
output_clock_frequency14 | 0 MHz
phase_shift14 | 0 ps
duty_cycle14 | 50
output_clock_frequency15 | 0 MHz
phase_shift15 | 0 ps
duty_cycle15 | 50
output_clock_frequency16 | 0 MHz
phase_shift16 | 0 ps
duty_cycle16 | 50
output_clock_frequency17 | 0 MHz
phase_shift17 | 0 ps
duty_cycle17 | 50
gui_pll_auto_reset | Off
gui_pll_bandwidth_preset | Auto
gui_en_reconf | false
gui_en_dps_ports | false
gui_en_phout_ports | false
gui_phout_division | 1
pll_vcoph_div | 1
pll_type | General
pll_subtype | General
m_cnt_hi_div | 3
m_cnt_lo_div | 3
n_cnt_hi_div | 256
n_cnt_lo_div | 256
m_cnt_bypass_en | false
n_cnt_bypass_en | true
m_cnt_odd_div_duty_en | false
n_cnt_odd_div_duty_en | false
c_cnt_hi_div0 | 3
c_cnt_lo_div0 | 3
c_cnt_prst0 | 1
c_cnt_ph_mux_prst0 | 0
c_cnt_in_src0 | ph_mux_clk
c_cnt_bypass_en0 | false
c_cnt_odd_div_duty_en0 | false
c_cnt_hi_div1 | 12
c_cnt_lo_div1 | 12
c_cnt_prst1 | 1
c_cnt_ph_mux_prst1 | 0
c_cnt_in_src1 | ph_mux_clk
c_cnt_bypass_en1 | false
c_cnt_odd_div_duty_en1 | false
c_cnt_hi_div2 | 1
c_cnt_lo_div2 | 1
c_cnt_prst2 | 1
c_cnt_ph_mux_prst2 | 0
c_cnt_in_src2 | ph_mux_clk
c_cnt_bypass_en2 | true
c_cnt_odd_div_duty_en2 | false
c_cnt_hi_div3 | 1
c_cnt_lo_div3 | 1
c_cnt_prst3 | 1
c_cnt_ph_mux_prst3 | 0
c_cnt_in_src3 | ph_mux_clk
c_cnt_bypass_en3 | true
c_cnt_odd_div_duty_en3 | false
c_cnt_hi_div4 | 1
c_cnt_lo_div4 | 1
c_cnt_prst4 | 1
c_cnt_ph_mux_prst4 | 0
c_cnt_in_src4 | ph_mux_clk
c_cnt_bypass_en4 | true
c_cnt_odd_div_duty_en4 | false
c_cnt_hi_div5 | 1
c_cnt_lo_div5 | 1
c_cnt_prst5 | 1
c_cnt_ph_mux_prst5 | 0
c_cnt_in_src5 | ph_mux_clk
c_cnt_bypass_en5 | true
c_cnt_odd_div_duty_en5 | false
c_cnt_hi_div6 | 1
c_cnt_lo_div6 | 1
c_cnt_prst6 | 1
c_cnt_ph_mux_prst6 | 0
c_cnt_in_src6 | ph_mux_clk
c_cnt_bypass_en6 | true
c_cnt_odd_div_duty_en6 | false
c_cnt_hi_div7 | 1
c_cnt_lo_div7 | 1
c_cnt_prst7 | 1
c_cnt_ph_mux_prst7 | 0
c_cnt_in_src7 | ph_mux_clk
c_cnt_bypass_en7 | true
c_cnt_odd_div_duty_en7 | false
c_cnt_hi_div8 | 1
c_cnt_lo_div8 | 1
c_cnt_prst8 | 1
c_cnt_ph_mux_prst8 | 0
c_cnt_in_src8 | ph_mux_clk
c_cnt_bypass_en8 | true
c_cnt_odd_div_duty_en8 | false
c_cnt_hi_div9 | 1
c_cnt_lo_div9 | 1
c_cnt_prst9 | 1
c_cnt_ph_mux_prst9 | 0
c_cnt_in_src9 | ph_mux_clk
c_cnt_bypass_en9 | true
c_cnt_odd_div_duty_en9 | false
c_cnt_hi_div10 | 1
c_cnt_lo_div10 | 1
c_cnt_prst10 | 1
c_cnt_ph_mux_prst10 | 0
c_cnt_in_src10 | ph_mux_clk
c_cnt_bypass_en10 | true
c_cnt_odd_div_duty_en10 | false
c_cnt_hi_div11 | 1
c_cnt_lo_div11 | 1
c_cnt_prst11 | 1
c_cnt_ph_mux_prst11 | 0
c_cnt_in_src11 | ph_mux_clk
c_cnt_bypass_en11 | true
c_cnt_odd_div_duty_en11 | false
c_cnt_hi_div12 | 1
c_cnt_lo_div12 | 1
c_cnt_prst12 | 1
c_cnt_ph_mux_prst12 | 0
c_cnt_in_src12 | ph_mux_clk
c_cnt_bypass_en12 | true
c_cnt_odd_div_duty_en12 | false
c_cnt_hi_div13 | 1
c_cnt_lo_div13 | 1
c_cnt_prst13 | 1
c_cnt_ph_mux_prst13 | 0
c_cnt_in_src13 | ph_mux_clk
c_cnt_bypass_en13 | true
c_cnt_odd_div_duty_en13 | false
c_cnt_hi_div14 | 1
c_cnt_lo_div14 | 1
c_cnt_prst14 | 1
c_cnt_ph_mux_prst14 | 0
c_cnt_in_src14 | ph_mux_clk
c_cnt_bypass_en14 | true
c_cnt_odd_div_duty_en14 | false
c_cnt_hi_div15 | 1
c_cnt_lo_div15 | 1
c_cnt_prst15 | 1
c_cnt_ph_mux_prst15 | 0
c_cnt_in_src15 | ph_mux_clk
c_cnt_bypass_en15 | true
c_cnt_odd_div_duty_en15 | false
c_cnt_hi_div16 | 1
c_cnt_lo_div16 | 1
c_cnt_prst16 | 1
c_cnt_ph_mux_prst16 | 0
c_cnt_in_src16 | ph_mux_clk
c_cnt_bypass_en16 | true
c_cnt_odd_div_duty_en16 | false
c_cnt_hi_div17 | 1
c_cnt_lo_div17 | 1
c_cnt_prst17 | 1
c_cnt_ph_mux_prst17 | 0
c_cnt_in_src17 | ph_mux_clk
c_cnt_bypass_en17 | true
c_cnt_odd_div_duty_en17 | false
pll_vco_div | 2
pll_cp_current | 30
pll_bwctrl | 2000
pll_output_clk_frequency | 300.0 MHz
pll_fractional_division | 1
mimic_fbclk_type | none
pll_fbclk_mux_1 | glb
pll_fbclk_mux_2 | m_cnt
pll_m_cnt_in_src | ph_mux_clk
pll_slf_rst | false
gui_parameter_list | M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset
gui_parameter_values | 3,3,256,256,false,true,false,false,3,3,1,0,ph_mux_clk,false,false,12,12,1,0,ph_mux_clk,false,false,2,30,2000,300.0 MHz,1,none,glb,m_cnt,ph_mux_clk,false
gui_mif_generate | false
gui_enable_mif_dps | false
gui_dps_cntr | C0
gui_dps_num | 1
gui_dps_dir | Positive
gui_refclk_switch | false
gui_refclk1_frequency | 100.0
gui_switchover_mode | Automatic Switchover
gui_switchover_delay | 0
gui_active_clk | false
gui_clk_bad | false
refclk1_frequency | 100.0 MHz
pll_clk_loss_sw_en | false
pll_manu_clk_sw_en | false
pll_auto_clk_sw_en | false
pll_clkin_1_src | clk_0
pll_clk_sw_dly | 0
gui_enable_cascade_out | false
gui_cascade_outclk_index | 0
gui_enable_cascade_in | false
pll_clkin_0_src | clk_0
gui_pll_cascading_mode | Create an adjpllin signal to connect with an upstream PLL
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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