
State Machine - |DE0_NANO_SOC_Default|ADC_test:u0|ADC_test_adc_0:adc_0|altera_up_avalon_adv_adc:ADC_CTRL|currState
Name currState.pauseStateNoAddrIncr currState.initCtrlRegState currState.pauseState currState.doneState currState.transState currState.waitState currState.resetState 
currState.resetState 0 0 0 0 0 0 0 
currState.waitState 0 0 0 0 0 1 1 
currState.transState 0 0 0 0 1 0 1 
currState.doneState 0 0 0 1 0 0 1 
currState.pauseState 0 0 1 0 0 0 1 
currState.initCtrlRegState 0 1 0 0 0 0 1 
currState.pauseStateNoAddrIncr 1 0 0 0 0 0 1 

State Machine - |DE0_NANO_SOC_Default|ADC_test:u0|ADC_test_CPU_ADC:cpu_adc|ADC_test_CPU_ADC_cpu:cpu|ADC_test_CPU_ADC_cpu_nios2_oci:the_ADC_test_CPU_ADC_cpu_nios2_oci|ADC_test_CPU_ADC_cpu_debug_slave_wrapper:the_ADC_test_CPU_ADC_cpu_debug_slave_wrapper|ADC_test_CPU_ADC_cpu_debug_slave_tck:the_ADC_test_CPU_ADC_cpu_debug_slave_tck|DRsize
Name DRsize.101 DRsize.100 DRsize.011 DRsize.010 DRsize.001 DRsize.000 
DRsize.000 0 0 0 0 0 0 
DRsize.001 0 0 0 0 1 1 
DRsize.010 0 0 0 1 0 1 
DRsize.011 0 0 1 0 0 1 
DRsize.100 0 1 0 0 0 1 
DRsize.101 1 0 0 0 0 1 
