Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition Info: Processing started: Mon May 30 11:50:57 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off standard -c standard Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected Info (12021): Found 1 design units, including 1 entities, in source file standard.sv Info (12023): Found entity 1: standard Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/nios2.v Info (12023): Found entity 1: Nios2 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_irq_mapper.sv Info (12023): Found entity 1: Nios2_irq_mapper Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0.v Info (12023): Found entity 1: Nios2_mm_interconnect_0 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004.v Info (12023): Found entity 1: Nios2_mm_interconnect_0_avalon_st_adapter_004 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter.v Info (12023): Found entity 1: Nios2_mm_interconnect_0_avalon_st_adapter Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_width_adapter.sv Info (12023): Found entity 1: altera_merlin_width_adapter Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator Info (12023): Found entity 2: altera_merlin_arb_adder Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_rsp_mux Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_demux_001.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_rsp_demux_001 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_rsp_demux.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_rsp_demux Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux_001.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_cmd_mux_001 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_cmd_mux Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_cmd_demux Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_burst_adapter.sv Info (12023): Found entity 1: altera_merlin_burst_adapter Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only Info (12021): Found 5 design units, including 5 entities, in source file nios2/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment Info (12023): Found entity 2: altera_merlin_burst_adapter_adder Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor Info (12023): Found entity 4: altera_merlin_burst_adapter_min Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_burst_adapter_new.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_new Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_incr_burst_converter.sv Info (12023): Found entity 1: altera_incr_burst_converter Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_wrap_burst_converter.sv Info (12023): Found entity 1: altera_wrap_burst_converter Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_default_burst_converter.sv Info (12023): Found entity 1: altera_default_burst_converter Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_traffic_limiter.sv Info (12023): Found entity 1: altera_merlin_traffic_limiter Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/altera_merlin_reorder_memory.sv Info (12023): Found entity 1: altera_merlin_reorder_memory Info (12023): Found entity 2: memory_pointer_controller Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_router_007.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_router_007_default_decode Info (12023): Found entity 2: Nios2_mm_interconnect_0_router_007 Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_router_006.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_router_006_default_decode Info (12023): Found entity 2: Nios2_mm_interconnect_0_router_006 Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_router_003.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_router_003_default_decode Info (12023): Found entity 2: Nios2_mm_interconnect_0_router_003 Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_router_002.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_router_002_default_decode Info (12023): Found entity 2: Nios2_mm_interconnect_0_router_002 Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_router_001_default_decode Info (12023): Found entity 2: Nios2_mm_interconnect_0_router_001 Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/nios2_mm_interconnect_0_router.sv Info (12023): Found entity 1: Nios2_mm_interconnect_0_router_default_decode Info (12023): Found entity 2: Nios2_mm_interconnect_0_router Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator Info (12021): Found 5 design units, including 5 entities, in source file nios2/synthesis/submodules/nios2_uart_0.v Info (12023): Found entity 1: Nios2_uart_0_tx Info (12023): Found entity 2: Nios2_uart_0_rx_stimulus_source Info (12023): Found entity 3: Nios2_uart_0_rx Info (12023): Found entity 4: Nios2_uart_0_regs Info (12023): Found entity 5: Nios2_uart_0 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_tristate_conduit_bridge_0.sv Info (12023): Found entity 1: Nios2_tristate_conduit_bridge_0 Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/nios2_sdram_0.v Info (12023): Found entity 1: Nios2_sdram_0_input_efifo_module Info (12023): Found entity 2: Nios2_sdram_0 Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/nios2_sdram_0_test_component.v Info (12023): Found entity 1: Nios2_sdram_0_test_component_ram_module Info (12023): Found entity 2: Nios2_sdram_0_test_component Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_onchip_memory2_0.v Info (12023): Found entity 1: Nios2_onchip_memory2_0 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_nios2_qsys_0.v Info (12023): Found entity 1: Nios2_nios2_qsys_0 Info (12021): Found 27 design units, including 27 entities, in source file nios2/synthesis/submodules/nios2_nios2_qsys_0_cpu.v Info (12023): Found entity 1: Nios2_nios2_qsys_0_cpu_ic_data_module Info (12023): Found entity 2: Nios2_nios2_qsys_0_cpu_ic_tag_module Info (12023): Found entity 3: Nios2_nios2_qsys_0_cpu_bht_module Info (12023): Found entity 4: Nios2_nios2_qsys_0_cpu_register_bank_a_module Info (12023): Found entity 5: Nios2_nios2_qsys_0_cpu_register_bank_b_module Info (12023): Found entity 6: Nios2_nios2_qsys_0_cpu_dc_tag_module Info (12023): Found entity 7: Nios2_nios2_qsys_0_cpu_dc_data_module Info (12023): Found entity 8: Nios2_nios2_qsys_0_cpu_dc_victim_module Info (12023): Found entity 9: Nios2_nios2_qsys_0_cpu_nios2_oci_debug Info (12023): Found entity 10: Nios2_nios2_qsys_0_cpu_nios2_oci_break Info (12023): Found entity 11: Nios2_nios2_qsys_0_cpu_nios2_oci_xbrk Info (12023): Found entity 12: Nios2_nios2_qsys_0_cpu_nios2_oci_dbrk Info (12023): Found entity 13: Nios2_nios2_qsys_0_cpu_nios2_oci_itrace Info (12023): Found entity 14: Nios2_nios2_qsys_0_cpu_nios2_oci_td_mode Info (12023): Found entity 15: Nios2_nios2_qsys_0_cpu_nios2_oci_dtrace Info (12023): Found entity 16: Nios2_nios2_qsys_0_cpu_nios2_oci_compute_input_tm_cnt Info (12023): Found entity 17: Nios2_nios2_qsys_0_cpu_nios2_oci_fifo_wrptr_inc Info (12023): Found entity 18: Nios2_nios2_qsys_0_cpu_nios2_oci_fifo_cnt_inc Info (12023): Found entity 19: Nios2_nios2_qsys_0_cpu_nios2_oci_fifo Info (12023): Found entity 20: Nios2_nios2_qsys_0_cpu_nios2_oci_pib Info (12023): Found entity 21: Nios2_nios2_qsys_0_cpu_nios2_oci_im Info (12023): Found entity 22: Nios2_nios2_qsys_0_cpu_nios2_performance_monitors Info (12023): Found entity 23: Nios2_nios2_qsys_0_cpu_nios2_avalon_reg Info (12023): Found entity 24: Nios2_nios2_qsys_0_cpu_ociram_sp_ram_module Info (12023): Found entity 25: Nios2_nios2_qsys_0_cpu_nios2_ocimem Info (12023): Found entity 26: Nios2_nios2_qsys_0_cpu_nios2_oci Info (12023): Found entity 27: Nios2_nios2_qsys_0_cpu Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_nios2_qsys_0_cpu_debug_slave_sysclk.v Info (12023): Found entity 1: Nios2_nios2_qsys_0_cpu_debug_slave_sysclk Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_nios2_qsys_0_cpu_debug_slave_tck.v Info (12023): Found entity 1: Nios2_nios2_qsys_0_cpu_debug_slave_tck Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_nios2_qsys_0_cpu_debug_slave_wrapper.v Info (12023): Found entity 1: Nios2_nios2_qsys_0_cpu_debug_slave_wrapper Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_nios2_qsys_0_cpu_mult_cell.v Info (12023): Found entity 1: Nios2_nios2_qsys_0_cpu_mult_cell Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_nios2_qsys_0_cpu_test_bench.v Info (12023): Found entity 1: Nios2_nios2_qsys_0_cpu_test_bench Info (12021): Found 5 design units, including 5 entities, in source file nios2/synthesis/submodules/nios2_jtag_uart_0.v Info (12023): Found entity 1: Nios2_jtag_uart_0_sim_scfifo_w Info (12023): Found entity 2: Nios2_jtag_uart_0_scfifo_w Info (12023): Found entity 3: Nios2_jtag_uart_0_sim_scfifo_r Info (12023): Found entity 4: Nios2_jtag_uart_0_scfifo_r Info (12023): Found entity 5: Nios2_jtag_uart_0 Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_flash_bus_pin_sharer_0.v Info (12023): Found entity 1: Nios2_flash_bus_pin_sharer_0 Info (12021): Found 2 design units, including 2 entities, in source file nios2/synthesis/submodules/altera_merlin_std_arbitrator_core.sv Info (12023): Found entity 1: altera_merlin_std_arbitrator_core Info (12023): Found entity 2: altera_merlin_std_arb_adder Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_flash_bus_pin_sharer_0_arbiter.sv Info (12023): Found entity 1: Nios2_flash_bus_pin_sharer_0_arbiter Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_flash_bus_pin_sharer_0_pin_sharer.sv Info (12023): Found entity 1: Nios2_flash_bus_pin_sharer_0_pin_sharer Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/nios2_flash.v Info (12023): Found entity 1: Nios2_flash Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_tristate_controller_aggregator.sv Info (12023): Found entity 1: altera_tristate_controller_aggregator Info (12021): Found 1 design units, including 1 entities, in source file nios2/synthesis/submodules/altera_tristate_controller_translator.sv Info (12023): Found entity 1: altera_tristate_controller_translator Info (12021): Found 1 design units, including 1 entities, in source file pll.v Info (12023): Found entity 1: pll Warning (10236): Verilog HDL Implicit Net warning at standard.sv(52): created implicit net for "sysclk" Warning (10037): Verilog HDL or VHDL warning at Nios2_sdram_0.v(316): conditional expression evaluates to a constant Warning (10037): Verilog HDL or VHDL warning at Nios2_sdram_0.v(326): conditional expression evaluates to a constant Warning (10037): Verilog HDL or VHDL warning at Nios2_sdram_0.v(336): conditional expression evaluates to a constant Warning (10037): Verilog HDL or VHDL warning at Nios2_sdram_0.v(680): conditional expression evaluates to a constant Info (12127): Elaborating entity "standard" for the top level hierarchy Info (12128): Elaborating entity "pll" for hierarchy "pll:pll_inst" Info (12128): Elaborating entity "altpll" for hierarchy "pll:pll_inst|altpll:altpll_component" Info (12130): Elaborated megafunction instantiation "pll:pll_inst|altpll:altpll_component" Info (12133): Instantiated megafunction "pll:pll_inst|altpll:altpll_component" with the following parameter: Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "6" Info (12134): Parameter "clk0_duty_cycle" = "50" Info (12134): Parameter "clk0_multiply_by" = "25" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "clk1_divide_by" = "6" Info (12134): Parameter "clk1_duty_cycle" = "50" Info (12134): Parameter "clk1_multiply_by" = "25" Info (12134): Parameter "clk1_phase_shift" = "0" Info (12134): Parameter "compensate_clock" = "CLK1" Info (12134): Parameter "inclk0_input_frequency" = "41666" Info (12134): Parameter "intended_device_family" = "Cyclone IV E" Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NORMAL" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" Info (12134): Parameter "port_areset" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" Info (12134): Parameter "port_fbin" = "PORT_UNUSED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" Info (12134): Parameter "port_locked" = "PORT_UNUSED" Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" Info (12134): Parameter "port_pllena" = "PORT_UNUSED" Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" Info (12134): Parameter "port_scandata" = "PORT_UNUSED" Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" Info (12134): Parameter "port_scandone" = "PORT_UNUSED" Info (12134): Parameter "port_scanread" = "PORT_UNUSED" Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_USED" Info (12134): Parameter "port_clk2" = "PORT_UNUSED" Info (12134): Parameter "port_clk3" = "PORT_UNUSED" Info (12134): Parameter "port_clk4" = "PORT_UNUSED" Info (12134): Parameter "port_clk5" = "PORT_UNUSED" Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" Info (12134): Parameter "width_clock" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/pll_altpll.v Info (12023): Found entity 1: pll_altpll Info (12128): Elaborating entity "pll_altpll" for hierarchy "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated" Info (12128): Elaborating entity "Nios2" for hierarchy "Nios2:Nios2_inst" Info (12128): Elaborating entity "Nios2_flash" for hierarchy "Nios2:Nios2_inst|Nios2_flash:flash" Info (12128): Elaborating entity "altera_tristate_controller_translator" for hierarchy "Nios2:Nios2_inst|Nios2_flash:flash|altera_tristate_controller_translator:tdt" Warning (10230): Verilog HDL assignment warning at altera_tristate_controller_translator.sv(127): truncated value with size 32 to match size of target (2) Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "Nios2:Nios2_inst|Nios2_flash:flash|altera_merlin_slave_translator:slave_translator" Info (12128): Elaborating entity "altera_tristate_controller_aggregator" for hierarchy "Nios2:Nios2_inst|Nios2_flash:flash|altera_tristate_controller_aggregator:tda" Info (12128): Elaborating entity "Nios2_flash_bus_pin_sharer_0" for hierarchy "Nios2:Nios2_inst|Nios2_flash_bus_pin_sharer_0:flash_bus_pin_sharer_0" Info (12128): Elaborating entity "Nios2_flash_bus_pin_sharer_0_pin_sharer" for hierarchy "Nios2:Nios2_inst|Nios2_flash_bus_pin_sharer_0:flash_bus_pin_sharer_0|Nios2_flash_bus_pin_sharer_0_pin_sharer:pin_sharer" Warning (10230): Verilog HDL assignment warning at Nios2_flash_bus_pin_sharer_0_pin_sharer.sv(80): truncated value with size 32 to match size of target (1) Info (12128): Elaborating entity "Nios2_flash_bus_pin_sharer_0_arbiter" for hierarchy "Nios2:Nios2_inst|Nios2_flash_bus_pin_sharer_0:flash_bus_pin_sharer_0|Nios2_flash_bus_pin_sharer_0_arbiter:arbiter" Info (12128): Elaborating entity "altera_merlin_std_arbitrator_core" for hierarchy "Nios2:Nios2_inst|Nios2_flash_bus_pin_sharer_0:flash_bus_pin_sharer_0|Nios2_flash_bus_pin_sharer_0_arbiter:arbiter|altera_merlin_std_arbitrator_core:arb" Info (12128): Elaborating entity "altera_merlin_std_arb_adder" for hierarchy "Nios2:Nios2_inst|Nios2_flash_bus_pin_sharer_0:flash_bus_pin_sharer_0|Nios2_flash_bus_pin_sharer_0_arbiter:arbiter|altera_merlin_std_arbitrator_core:arb|altera_merlin_std_arb_adder:adder" Info (12128): Elaborating entity "Nios2_jtag_uart_0" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0" Info (12128): Elaborating entity "Nios2_jtag_uart_0_scfifo_w" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w" Info (12128): Elaborating entity "scfifo" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo" with the following parameter: Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO" Info (12134): Parameter "lpm_numwords" = "64" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "8" Info (12134): Parameter "lpm_widthu" = "6" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "OFF" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf Info (12023): Found entity 1: scfifo_jr21 Info (12128): Elaborating entity "scfifo_jr21" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated" Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_l011.tdf Info (12023): Found entity 1: a_dpfifo_l011 Info (12128): Elaborating entity "a_dpfifo_l011" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_l011:dpfifo" Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf Info (12023): Found entity 1: a_fefifo_7cf Info (12128): Elaborating entity "a_fefifo_7cf" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_l011:dpfifo|a_fefifo_7cf:fifo_state" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf Info (12023): Found entity 1: cntr_do7 Info (12128): Elaborating entity "cntr_do7" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_l011:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nio1.tdf Info (12023): Found entity 1: altsyncram_nio1 Info (12128): Elaborating entity "altsyncram_nio1" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_l011:dpfifo|altsyncram_nio1:FIFOram" Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf Info (12023): Found entity 1: cntr_1ob Info (12128): Elaborating entity "cntr_1ob" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_w:the_Nios2_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_l011:dpfifo|cntr_1ob:rd_ptr_count" Info (12128): Elaborating entity "Nios2_jtag_uart_0_scfifo_r" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|Nios2_jtag_uart_0_scfifo_r:the_Nios2_jtag_uart_0_scfifo_r" Info (12128): Elaborating entity "alt_jtag_atlantic" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic" with the following parameter: Info (12134): Parameter "INSTANCE_ID" = "0" Info (12134): Parameter "LOG2_RXFIFO_DEPTH" = "6" Info (12134): Parameter "LOG2_TXFIFO_DEPTH" = "6" Info (12134): Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES" Info (12128): Elaborating entity "altera_sld_agent_endpoint" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic|altera_sld_agent_endpoint:inst" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic|altera_sld_agent_endpoint:inst", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic" Info (12128): Elaborating entity "altera_fabric_endpoint" for hierarchy "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic|altera_sld_agent_endpoint:inst|altera_fabric_endpoint:ep" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic|altera_sld_agent_endpoint:inst|altera_fabric_endpoint:ep", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:Nios2_jtag_uart_0_alt_jtag_atlantic" Info (12128): Elaborating entity "Nios2_nios2_qsys_0" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_test_bench" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_test_bench:the_Nios2_nios2_qsys_0_cpu_test_bench" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_ic_data_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_data_module:Nios2_nios2_qsys_0_cpu_ic_data" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_data_module:Nios2_nios2_qsys_0_cpu_ic_data|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_data_module:Nios2_nios2_qsys_0_cpu_ic_data|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_data_module:Nios2_nios2_qsys_0_cpu_ic_data|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "1024" Info (12134): Parameter "numwords_b" = "1024" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "10" Info (12134): Parameter "widthad_b" = "10" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_cjd1.tdf Info (12023): Found entity 1: altsyncram_cjd1 Info (12128): Elaborating entity "altsyncram_cjd1" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_data_module:Nios2_nios2_qsys_0_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_cjd1:auto_generated" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_ic_tag_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_tag_module:Nios2_nios2_qsys_0_cpu_ic_tag" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_tag_module:Nios2_nios2_qsys_0_cpu_ic_tag|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_tag_module:Nios2_nios2_qsys_0_cpu_ic_tag|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_tag_module:Nios2_nios2_qsys_0_cpu_ic_tag|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "128" Info (12134): Parameter "numwords_b" = "128" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "24" Info (12134): Parameter "width_b" = "24" Info (12134): Parameter "widthad_a" = "7" Info (12134): Parameter "widthad_b" = "7" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bad1.tdf Info (12023): Found entity 1: altsyncram_bad1 Info (12128): Elaborating entity "altsyncram_bad1" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_ic_tag_module:Nios2_nios2_qsys_0_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_bad1:auto_generated" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_bht_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_bht_module:Nios2_nios2_qsys_0_cpu_bht" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_bht_module:Nios2_nios2_qsys_0_cpu_bht|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_bht_module:Nios2_nios2_qsys_0_cpu_bht|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_bht_module:Nios2_nios2_qsys_0_cpu_bht|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "numwords_b" = "256" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "2" Info (12134): Parameter "width_b" = "2" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "widthad_b" = "8" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_97d1.tdf Info (12023): Found entity 1: altsyncram_97d1 Info (12128): Elaborating entity "altsyncram_97d1" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_bht_module:Nios2_nios2_qsys_0_cpu_bht|altsyncram:the_altsyncram|altsyncram_97d1:auto_generated" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_register_bank_a_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_register_bank_a_module:Nios2_nios2_qsys_0_cpu_register_bank_a" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_register_bank_a_module:Nios2_nios2_qsys_0_cpu_register_bank_a|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_register_bank_a_module:Nios2_nios2_qsys_0_cpu_register_bank_a|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_register_bank_a_module:Nios2_nios2_qsys_0_cpu_register_bank_a|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "32" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "5" Info (12134): Parameter "widthad_b" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fic1.tdf Info (12023): Found entity 1: altsyncram_fic1 Info (12128): Elaborating entity "altsyncram_fic1" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_register_bank_a_module:Nios2_nios2_qsys_0_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fic1:auto_generated" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_register_bank_b_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_register_bank_b_module:Nios2_nios2_qsys_0_cpu_register_bank_b" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_mult_cell" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell" Info (12128): Elaborating entity "altera_mult_add" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1" with the following parameter: Info (12134): Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0" Info (12134): Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0" Info (12134): Parameter "addnsub_multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "dedicated_multiplier_circuitry" = "YES" Info (12134): Parameter "input_register_a0" = "UNREGISTERED" Info (12134): Parameter "input_register_b0" = "UNREGISTERED" Info (12134): Parameter "input_source_a0" = "DATAA" Info (12134): Parameter "input_source_b0" = "DATAB" Info (12134): Parameter "lpm_type" = "altera_mult_add" Info (12134): Parameter "multiplier1_direction" = "ADD" Info (12134): Parameter "multiplier_aclr0" = "ACLR0" Info (12134): Parameter "multiplier_register0" = "CLOCK0" Info (12134): Parameter "number_of_multipliers" = "1" Info (12134): Parameter "output_register" = "UNREGISTERED" Info (12134): Parameter "port_addnsub1" = "PORT_UNUSED" Info (12134): Parameter "port_addnsub3" = "PORT_UNUSED" Info (12134): Parameter "representation_a" = "UNSIGNED" Info (12134): Parameter "representation_b" = "UNSIGNED" Info (12134): Parameter "selected_device_family" = "CYCLONEIVE" Info (12134): Parameter "signed_pipeline_aclr_a" = "ACLR0" Info (12134): Parameter "signed_pipeline_aclr_b" = "ACLR0" Info (12134): Parameter "signed_pipeline_register_a" = "CLOCK0" Info (12134): Parameter "signed_pipeline_register_b" = "CLOCK0" Info (12134): Parameter "signed_register_a" = "UNREGISTERED" Info (12134): Parameter "signed_register_b" = "UNREGISTERED" Info (12134): Parameter "width_a" = "16" Info (12134): Parameter "width_b" = "16" Info (12134): Parameter "width_result" = "32" Info (12021): Found 1 design units, including 1 entities, in source file db/altera_mult_add_vkp2.v Info (12023): Found entity 1: altera_mult_add_vkp2 Info (12128): Elaborating entity "altera_mult_add_vkp2" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated" Info (12128): Elaborating entity "altera_mult_add_rtl" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" with the following parameter: Info (12134): Parameter "accum_direction" = "ADD" Info (12134): Parameter "accum_sload_aclr" = "NONE" Info (12134): Parameter "accum_sload_latency_aclr" = "NONE" Info (12134): Parameter "accum_sload_latency_clock" = "UNREGISTERED" Info (12134): Parameter "accum_sload_register" = "UNREGISTERED" Info (12134): Parameter "accumulator" = "NO" Info (12134): Parameter "adder1_rounding" = "NO" Info (12134): Parameter "adder3_rounding" = "NO" Info (12134): Parameter "addnsub1_round_aclr" = "NONE" Info (12134): Parameter "addnsub1_round_pipeline_aclr" = "NONE" Info (12134): Parameter "addnsub1_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "addnsub1_round_register" = "UNREGISTERED" Info (12134): Parameter "addnsub3_round_aclr" = "NONE" Info (12134): Parameter "addnsub3_round_pipeline_aclr" = "NONE" Info (12134): Parameter "addnsub3_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "addnsub3_round_register" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_aclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_aclr3" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_aclr1" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_aclr3" = "NONE" Info (12134): Parameter "addnsub_multiplier_latency_clock1" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_latency_clock3" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "addnsub_multiplier_register3" = "UNREGISTERED" Info (12134): Parameter "chainout_aclr" = "NONE" Info (12134): Parameter "chainout_adder" = "NO" Info (12134): Parameter "chainout_adder_direction" = "ADD" Info (12134): Parameter "chainout_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_aclr" = "NONE" Info (12134): Parameter "chainout_round_output_aclr" = "NONE" Info (12134): Parameter "chainout_round_output_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_pipeline_aclr" = "NONE" Info (12134): Parameter "chainout_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "chainout_round_register" = "UNREGISTERED" Info (12134): Parameter "chainout_rounding" = "NO" Info (12134): Parameter "chainout_saturate_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_output_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_output_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturate_pipeline_aclr" = "NONE" Info (12134): Parameter "chainout_saturate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturate_register" = "UNREGISTERED" Info (12134): Parameter "chainout_saturation" = "NO" Info (12134): Parameter "coef0_0" = "0" Info (12134): Parameter "coef0_1" = "0" Info (12134): Parameter "coef0_2" = "0" Info (12134): Parameter "coef0_3" = "0" Info (12134): Parameter "coef0_4" = "0" Info (12134): Parameter "coef0_5" = "0" Info (12134): Parameter "coef0_6" = "0" Info (12134): Parameter "coef0_7" = "0" Info (12134): Parameter "coef1_0" = "0" Info (12134): Parameter "coef1_1" = "0" Info (12134): Parameter "coef1_2" = "0" Info (12134): Parameter "coef1_3" = "0" Info (12134): Parameter "coef1_4" = "0" Info (12134): Parameter "coef1_5" = "0" Info (12134): Parameter "coef1_6" = "0" Info (12134): Parameter "coef1_7" = "0" Info (12134): Parameter "coef2_0" = "0" Info (12134): Parameter "coef2_1" = "0" Info (12134): Parameter "coef2_2" = "0" Info (12134): Parameter "coef2_3" = "0" Info (12134): Parameter "coef2_4" = "0" Info (12134): Parameter "coef2_5" = "0" Info (12134): Parameter "coef2_6" = "0" Info (12134): Parameter "coef2_7" = "0" Info (12134): Parameter "coef3_0" = "0" Info (12134): Parameter "coef3_1" = "0" Info (12134): Parameter "coef3_2" = "0" Info (12134): Parameter "coef3_3" = "0" Info (12134): Parameter "coef3_4" = "0" Info (12134): Parameter "coef3_5" = "0" Info (12134): Parameter "coef3_6" = "0" Info (12134): Parameter "coef3_7" = "0" Info (12134): Parameter "coefsel0_aclr" = "NONE" Info (12134): Parameter "coefsel0_latency_aclr" = "NONE" Info (12134): Parameter "coefsel0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel0_register" = "UNREGISTERED" Info (12134): Parameter "coefsel1_aclr" = "NONE" Info (12134): Parameter "coefsel1_latency_aclr" = "NONE" Info (12134): Parameter "coefsel1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel1_register" = "UNREGISTERED" Info (12134): Parameter "coefsel2_aclr" = "NONE" Info (12134): Parameter "coefsel2_latency_aclr" = "NONE" Info (12134): Parameter "coefsel2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel2_register" = "UNREGISTERED" Info (12134): Parameter "coefsel3_aclr" = "NONE" Info (12134): Parameter "coefsel3_latency_aclr" = "NONE" Info (12134): Parameter "coefsel3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "coefsel3_register" = "UNREGISTERED" Info (12134): Parameter "dedicated_multiplier_circuitry" = "YES" Info (12134): Parameter "double_accum" = "NO" Info (12134): Parameter "dsp_block_balancing" = "Auto" Info (12134): Parameter "extra_latency" = "0" Info (12134): Parameter "input_a0_latency_aclr" = "NONE" Info (12134): Parameter "input_a0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a1_latency_aclr" = "NONE" Info (12134): Parameter "input_a1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a2_latency_aclr" = "NONE" Info (12134): Parameter "input_a2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_a3_latency_aclr" = "NONE" Info (12134): Parameter "input_a3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_aclr_a0" = "NONE" Info (12134): Parameter "input_aclr_a1" = "NONE" Info (12134): Parameter "input_aclr_a2" = "NONE" Info (12134): Parameter "input_aclr_a3" = "NONE" Info (12134): Parameter "input_aclr_b0" = "NONE" Info (12134): Parameter "input_aclr_b1" = "NONE" Info (12134): Parameter "input_aclr_b2" = "NONE" Info (12134): Parameter "input_aclr_b3" = "NONE" Info (12134): Parameter "input_aclr_c0" = "NONE" Info (12134): Parameter "input_aclr_c1" = "NONE" Info (12134): Parameter "input_aclr_c2" = "NONE" Info (12134): Parameter "input_aclr_c3" = "NONE" Info (12134): Parameter "input_b0_latency_aclr" = "NONE" Info (12134): Parameter "input_b0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b1_latency_aclr" = "NONE" Info (12134): Parameter "input_b1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b2_latency_aclr" = "NONE" Info (12134): Parameter "input_b2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_b3_latency_aclr" = "NONE" Info (12134): Parameter "input_b3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c0_latency_aclr" = "NONE" Info (12134): Parameter "input_c0_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c1_latency_aclr" = "NONE" Info (12134): Parameter "input_c1_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c2_latency_aclr" = "NONE" Info (12134): Parameter "input_c2_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_c3_latency_aclr" = "NONE" Info (12134): Parameter "input_c3_latency_clock" = "UNREGISTERED" Info (12134): Parameter "input_register_a0" = "UNREGISTERED" Info (12134): Parameter "input_register_a1" = "UNREGISTERED" Info (12134): Parameter "input_register_a2" = "UNREGISTERED" Info (12134): Parameter "input_register_a3" = "UNREGISTERED" Info (12134): Parameter "input_register_b0" = "UNREGISTERED" Info (12134): Parameter "input_register_b1" = "UNREGISTERED" Info (12134): Parameter "input_register_b2" = "UNREGISTERED" Info (12134): Parameter "input_register_b3" = "UNREGISTERED" Info (12134): Parameter "input_register_c0" = "UNREGISTERED" Info (12134): Parameter "input_register_c1" = "UNREGISTERED" Info (12134): Parameter "input_register_c2" = "UNREGISTERED" Info (12134): Parameter "input_register_c3" = "UNREGISTERED" Info (12134): Parameter "input_source_a0" = "DATAA" Info (12134): Parameter "input_source_a1" = "DATAA" Info (12134): Parameter "input_source_a2" = "DATAA" Info (12134): Parameter "input_source_a3" = "DATAA" Info (12134): Parameter "input_source_b0" = "DATAB" Info (12134): Parameter "input_source_b1" = "DATAB" Info (12134): Parameter "input_source_b2" = "DATAB" Info (12134): Parameter "input_source_b3" = "DATAB" Info (12134): Parameter "latency" = "0" Info (12134): Parameter "loadconst_control_aclr" = "NONE" Info (12134): Parameter "loadconst_control_register" = "UNREGISTERED" Info (12134): Parameter "loadconst_value" = "64" Info (12134): Parameter "mult01_round_aclr" = "NONE" Info (12134): Parameter "mult01_round_register" = "UNREGISTERED" Info (12134): Parameter "mult01_saturation_aclr" = "ACLR0" Info (12134): Parameter "mult01_saturation_register" = "UNREGISTERED" Info (12134): Parameter "mult23_round_aclr" = "NONE" Info (12134): Parameter "mult23_round_register" = "UNREGISTERED" Info (12134): Parameter "mult23_saturation_aclr" = "NONE" Info (12134): Parameter "mult23_saturation_register" = "UNREGISTERED" Info (12134): Parameter "multiplier01_rounding" = "NO" Info (12134): Parameter "multiplier01_saturation" = "NO" Info (12134): Parameter "multiplier1_direction" = "ADD" Info (12134): Parameter "multiplier23_rounding" = "NO" Info (12134): Parameter "multiplier23_saturation" = "NO" Info (12134): Parameter "multiplier3_direction" = "ADD" Info (12134): Parameter "multiplier_aclr0" = "ACLR0" Info (12134): Parameter "multiplier_aclr1" = "NONE" Info (12134): Parameter "multiplier_aclr2" = "NONE" Info (12134): Parameter "multiplier_aclr3" = "NONE" Info (12134): Parameter "multiplier_register0" = "CLOCK0" Info (12134): Parameter "multiplier_register1" = "UNREGISTERED" Info (12134): Parameter "multiplier_register2" = "UNREGISTERED" Info (12134): Parameter "multiplier_register3" = "UNREGISTERED" Info (12134): Parameter "negate_aclr" = "NONE" Info (12134): Parameter "negate_latency_aclr" = "NONE" Info (12134): Parameter "negate_latency_clock" = "UNREGISTERED" Info (12134): Parameter "negate_register" = "UNREGISTERED" Info (12134): Parameter "number_of_multipliers" = "1" Info (12134): Parameter "output_aclr" = "NONE" Info (12134): Parameter "output_register" = "UNREGISTERED" Info (12134): Parameter "output_round_aclr" = "NONE" Info (12134): Parameter "output_round_pipeline_aclr" = "NONE" Info (12134): Parameter "output_round_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "output_round_register" = "UNREGISTERED" Info (12134): Parameter "output_round_type" = "NEAREST_INTEGER" Info (12134): Parameter "output_rounding" = "NO" Info (12134): Parameter "output_saturate_aclr" = "NONE" Info (12134): Parameter "output_saturate_pipeline_aclr" = "NONE" Info (12134): Parameter "output_saturate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "output_saturate_register" = "UNREGISTERED" Info (12134): Parameter "output_saturate_type" = "ASYMMETRIC" Info (12134): Parameter "output_saturation" = "NO" Info (12134): Parameter "port_addnsub1" = "PORT_UNUSED" Info (12134): Parameter "port_addnsub3" = "PORT_UNUSED" Info (12134): Parameter "port_chainout_sat_is_overflow" = "PORT_UNUSED" Info (12134): Parameter "port_negate" = "PORT_UNUSED" Info (12134): Parameter "port_output_is_overflow" = "PORT_UNUSED" Info (12134): Parameter "port_signa" = "PORT_UNUSED" Info (12134): Parameter "port_signb" = "PORT_UNUSED" Info (12134): Parameter "preadder_direction_0" = "ADD" Info (12134): Parameter "preadder_direction_1" = "ADD" Info (12134): Parameter "preadder_direction_2" = "ADD" Info (12134): Parameter "preadder_direction_3" = "ADD" Info (12134): Parameter "preadder_mode" = "SIMPLE" Info (12134): Parameter "representation_a" = "UNSIGNED" Info (12134): Parameter "representation_b" = "UNSIGNED" Info (12134): Parameter "rotate_aclr" = "NONE" Info (12134): Parameter "rotate_output_aclr" = "NONE" Info (12134): Parameter "rotate_output_register" = "UNREGISTERED" Info (12134): Parameter "rotate_pipeline_aclr" = "NONE" Info (12134): Parameter "rotate_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "rotate_register" = "UNREGISTERED" Info (12134): Parameter "scanouta_aclr" = "NONE" Info (12134): Parameter "scanouta_register" = "UNREGISTERED" Info (12134): Parameter "selected_device_family" = "Cyclone IV E" Info (12134): Parameter "shift_mode" = "NO" Info (12134): Parameter "shift_right_aclr" = "NONE" Info (12134): Parameter "shift_right_output_aclr" = "NONE" Info (12134): Parameter "shift_right_output_register" = "UNREGISTERED" Info (12134): Parameter "shift_right_pipeline_aclr" = "NONE" Info (12134): Parameter "shift_right_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "shift_right_register" = "UNREGISTERED" Info (12134): Parameter "signed_aclr_a" = "NONE" Info (12134): Parameter "signed_aclr_b" = "NONE" Info (12134): Parameter "signed_latency_aclr_a" = "NONE" Info (12134): Parameter "signed_latency_aclr_b" = "NONE" Info (12134): Parameter "signed_latency_clock_a" = "UNREGISTERED" Info (12134): Parameter "signed_latency_clock_b" = "UNREGISTERED" Info (12134): Parameter "signed_register_a" = "UNREGISTERED" Info (12134): Parameter "signed_register_b" = "UNREGISTERED" Info (12134): Parameter "systolic_aclr1" = "NONE" Info (12134): Parameter "systolic_aclr3" = "NONE" Info (12134): Parameter "systolic_delay1" = "UNREGISTERED" Info (12134): Parameter "systolic_delay3" = "UNREGISTERED" Info (12134): Parameter "use_sload_accum_port" = "NO" Info (12134): Parameter "use_subnadd" = "NO" Info (12134): Parameter "width_a" = "16" Info (12134): Parameter "width_b" = "16" Info (12134): Parameter "width_c" = "22" Info (12134): Parameter "width_chainin" = "1" Info (12134): Parameter "width_coef" = "18" Info (12134): Parameter "width_msb" = "17" Info (12134): Parameter "width_result" = "32" Info (12134): Parameter "width_saturate_sign" = "1" Info (12134): Parameter "zero_chainout_output_aclr" = "NONE" Info (12134): Parameter "zero_chainout_output_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_aclr" = "NONE" Info (12134): Parameter "zero_loopback_output_aclr" = "NONE" Info (12134): Parameter "zero_loopback_output_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_pipeline_aclr" = "NONE" Info (12134): Parameter "zero_loopback_pipeline_register" = "UNREGISTERED" Info (12134): Parameter "zero_loopback_register" = "UNREGISTERED" Info (12134): Parameter "lpm_type" = "altera_mult_add_rtl" Info (12128): Elaborating entity "ama_register_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:signa_reg_block" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:signa_reg_block", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_data_split_reg_ext_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_register_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_register_function:data_register_block_0" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_register_function:data_register_block_0", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_dynamic_signed_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_dynamic_signed_function:data0_signed_extension_block" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:dataa_split|ama_dynamic_signed_function:data0_signed_extension_block", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_data_split_reg_ext_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_register_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_register_function:data_register_block_0" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_register_function:data_register_block_0", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_dynamic_signed_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_dynamic_signed_function:data0_signed_extension_block" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_data_split_reg_ext_function:datac_split|ama_dynamic_signed_function:data0_signed_extension_block", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_preadder_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_adder_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:first_adder_ext_block_0" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:first_adder_ext_block_0", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:second_adder_ext_block_0" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_preadder_function:preadder_block|ama_adder_function:preadder_adder_0|ama_signed_extension_function:second_adder_ext_block_0", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_multiplier_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_register_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_0", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_register_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_1" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|ama_register_function:multiplier_register_block_1", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_adder_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:first_adder_ext_block_0" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:first_adder_ext_block_0", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_signed_extension_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:second_adder_ext_block_0" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_adder_function:final_adder_block|ama_signed_extension_function:second_adder_ext_block_0", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "ama_register_function" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:output_reg_block" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_register_function:output_reg_block", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_dc_tag_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_tag_module:Nios2_nios2_qsys_0_cpu_dc_tag" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_tag_module:Nios2_nios2_qsys_0_cpu_dc_tag|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_tag_module:Nios2_nios2_qsys_0_cpu_dc_tag|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_tag_module:Nios2_nios2_qsys_0_cpu_dc_tag|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "64" Info (12134): Parameter "numwords_b" = "64" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "19" Info (12134): Parameter "width_b" = "19" Info (12134): Parameter "widthad_a" = "6" Info (12134): Parameter "widthad_b" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5jc1.tdf Info (12023): Found entity 1: altsyncram_5jc1 Info (12128): Elaborating entity "altsyncram_5jc1" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_tag_module:Nios2_nios2_qsys_0_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_5jc1:auto_generated" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_dc_data_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_data_module:Nios2_nios2_qsys_0_cpu_dc_data" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_data_module:Nios2_nios2_qsys_0_cpu_dc_data|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_data_module:Nios2_nios2_qsys_0_cpu_dc_data|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_data_module:Nios2_nios2_qsys_0_cpu_dc_data|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "512" Info (12134): Parameter "numwords_b" = "512" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "9" Info (12134): Parameter "widthad_b" = "9" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_kdf1.tdf Info (12023): Found entity 1: altsyncram_kdf1 Info (12128): Elaborating entity "altsyncram_kdf1" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_data_module:Nios2_nios2_qsys_0_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_kdf1:auto_generated" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_dc_victim_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_victim_module:Nios2_nios2_qsys_0_cpu_dc_victim" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_victim_module:Nios2_nios2_qsys_0_cpu_dc_victim|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_victim_module:Nios2_nios2_qsys_0_cpu_dc_victim|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_victim_module:Nios2_nios2_qsys_0_cpu_dc_victim|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "8" Info (12134): Parameter "numwords_b" = "8" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "3" Info (12134): Parameter "widthad_b" = "3" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r3d1.tdf Info (12023): Found entity 1: altsyncram_r3d1 Info (12128): Elaborating entity "altsyncram_r3d1" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_dc_victim_module:Nios2_nios2_qsys_0_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_debug" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_debug:the_Nios2_nios2_qsys_0_cpu_nios2_oci_debug" Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_debug:the_Nios2_nios2_qsys_0_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_debug:the_Nios2_nios2_qsys_0_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_debug:the_Nios2_nios2_qsys_0_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: Info (12134): Parameter "depth" = "2" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_break" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_break:the_Nios2_nios2_qsys_0_cpu_nios2_oci_break" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_xbrk" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_xbrk:the_Nios2_nios2_qsys_0_cpu_nios2_oci_xbrk" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_dbrk" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_dbrk:the_Nios2_nios2_qsys_0_cpu_nios2_oci_dbrk" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_itrace" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_itrace:the_Nios2_nios2_qsys_0_cpu_nios2_oci_itrace" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_dtrace" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_dtrace:the_Nios2_nios2_qsys_0_cpu_nios2_oci_dtrace" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_td_mode" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_dtrace:the_Nios2_nios2_qsys_0_cpu_nios2_oci_dtrace|Nios2_nios2_qsys_0_cpu_nios2_oci_td_mode:Nios2_nios2_qsys_0_cpu_nios2_oci_trc_ctrl_td_mode" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_fifo" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_fifo:the_Nios2_nios2_qsys_0_cpu_nios2_oci_fifo" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_compute_input_tm_cnt" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_fifo:the_Nios2_nios2_qsys_0_cpu_nios2_oci_fifo|Nios2_nios2_qsys_0_cpu_nios2_oci_compute_input_tm_cnt:the_Nios2_nios2_qsys_0_cpu_nios2_oci_compute_input_tm_cnt" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_fifo_wrptr_inc" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_fifo:the_Nios2_nios2_qsys_0_cpu_nios2_oci_fifo|Nios2_nios2_qsys_0_cpu_nios2_oci_fifo_wrptr_inc:the_Nios2_nios2_qsys_0_cpu_nios2_oci_fifo_wrptr_inc" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_fifo_cnt_inc" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_fifo:the_Nios2_nios2_qsys_0_cpu_nios2_oci_fifo|Nios2_nios2_qsys_0_cpu_nios2_oci_fifo_cnt_inc:the_Nios2_nios2_qsys_0_cpu_nios2_oci_fifo_cnt_inc" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_pib" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_pib:the_Nios2_nios2_qsys_0_cpu_nios2_oci_pib" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_oci_im" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_im:the_Nios2_nios2_qsys_0_cpu_nios2_oci_im" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_avalon_reg" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_avalon_reg:the_Nios2_nios2_qsys_0_cpu_nios2_avalon_reg" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_nios2_ocimem" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_ocimem:the_Nios2_nios2_qsys_0_cpu_nios2_ocimem" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_ociram_sp_ram_module" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_ocimem:the_Nios2_nios2_qsys_0_cpu_nios2_ocimem|Nios2_nios2_qsys_0_cpu_ociram_sp_ram_module:Nios2_nios2_qsys_0_cpu_ociram_sp_ram" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_ocimem:the_Nios2_nios2_qsys_0_cpu_nios2_ocimem|Nios2_nios2_qsys_0_cpu_ociram_sp_ram_module:Nios2_nios2_qsys_0_cpu_ociram_sp_ram|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_ocimem:the_Nios2_nios2_qsys_0_cpu_nios2_ocimem|Nios2_nios2_qsys_0_cpu_ociram_sp_ram_module:Nios2_nios2_qsys_0_cpu_ociram_sp_ram|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_ocimem:the_Nios2_nios2_qsys_0_cpu_nios2_ocimem|Nios2_nios2_qsys_0_cpu_ociram_sp_ram_module:Nios2_nios2_qsys_0_cpu_ociram_sp_ram|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "init_file" = "UNUSED" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "8" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4a31.tdf Info (12023): Found entity 1: altsyncram_4a31 Info (12128): Elaborating entity "altsyncram_4a31" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_ocimem:the_Nios2_nios2_qsys_0_cpu_nios2_ocimem|Nios2_nios2_qsys_0_cpu_ociram_sp_ram_module:Nios2_nios2_qsys_0_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4a31:auto_generated" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_debug_slave_wrapper" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_debug_slave_tck" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|Nios2_nios2_qsys_0_cpu_debug_slave_tck:the_Nios2_nios2_qsys_0_cpu_debug_slave_tck" Info (12128): Elaborating entity "Nios2_nios2_qsys_0_cpu_debug_slave_sysclk" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|Nios2_nios2_qsys_0_cpu_debug_slave_sysclk:the_Nios2_nios2_qsys_0_cpu_debug_slave_sysclk" Info (12128): Elaborating entity "sld_virtual_jtag_basic" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:Nios2_nios2_qsys_0_cpu_debug_slave_phy" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:Nios2_nios2_qsys_0_cpu_debug_slave_phy" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:Nios2_nios2_qsys_0_cpu_debug_slave_phy" with the following parameter: Info (12134): Parameter "sld_auto_instance_index" = "YES" Info (12134): Parameter "sld_instance_index" = "0" Info (12134): Parameter "sld_ir_width" = "2" Info (12134): Parameter "sld_mfg_id" = "70" Info (12134): Parameter "sld_sim_action" = "" Info (12134): Parameter "sld_sim_n_scan" = "0" Info (12134): Parameter "sld_sim_total_length" = "0" Info (12134): Parameter "sld_type_id" = "34" Info (12134): Parameter "sld_version" = "3" Info (12128): Elaborating entity "sld_virtual_jtag_impl" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:Nios2_nios2_qsys_0_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" Info (12131): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:Nios2_nios2_qsys_0_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:Nios2_nios2_qsys_0_cpu_debug_slave_phy" Info (12128): Elaborating entity "sld_jtag_endpoint_adapter" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:Nios2_nios2_qsys_0_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst|sld_jtag_endpoint_adapter:jtag_signal_adapter" Info (12128): Elaborating entity "sld_jtag_endpoint_adapter_impl" for hierarchy "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_debug_slave_wrapper:the_Nios2_nios2_qsys_0_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:Nios2_nios2_qsys_0_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst|sld_jtag_endpoint_adapter:jtag_signal_adapter|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst" Info (12128): Elaborating entity "Nios2_onchip_memory2_0" for hierarchy "Nios2:Nios2_inst|Nios2_onchip_memory2_0:onchip_memory2_0" Info (12128): Elaborating entity "altsyncram" for hierarchy "Nios2:Nios2_inst|Nios2_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram" with the following parameter: Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "init_file" = "Nios2_onchip_memory2_0.hex" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "2049" Info (12134): Parameter "numwords_a" = "2049" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "12" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_tqc1.tdf Info (12023): Found entity 1: altsyncram_tqc1 Info (12128): Elaborating entity "altsyncram_tqc1" for hierarchy "Nios2:Nios2_inst|Nios2_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_tqc1:auto_generated" Info (12128): Elaborating entity "Nios2_sdram_0" for hierarchy "Nios2:Nios2_inst|Nios2_sdram_0:sdram_0" Info (12128): Elaborating entity "Nios2_sdram_0_input_efifo_module" for hierarchy "Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|Nios2_sdram_0_input_efifo_module:the_Nios2_sdram_0_input_efifo_module" Info (12128): Elaborating entity "Nios2_tristate_conduit_bridge_0" for hierarchy "Nios2:Nios2_inst|Nios2_tristate_conduit_bridge_0:tristate_conduit_bridge_0" Info (12128): Elaborating entity "Nios2_uart_0" for hierarchy "Nios2:Nios2_inst|Nios2_uart_0:uart_0" Info (12128): Elaborating entity "Nios2_uart_0_tx" for hierarchy "Nios2:Nios2_inst|Nios2_uart_0:uart_0|Nios2_uart_0_tx:the_Nios2_uart_0_tx" Info (12128): Elaborating entity "Nios2_uart_0_rx" for hierarchy "Nios2:Nios2_inst|Nios2_uart_0:uart_0|Nios2_uart_0_rx:the_Nios2_uart_0_rx" Info (12128): Elaborating entity "Nios2_uart_0_rx_stimulus_source" for hierarchy "Nios2:Nios2_inst|Nios2_uart_0:uart_0|Nios2_uart_0_rx:the_Nios2_uart_0_rx|Nios2_uart_0_rx_stimulus_source:the_Nios2_uart_0_rx_stimulus_source" Info (12128): Elaborating entity "Nios2_uart_0_regs" for hierarchy "Nios2:Nios2_inst|Nios2_uart_0:uart_0|Nios2_uart_0_regs:the_Nios2_uart_0_regs" Info (12128): Elaborating entity "Nios2_mm_interconnect_0" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0" Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_qsys_0_data_master_translator" Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:nios2_qsys_0_instruction_master_translator" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:nios2_qsys_0_debug_mem_slave_translator" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sdram_0_s1_translator" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:onchip_memory2_0_s1_translator" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:flash_uas_translator" Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:uart_0_s1_translator" Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_qsys_0_data_master_agent" Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:nios2_qsys_0_instruction_master_agent" Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent" Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_agent|altera_merlin_burst_uncompressor:uncompressor" Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo" Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:sdram_0_s1_agent_rsp_fifo" Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:flash_uas_agent" Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:flash_uas_agent|altera_merlin_burst_uncompressor:uncompressor" Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:flash_uas_agent_rsp_fifo" Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:flash_uas_agent_rdata_fifo" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router:router" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_default_decode" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router:router|Nios2_mm_interconnect_0_router_default_decode:the_default_decode" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_001" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_001:router_001" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_001_default_decode" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_001:router_001|Nios2_mm_interconnect_0_router_001_default_decode:the_default_decode" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_002" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_002:router_002" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_002_default_decode" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_002:router_002|Nios2_mm_interconnect_0_router_002_default_decode:the_default_decode" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_003" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_003:router_003" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_003_default_decode" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_003:router_003|Nios2_mm_interconnect_0_router_003_default_decode:the_default_decode" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_006" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_006:router_006" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_006_default_decode" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_006:router_006|Nios2_mm_interconnect_0_router_006_default_decode:the_default_decode" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_007" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_007:router_007" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_router_007_default_decode" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_router_007:router_007|Nios2_mm_interconnect_0_router_007_default_decode:the_default_decode" Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:nios2_qsys_0_data_master_limiter" Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:flash_uas_burst_adapter" Info (12128): Elaborating entity "altera_merlin_burst_adapter_uncompressed_only" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:flash_uas_burst_adapter|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.burst_adapter" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_cmd_demux" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_cmd_demux:cmd_demux" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_cmd_mux" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_cmd_mux:cmd_mux" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_cmd_mux_001" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_cmd_mux_001:cmd_mux_001" Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb" Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_rsp_demux" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_rsp_demux:rsp_demux" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_rsp_demux_001" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_rsp_demux_001:rsp_demux_001" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_rsp_mux" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_rsp_mux:rsp_mux" Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:flash_uas_rsp_width_adapter" Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:flash_uas_cmd_width_adapter" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_avalon_st_adapter" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|Nios2_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_avalon_st_adapter_004" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_avalon_st_adapter_004:avalon_st_adapter_004" Info (12128): Elaborating entity "Nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0" for hierarchy "Nios2:Nios2_inst|Nios2_mm_interconnect_0:mm_interconnect_0|Nios2_mm_interconnect_0_avalon_st_adapter_004:avalon_st_adapter_004|Nios2_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0:error_adapter_0" Info (12128): Elaborating entity "Nios2_irq_mapper" for hierarchy "Nios2:Nios2_inst|Nios2_irq_mapper:irq_mapper" Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "Nios2:Nios2_inst|altera_reset_controller:rst_controller" Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "Nios2:Nios2_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "Nios2:Nios2_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "Nios2:Nios2_inst|altera_reset_controller:rst_controller_001" Warning (12020): Port "jdo" on the entity instantiation of "the_Nios2_nios2_qsys_0_cpu_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored. Info (11170): Start IP generation for the debug fabric within sld_hub. Info (11172): 2022.05.30.11:51:13 Progress: Loading sld0232097d/alt_sld_fab_wrapper_hw.tcl Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab" Info (11172): Presplit: "alt_sld_fab" instantiated altera_super_splitter "presplit" Info (11172): Splitter: "alt_sld_fab" instantiated altera_sld_splitter "splitter" Info (11172): Sldfabric: "alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric" Info (11172): Ident: "alt_sld_fab" instantiated altera_connection_identification_hub "ident" Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 6 files Info (11171): Finished IP generation for the debug fabric within sld_hub. Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0232097d/alt_sld_fab.v Info (12023): Found entity 1: alt_sld_fab Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0232097d/submodules/alt_sld_fab_alt_sld_fab.v Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0232097d/submodules/alt_sld_fab_alt_sld_fab_ident.sv Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0232097d/submodules/alt_sld_fab_alt_sld_fab_presplit.sv Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sld0232097d/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld0232097d/submodules/alt_sld_fab_alt_sld_fab_splitter.sv Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter Info (278001): Inferred 4 megafunctions from design logic Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Add9" Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p3|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|Mult0" Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|lpm_add_sub:Add9" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|lpm_add_sub:Add9" with the following parameter: Info (12134): Parameter "LPM_WIDTH" = "33" Info (12134): Parameter "LPM_DIRECTION" = "DEFAULT" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "NO" Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf Info (12023): Found entity 1: add_sub_qvi Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p1|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" with the following parameter: Info (12134): Parameter "LPM_WIDTHA" = "17" Info (12134): Parameter "LPM_WIDTHB" = "17" Info (12134): Parameter "LPM_WIDTHP" = "34" Info (12134): Parameter "LPM_WIDTHR" = "34" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_kp01.tdf Info (12023): Found entity 1: mult_kp01 Info (12130): Elaborated megafunction instantiation "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" Info (12133): Instantiated megafunction "Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_mult_cell:the_Nios2_nios2_qsys_0_cpu_mult_cell|altera_mult_add:the_altmult_add_p2|altera_mult_add_vkp2:auto_generated|altera_mult_add_rtl:altera_mult_add_rtl1|ama_multiplier_function:multiplier_block|lpm_mult:Mult0" with the following parameter: Info (12134): Parameter "LPM_WIDTHA" = "16" Info (12134): Parameter "LPM_WIDTHB" = "16" Info (12134): Parameter "LPM_WIDTHP" = "32" Info (12134): Parameter "LPM_WIDTHR" = "32" Info (12134): Parameter "LPM_WIDTHS" = "1" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" Info (12134): Parameter "MAXIMIZE_SPEED" = "6" Info (12021): Found 1 design units, including 1 entities, in source file db/mult_j011.tdf Info (12023): Found entity 1: mult_j011 Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "speed" technology mapper which leaves 36 WYSIWYG logic cells and I/Os untouched Info (13000): Registers with preset signals will power-up high Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Info (13086): Performing gate-level register retiming Info (13093): Not allowed to move 255 registers Info (13094): Not allowed to move at least 2 registers because they are in a sequence of registers directly fed by input pins Info (13095): Not allowed to move at least 90 registers because they feed output pins directly Info (13098): Not allowed to move at least 47 registers because they are fed by registers in a different clock domain Info (13099): Not allowed to move at least 56 registers because they feed registers in a different clock domain Info (13100): Not allowed to move at least 3 registers because they feed clock or asynchronous control signals of other registers Info (13101): Not allowed to move at least 55 registers due to user assignments Info (13102): Not allowed to move at least 2 registers due to timing assignments Info (13089): The Quartus Prime software applied gate-level register retiming to 1 clock domains Info (13092): The Quartus Prime software applied gate-level register retiming to clock "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]": created 25 new registers, removed 12 registers, left 2239 registers untouched Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "run_led" is stuck at VCC Warning (13410): Pin "sdram_cke" is stuck at VCC Warning (13410): Pin "flash_a[24]" is stuck at GND Warning (13410): Pin "txd" is stuck at VCC Info (286031): Timing-Driven Synthesis is running on partition "Top" Info (17049): 216 registers lost all their fanouts during netlist optimizations. Info (128000): Starting physical synthesis optimizations for speed Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 1 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 41.666 clk Info (128002): Starting physical synthesis algorithm register retiming Info (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 Info (144001): Generated suppressed messages file C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/standard.map.smsg Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Info (21057): Implemented 5915 device resources after synthesis - the final resource count might be different Info (21058): Implemented 6 input pins Info (21059): Implemented 57 output pins Info (21060): Implemented 48 bidirectional pins Info (21061): Implemented 5511 logic cells Info (21064): Implemented 285 RAM segments Info (21065): Implemented 1 PLLs Info (21062): Implemented 6 DSP elements Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 17 warnings Info: Peak virtual memory: 5222 megabytes Info: Processing ended: Mon May 30 11:51:30 2022 Info: Elapsed time: 00:00:33 Info: Total CPU time (on all processors): 00:00:50 Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition Info: Processing started: Mon May 30 11:51:33 2022 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off standard -c standard Info: qfit2_default_script.tcl version: #1 Info: Project = standard Info: Revision = standard Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected Info (119006): Selected device EP4CE55F23I7 for design "standard" Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (15535): Implemented PLL "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type Info (15099): Implementing clock multiplication of 25, clock division of 6, and phase shift of 0 degrees (0 ps) for pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port Info (15099): Implementing clock multiplication of 25, clock division of 6, and phase shift of 0 degrees (0 ps) for pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device EP4CE15F23A7 is compatible Info (176445): Device EP4CE15F23C7 is compatible Info (176445): Device EP4CE15F23I7 is compatible Info (176445): Device EP4CE40F23A7 is compatible Info (176445): Device EP4CE40F23C7 is compatible Info (176445): Device EP4CE40F23I7 is compatible Info (176445): Device EP4CE30F23A7 is compatible Info (176445): Device EP4CE30F23C7 is compatible Info (176445): Device EP4CE30F23I7 is compatible Info (176445): Device EP4CE55F23C7 is compatible Info (176445): Device EP4CE55F23A7 is compatible Info (176445): Device EP4CE75F23C7 is compatible Info (176445): Device EP4CE75F23I7 is compatible Info (176445): Device EP4CE115F23C7 is compatible Info (176445): Device EP4CE115F23I7 is compatible Info (169124): Fitter converted 5 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity alt_jtag_atlantic Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity sld_hub Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} Info (332104): Reading SDC File: 'standard.out.sdc' Warning (332043): Overwriting existing clock: altera_reserved_tck Info (332104): Reading SDC File: 'Nios2/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'Nios2/synthesis/submodules/Nios2_nios2_qsys_0_cpu.sdc' Warning (332056): PLL cross checking found inconsistent PLL clock settings: Warning (332056): Node: pll_inst|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666 Warning (332056): Node: pll_inst|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666 Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From clk (Rise) to clk (Rise) (setup and hold) Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 2 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 100.000 altera_reserved_tck Info (332111): 41.666 clk Info (176353): Automatically promoted node pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C1 of PLL_3) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G14 Info (176353): Automatically promoted node pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C0 of PLL_3) Info (176355): Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL3E0 Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176353): Automatically promoted node Nios2:Nios2_inst|altera_reset_controller:rst_controller_001|r_sync_rst Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node Nios2:Nios2_inst|altera_reset_controller:rst_controller_001|WideOr0~0 Info (176357): Destination node Nios2:Nios2_inst|Nios2_nios2_qsys_0:nios2_qsys_0|Nios2_nios2_qsys_0_cpu:cpu|Nios2_nios2_qsys_0_cpu_nios2_oci:the_Nios2_nios2_qsys_0_cpu_nios2_oci|Nios2_nios2_qsys_0_cpu_nios2_oci_debug:the_Nios2_nios2_qsys_0_cpu_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 Info (176353): Automatically promoted node Nios2:Nios2_inst|altera_reset_controller:rst_controller|r_sync_rst Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_rnw Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[22] Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[21] Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[20] Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[19] Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[18] Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[17] Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[16] Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[15] Info (176357): Destination node Nios2:Nios2_inst|Nios2_sdram_0:sdram_0|active_addr[14] Info (176358): Non-global destination nodes limited to 10 nodes Info (176353): Automatically promoted node Nios2:Nios2_inst|altera_reset_controller:rst_controller_001|merged_reset~0 Info (176355): Automatically promoted destinations to use location or clock signal Global Clock Info (176233): Starting register packing Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments Info (176252): Wildcard assignment "Fast Output Enable Register=ON" to "oe" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_dqm[3]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_dqm[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_dqm[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_dqm[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[9]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[8]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[7]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[6]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[5]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[4]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[3]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[31]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[30]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[29]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[28]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[27]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[26]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[25]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[24]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[23]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[22]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[21]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[20]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[19]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[18]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[17]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[16]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[15]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[14]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[13]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[12]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[11]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[10]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_bank[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_bank[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[9]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[8]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[7]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[6]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[5]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[4]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[3]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[12]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[11]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[10]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_addr[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment Info (176235): Finished register packing Extra Info (176218): Packed 10 registers into blocks of type EC Extra Info (176218): Packed 16 registers into blocks of type Embedded multiplier block Extra Info (176218): Packed 64 registers into blocks of type Embedded multiplier output Extra Info (176218): Packed 32 registers into blocks of type I/O Input Buffer Extra Info (176218): Packed 87 registers into blocks of type I/O Output Buffer Extra Info (176220): Created 101 register duplicates Warning (15058): PLL "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[1] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins Info (128000): Starting physical synthesis optimizations for speed Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:02 Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "cts" is assigned to location or region, but does not exist in design Warning (15706): Node "rts" is assigned to location or region, but does not exist in design Info (171121): Fitter preparation operations ending: elapsed time is 00:00:07 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:07 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 3% of the available device resources Info (170196): Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X44_Y21 to location X54_Y31 Info (170194): Fitter routing operations ending: elapsed time is 00:00:07 Info (11888): Total time spent on timing analysis during the Fitter is 4.50 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (169177): 78 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin flash_ce_n uses I/O standard 3.3-V LVTTL at E4 Info (169178): Pin flash_oe_n uses I/O standard 3.3-V LVTTL at C2 Info (169178): Pin flash_we_n uses I/O standard 3.3-V LVTTL at E3 Info (169178): Pin flash_a[0] uses I/O standard 3.3-V LVTTL at M1 Info (169178): Pin flash_a[1] uses I/O standard 3.3-V LVTTL at M2 Info (169178): Pin flash_a[2] uses I/O standard 3.3-V LVTTL at M3 Info (169178): Pin flash_a[3] uses I/O standard 3.3-V LVTTL at L6 Info (169178): Pin flash_a[4] uses I/O standard 3.3-V LVTTL at M4 Info (169178): Pin flash_a[5] uses I/O standard 3.3-V LVTTL at N1 Info (169178): Pin flash_a[6] uses I/O standard 3.3-V LVTTL at N2 Info (169178): Pin flash_a[7] uses I/O standard 3.3-V LVTTL at N6 Info (169178): Pin flash_a[8] uses I/O standard 3.3-V LVTTL at U1 Info (169178): Pin flash_a[9] uses I/O standard 3.3-V LVTTL at T5 Info (169178): Pin flash_a[10] uses I/O standard 3.3-V LVTTL at R1 Info (169178): Pin flash_a[11] uses I/O standard 3.3-V LVTTL at P3 Info (169178): Pin flash_a[12] uses I/O standard 3.3-V LVTTL at V3 Info (169178): Pin flash_a[13] uses I/O standard 3.3-V LVTTL at W2 Info (169178): Pin flash_a[14] uses I/O standard 3.3-V LVTTL at V2 Info (169178): Pin flash_a[15] uses I/O standard 3.3-V LVTTL at V1 Info (169178): Pin flash_a[16] uses I/O standard 3.3-V LVTTL at R2 Info (169178): Pin flash_a[17] uses I/O standard 3.3-V LVTTL at M6 Info (169178): Pin flash_a[18] uses I/O standard 3.3-V LVTTL at N5 Info (169178): Pin flash_a[19] uses I/O standard 3.3-V LVTTL at P4 Info (169178): Pin flash_a[20] uses I/O standard 3.3-V LVTTL at P1 Info (169178): Pin flash_a[21] uses I/O standard 3.3-V LVTTL at P2 Info (169178): Pin flash_a[22] uses I/O standard 3.3-V LVTTL at Y2 Info (169178): Pin flash_a[23] uses I/O standard 3.3-V LVTTL at Y1 Info (169178): Pin sdram_dq[0] uses I/O standard 3.3-V LVTTL at G7 Info (169178): Pin sdram_dq[1] uses I/O standard 3.3-V LVTTL at C8 Info (169178): Pin sdram_dq[2] uses I/O standard 3.3-V LVTTL at F7 Info (169178): Pin sdram_dq[3] uses I/O standard 3.3-V LVTTL at F8 Info (169178): Pin sdram_dq[4] uses I/O standard 3.3-V LVTTL at E7 Info (169178): Pin sdram_dq[5] uses I/O standard 3.3-V LVTTL at F9 Info (169178): Pin sdram_dq[6] uses I/O standard 3.3-V LVTTL at E9 Info (169178): Pin sdram_dq[7] uses I/O standard 3.3-V LVTTL at F10 Info (169178): Pin sdram_dq[8] uses I/O standard 3.3-V LVTTL at B5 Info (169178): Pin sdram_dq[9] uses I/O standard 3.3-V LVTTL at A5 Info (169178): Pin sdram_dq[10] uses I/O standard 3.3-V LVTTL at C4 Info (169178): Pin sdram_dq[11] uses I/O standard 3.3-V LVTTL at A3 Info (169178): Pin sdram_dq[12] uses I/O standard 3.3-V LVTTL at B4 Info (169178): Pin sdram_dq[13] uses I/O standard 3.3-V LVTTL at C3 Info (169178): Pin sdram_dq[14] uses I/O standard 3.3-V LVTTL at A4 Info (169178): Pin sdram_dq[15] uses I/O standard 3.3-V LVTTL at B3 Info (169178): Pin sdram_dq[16] uses I/O standard 3.3-V LVTTL at A8 Info (169178): Pin sdram_dq[17] uses I/O standard 3.3-V LVTTL at A9 Info (169178): Pin sdram_dq[18] uses I/O standard 3.3-V LVTTL at B8 Info (169178): Pin sdram_dq[19] uses I/O standard 3.3-V LVTTL at B10 Info (169178): Pin sdram_dq[20] uses I/O standard 3.3-V LVTTL at B9 Info (169178): Pin sdram_dq[21] uses I/O standard 3.3-V LVTTL at C10 Info (169178): Pin sdram_dq[22] uses I/O standard 3.3-V LVTTL at A10 Info (169178): Pin sdram_dq[23] uses I/O standard 3.3-V LVTTL at D10 Info (169178): Pin sdram_dq[24] uses I/O standard 3.3-V LVTTL at A7 Info (169178): Pin sdram_dq[25] uses I/O standard 3.3-V LVTTL at B6 Info (169178): Pin sdram_dq[26] uses I/O standard 3.3-V LVTTL at D7 Info (169178): Pin sdram_dq[27] uses I/O standard 3.3-V LVTTL at A6 Info (169178): Pin sdram_dq[28] uses I/O standard 3.3-V LVTTL at B7 Info (169178): Pin sdram_dq[29] uses I/O standard 3.3-V LVTTL at C7 Info (169178): Pin sdram_dq[30] uses I/O standard 3.3-V LVTTL at C6 Info (169178): Pin sdram_dq[31] uses I/O standard 3.3-V LVTTL at D6 Info (169178): Pin flash_dq[0] uses I/O standard 3.3-V LVTTL at J6 Info (169178): Pin flash_dq[1] uses I/O standard 3.3-V LVTTL at E1 Info (169178): Pin flash_dq[2] uses I/O standard 3.3-V LVTTL at J5 Info (169178): Pin flash_dq[3] uses I/O standard 3.3-V LVTTL at D2 Info (169178): Pin flash_dq[4] uses I/O standard 3.3-V LVTTL at B2 Info (169178): Pin flash_dq[5] uses I/O standard 3.3-V LVTTL at J4 Info (169178): Pin flash_dq[6] uses I/O standard 3.3-V LVTTL at C1 Info (169178): Pin flash_dq[7] uses I/O standard 3.3-V LVTTL at H6 Info (169178): Pin flash_dq[8] uses I/O standard 3.3-V LVTTL at F2 Info (169178): Pin flash_dq[9] uses I/O standard 3.3-V LVTTL at J2 Info (169178): Pin flash_dq[10] uses I/O standard 3.3-V LVTTL at F1 Info (169178): Pin flash_dq[11] uses I/O standard 3.3-V LVTTL at J1 Info (169178): Pin flash_dq[12] uses I/O standard 3.3-V LVTTL at G4 Info (169178): Pin flash_dq[13] uses I/O standard 3.3-V LVTTL at H1 Info (169178): Pin flash_dq[14] uses I/O standard 3.3-V LVTTL at G3 Info (169178): Pin flash_dq[15] uses I/O standard 3.3-V LVTTL at H2 Info (169178): Pin reset_n uses I/O standard 3.3-V LVTTL at H19 Info (169178): Pin clk uses I/O standard 3.3-V LVTTL at B12 Info (169178): Pin rxd uses I/O standard 3.3-V LVTTL at AA1 Info (144001): Generated suppressed messages file C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/standard.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 18 warnings Info: Peak virtual memory: 6111 megabytes Info: Processing ended: Mon May 30 11:52:03 2022 Info: Elapsed time: 00:00:30 Info: Total CPU time (on all processors): 00:00:50 Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition Info: Processing started: Mon May 30 11:52:14 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off standard -c standard Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4906 megabytes Info: Processing ended: Mon May 30 11:52:16 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition Info: Processing started: Mon May 30 11:52:19 2022 Info: Command: quartus_sta standard -c standard Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity alt_jtag_atlantic Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity sld_hub Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} Info (332104): Reading SDC File: 'standard.out.sdc' Warning (332043): Overwriting existing clock: altera_reserved_tck Info (332104): Reading SDC File: 'Nios2/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'Nios2/synthesis/submodules/Nios2_nios2_qsys_0_cpu.sdc' Warning (332056): PLL cross checking found inconsistent PLL clock settings: Warning (332056): Node: pll_inst|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666 Warning (332056): Node: pll_inst|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666 Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From clk (Rise) to clk (Rise) (setup and hold) Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 100C Model Info (332146): Worst-case setup slack is 29.428 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 29.428 0.000 clk Info (332119): 46.958 0.000 altera_reserved_tck Info (332146): Worst-case hold slack is 0.272 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.272 0.000 clk Info (332119): 0.413 0.000 altera_reserved_tck Info (332146): Worst-case recovery slack is 36.445 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 36.445 0.000 clk Info (332119): 48.358 0.000 altera_reserved_tck Info (332146): Worst-case removal slack is 1.239 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.239 0.000 altera_reserved_tck Info (332119): 3.320 0.000 clk Info (332146): Worst-case minimum pulse width slack is 20.278 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 20.278 0.000 clk Info (332119): 49.559 0.000 altera_reserved_tck Info (332114): Report Metastability: Found 11 synchronizer chains. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 11 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.455 Info (332114): Worst Case Available Settling Time: 80.461 ns Info (332114): Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 Info: Analyzing Slow 1200mV -40C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Warning (332056): PLL cross checking found inconsistent PLL clock settings: Warning (332056): Node: pll_inst|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666 Warning (332056): Node: pll_inst|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666 Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From clk (Rise) to clk (Rise) (setup and hold) Info (332146): Worst-case setup slack is 30.610 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 30.610 0.000 clk Info (332119): 47.415 0.000 altera_reserved_tck Info (332146): Worst-case hold slack is 0.274 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.274 0.000 clk Info (332119): 0.341 0.000 altera_reserved_tck Info (332146): Worst-case recovery slack is 37.098 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 37.098 0.000 clk Info (332119): 48.728 0.000 altera_reserved_tck Info (332146): Worst-case removal slack is 1.097 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.097 0.000 altera_reserved_tck Info (332119): 2.837 0.000 clk Info (332146): Worst-case minimum pulse width slack is 20.296 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 20.296 0.000 clk Info (332119): 49.454 0.000 altera_reserved_tck Info (332114): Report Metastability: Found 11 synchronizer chains. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 11 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.455 Info (332114): Worst Case Available Settling Time: 80.844 ns Info (332114): Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 Info: Analyzing Fast 1200mV -40C Model Warning (332056): PLL cross checking found inconsistent PLL clock settings: Warning (332056): Node: pll_inst|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666 Warning (332056): Node: pll_inst|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 41.666 Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From clk (Rise) to clk (Rise) (setup and hold) Info (332146): Worst-case setup slack is 35.532 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 35.532 0.000 clk Info (332119): 48.908 0.000 altera_reserved_tck Info (332146): Worst-case hold slack is 0.090 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.090 0.000 clk Info (332119): 0.176 0.000 altera_reserved_tck Info (332146): Worst-case recovery slack is 39.049 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 39.049 0.000 clk Info (332119): 49.594 0.000 altera_reserved_tck Info (332146): Worst-case removal slack is 0.564 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.564 0.000 altera_reserved_tck Info (332119): 1.608 0.000 clk Info (332146): Worst-case minimum pulse width slack is 20.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 20.000 0.000 clk Info (332119): 49.301 0.000 altera_reserved_tck Info (332114): Report Metastability: Found 11 synchronizer chains. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 11 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.455 Info (332114): Worst Case Available Settling Time: 82.036 ns Info (332114): Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 25 warnings Info: Peak virtual memory: 5121 megabytes Info: Processing ended: Mon May 30 11:52:23 2022 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition Info: Processing started: Mon May 30 11:52:26 2022 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off standard -c standard Info (204019): Generated file standard_7_1200mv_100c_slow.vho in folder "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file standard_7_1200mv_-40c_slow.vho in folder "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file standard_min_1200mv_-40c_fast.vho in folder "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file standard.vho in folder "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file standard_7_1200mv_100c_vhd_slow.sdo in folder "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file standard_7_1200mv_-40c_vhd_slow.sdo in folder "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file standard_min_1200mv_-40c_vhd_fast.sdo in folder "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file standard_vhd.sdo in folder "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/simulation/modelsim/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4923 megabytes Info: Processing ended: Mon May 30 11:52:30 2022 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 60 warnings