https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#tab-blade-1-1 # reset interface set_location_assignment PIN_BN52 -to pcie_rstn_pin_perst # PCIe clocking and reset set_location_assignment PIN_AW44 -to refclk_clk set_location_assignment PIN_AW43 -to "refclk_clk(n)" set_location_assignment PIN_BH54 -to xcvr_tx_out0 set_location_assignment PIN_BH53 -to "xcvr_tx_out0(n)" set_location_assignment PIN_BG52 -to xcvr_tx_out1 set_location_assignment PIN_BG51 -to "xcvr_tx_out1(n)" set_location_assignment PIN_BF54 -to xcvr_tx_out2 set_location_assignment PIN_BF53 -to "xcvr_tx_out2(n)" set_location_assignment PIN_BE52 -to xcvr_tx_out3 set_location_assignment PIN_BE51 -to "xcvr_tx_out3(n)" set_location_assignment PIN_BD54 -to xcvr_tx_out4 set_location_assignment PIN_BD53 -to "xcvr_tx_out4(n)" set_location_assignment PIN_BC52 -to xcvr_tx_out5 set_location_assignment PIN_BC51 -to "xcvr_tx_out5(n)" set_location_assignment PIN_BB54 -to xcvr_tx_out6 set_location_assignment PIN_BB53 -to "xcvr_tx_out6(n)" set_location_assignment PIN_BA52 -to xcvr_tx_out7 set_location_assignment PIN_BA51 -to "xcvr_tx_out7(n)" set_location_assignment PIN_AY50 -to xcvr_tx_out8 set_location_assignment PIN_AY49 -to "xcvr_tx_out8(n)" set_location_assignment PIN_AY54 -to xcvr_tx_out9 set_location_assignment PIN_AY53 -to "xcvr_tx_out9(n)" set_location_assignment PIN_AW52 -to xcvr_tx_out10 set_location_assignment PIN_AW51 -to "xcvr_tx_out10(n)" set_location_assignment PIN_AV50 -to xcvr_tx_out11 set_location_assignment PIN_AV49 -to "xcvr_tx_out11(n)" set_location_assignment PIN_AV54 -to xcvr_tx_out12 set_location_assignment PIN_AV53 -to "xcvr_tx_out12(n)" set_location_assignment PIN_AU52 -to xcvr_tx_out13 set_location_assignment PIN_AU51 -to "xcvr_tx_out13(n)" set_location_assignment PIN_AT50 -to xcvr_tx_out14 set_location_assignment PIN_AT49 -to "xcvr_tx_out14(n)" set_location_assignment PIN_AT54 -to xcvr_tx_out15 set_location_assignment PIN_AT53 -to "xcvr_tx_out15(n)" set_location_assignment PIN_BF50 -to xcvr_rx_in0 set_location_assignment PIN_BF49 -to "xcvr_rx_in0(n)" set_location_assignment PIN_BE48 -to xcvr_rx_in1 set_location_assignment PIN_BE47 -to "xcvr_rx_in1(n)" set_location_assignment PIN_BD50 -to xcvr_rx_in2 set_location_assignment PIN_BD49 -to "xcvr_rx_in2(n)" set_location_assignment PIN_BC48 -to xcvr_rx_in3 set_location_assignment PIN_BC47 -to "xcvr_rx_in3(n)" set_location_assignment PIN_BB50 -to xcvr_rx_in4 set_location_assignment PIN_BB49 -to "xcvr_rx_in4(n)" set_location_assignment PIN_BB46 -to xcvr_rx_in5 set_location_assignment PIN_BB45 -to "xcvr_rx_in5(n)" set_location_assignment PIN_BA48 -to xcvr_rx_in6 set_location_assignment PIN_BA47 -to "xcvr_rx_in6(n)" set_location_assignment PIN_AY46 -to xcvr_rx_in7 set_location_assignment PIN_AY45 -to "xcvr_rx_in7(n)" set_location_assignment PIN_AW48 -to xcvr_rx_in8 set_location_assignment PIN_AW47 -to "xcvr_rx_in8(n)" set_location_assignment PIN_AV46 -to xcvr_rx_in9 set_location_assignment PIN_AV45 -to "xcvr_rx_in9(n)" set_location_assignment PIN_AU48 -to xcvr_rx_in10 set_location_assignment PIN_AU47 -to "xcvr_rx_in10(n)" set_location_assignment PIN_AT46 -to xcvr_rx_in11 set_location_assignment PIN_AT45 -to "xcvr_rx_in11(n)" set_location_assignment PIN_AR48 -to xcvr_rx_in12 set_location_assignment PIN_AR47 -to "xcvr_rx_in12(n)" set_location_assignment PIN_AP46 -to xcvr_rx_in13 set_location_assignment PIN_AP45 -to "xcvr_rx_in13(n)" set_location_assignment PIN_AP50 -to xcvr_rx_in14 set_location_assignment PIN_AP49 -to "xcvr_rx_in14(n)" set_location_assignment PIN_AN48 -to xcvr_rx_in15 set_location_assignment PIN_AN47 -to "xcvr_rx_in15(n)" set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677 set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 40 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY" set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name VERILOG_FILE pcie_ed_top.v set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_DUT.ip set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_resetIP.ip set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_DMA_MEM.ip set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_PIO_INTERPRETER.ip set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_PIO_MEM.ip set_global_assignment -name QSYS_FILE pcie_ed.qsys set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" set_global_assignment -name USE_CONF_DONE SDM_IO16 set_global_assignment -name USE_INIT_DONE SDM_IO5 set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name BOARD default set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL set_global_assignment -name MESSAGE_DISABLE 12677 -entity pcie_ed_top set_global_assignment -name MESSAGE_DISABLE 21955 -entity pcie_ed_top set_instance_assignment -name VIRTUAL_PIN ON -to *pipe_sim_only* -entity *DUT set_instance_assignment -name VIRTUAL_PIN ON -to hip_ctrl_test_in -entity *DUT set_instance_assignment -name VIRTUAL_PIN ON -to hip_ctrl_simu_mode_pipe -entity *DUT set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to pcie_rstn_pin_perst -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out0 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out1 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out2 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out3 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out4 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out5 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out6 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out7 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out8 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out9 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out10 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out11 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out12 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out13 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out14 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out15 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in0 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in1 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in2 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in3 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in4 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in5 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in6 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in7 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in8 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in9 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in10 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in11 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in12 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in13 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in14 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in15 -entity pcie_ed_top set_instance_assignment -name IO_STANDARD LVDS -to refclk_clk -entity pcie_ed_top set_instance_assignment -name IO_STANDARD LVDS -to "refclk_clk(n)" -entity pcie_ed_top set_global_assignment -name FLOW_ENABLE_INTERACTIVE_TIMING_ANALYZER OFF set_global_assignment -name GENERATE_PROGRAMMING_FILES ON