----------------
; Command Info ;
----------------
Report Timing: Found 1 setup paths (1 violated).  Worst case slack is -2.081 

Tcl Command:
    report_timing -setup -file {file.txt} 

Options:
    -setup 
    -file {file.txt} 


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Summary of Paths                                                                                                                                                                      ;
+--------+------------------------+------------------------------------------------------------------------------------------------------------------------+--------------+-------------+
; Slack  ; From Node              ; To Node                                                                                                                ; Launch Clock ; Latch Clock ;
+--------+------------------------+------------------------------------------------------------------------------------------------------------------------+--------------+-------------+
; -2.081 ; in_mode_init~DUPLICATE ; fu_x:\gen_fu_x:8:fu_x_inst|altsyncram:buff_mess_0_rtl_17|altsyncram_eqi1:auto_generated|ram_block1a3~porta_datain_reg0 ; clock        ; clock       ;
+--------+------------------------+------------------------------------------------------------------------------------------------------------------------+--------------+-------------+

Path #1: Setup slack is -2.081 (VIOLATED)
===============================================================================
+---------------------------------------------------------------------------------------------------------------------------------------------+
; Path Summary                                                                                                                                ;
+--------------------+------------------------------------------------------------------------------------------------------------------------+
; Property           ; Value                                                                                                                  ;
+--------------------+------------------------------------------------------------------------------------------------------------------------+
; From Node          ; in_mode_init~DUPLICATE                                                                                                 ;
; To Node            ; fu_x:\gen_fu_x:8:fu_x_inst|altsyncram:buff_mess_0_rtl_17|altsyncram_eqi1:auto_generated|ram_block1a3~porta_datain_reg0 ;
; Launch Clock       ; clock                                                                                                                  ;
; Latch Clock        ; clock                                                                                                                  ;
; Data Arrival Time  ; 10.381                                                                                                                 ;
; Data Required Time ; 8.282                                                                                                                  ;
; Clock Pessimism    ; 0.018                                                                                                                  ;
; Slack              ; -2.081 (VIOLATED)                                                                                                      ;
+--------------------+------------------------------------------------------------------------------------------------------------------------+

+---------------------------------------------------------------------------------------+
; Statistics                                                                            ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property                  ; Value  ; Count ; Total Delay ; % of Total ; Min   ; Max   ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Setup Relationship        ; 5.000  ;       ;             ;            ;       ;       ;
; Clock Skew                ; -0.089 ;       ;             ;            ;       ;       ;
; Data Delay                ; 6.939  ;       ;             ;            ;       ;       ;
; Number of Logic Levels    ;        ; 1     ;             ;            ;       ;       ;
; Physical Delays           ;        ;       ;             ;            ;       ;       ;
;  Arrival Path             ;        ;       ;             ;            ;       ;       ;
;   Clock                   ;        ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;        ; 1     ; 3.442       ; 100        ; 3.442 ; 3.442 ;
;   Data                    ;        ;       ;             ;            ;       ;       ;
;    IC                     ;        ; 2     ; 6.457       ; 93         ; 2.704 ; 3.753 ;
;    Cell                   ;        ; 3     ; 0.409       ; 5          ; 0.000 ; 0.294 ;
;    uTco                   ;        ; 1     ; 0.073       ; 1          ; 0.073 ; 0.073 ;
;  Required Path            ;        ;       ;             ;            ;       ;       ;
;   Clock                   ;        ;       ;             ;            ;       ;       ;
;    Clock Network (Lumped) ;        ; 1     ; 3.353       ; 100        ; 3.353 ; 3.353 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Arrival Path                                                                                                                                                                 ;
+--------+-------+----+------+--------+--------------------+------------------------------------------------------------------------------------------------------------------------+
; Total  ; Incr  ; RF ; Type ; Fanout ; Location           ; Element                                                                                                                ;
+--------+-------+----+------+--------+--------------------+------------------------------------------------------------------------------------------------------------------------+
; 0.000  ; 0.000 ;    ;      ;        ;                    ; launch edge time                                                                                                       ;
; 3.442  ; 3.442 ; R  ;      ;        ;                    ; clock network delay                                                                                                    ;
; 3.515  ; 0.073 ;    ; uTco ; 1      ; FF_X67_Y52_N1      ; in_mode_init~DUPLICATE                                                                                                 ;
; 3.515  ; 0.000 ; FF ; CELL ; 1164   ; FF_X67_Y52_N1      ; in_mode_init~DUPLICATE|q                                                                                               ;
; 7.268  ; 3.753 ; FF ; IC   ; 1      ; LABCELL_X9_Y21_N16 ; \gen_fu_x:22:fu_x_inst|buff_mess_2~946|datad                                                                           ;
; 7.562  ; 0.294 ; FR ; CELL ; 3      ; LABCELL_X9_Y21_N16 ; \gen_fu_x:22:fu_x_inst|buff_mess_2~946|combout                                                                         ;
; 10.266 ; 2.704 ; RR ; IC   ; 1      ; M9K_X45_Y44_N0     ; \gen_fu_x:8:fu_x_inst|buff_mess_0_rtl_17|auto_generated|ram_block1a3|portadatain[19]                                   ;
; 10.381 ; 0.115 ; RR ; CELL ; 0      ; M9K_X45_Y44_N0     ; fu_x:\gen_fu_x:8:fu_x_inst|altsyncram:buff_mess_0_rtl_17|altsyncram_eqi1:auto_generated|ram_block1a3~porta_datain_reg0 ;
+--------+-------+----+------+--------+--------------------+------------------------------------------------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Required Path                                                                                                                                                            ;
+-------+--------+----+------+--------+----------------+------------------------------------------------------------------------------------------------------------------------+
; Total ; Incr   ; RF ; Type ; Fanout ; Location       ; Element                                                                                                                ;
+-------+--------+----+------+--------+----------------+------------------------------------------------------------------------------------------------------------------------+
; 5.000 ; 5.000  ;    ;      ;        ;                ; latch edge time                                                                                                        ;
; 8.353 ; 3.353  ; R  ;      ;        ;                ; clock network delay                                                                                                    ;
; 8.282 ; -0.071 ;    ; uTsu ; 0      ; M9K_X45_Y44_N0 ; fu_x:\gen_fu_x:8:fu_x_inst|altsyncram:buff_mess_0_rtl_17|altsyncram_eqi1:auto_generated|ram_block1a3~porta_datain_reg0 ;
+-------+--------+----+------+--------+----------------+------------------------------------------------------------------------------------------------------------------------+