Info: Starting: Create simulation model
Info: qsys-generate E:\Projects\MK666_MOD3\CONTROLLED_FILES\4524000-MOD3_CWI_NTS\4524000_SUBRACK\4524320_DIGITIZER\4524320-10_DIGITIZER_PXIe\FPGA_v21\q_sys.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=E:\Projects\MK666_MOD3\CONTROLLED_FILES\4524000-MOD3_CWI_NTS\4524000_SUBRACK\4524320_DIGITIZER\4524320-10_DIGITIZER_PXIe\FPGA_v21\q_sys\simulation --family="Cyclone V" --part=5CGTFD9E5F35C7
Progress: Loading FPGA_v21/q_sys.qsys
Progress: Reading input file
Progress: Adding clk_100 [clock_source 21.1]
Progress: Parameterizing module clk_100
Progress: Adding clk_50 [clock_source 21.1]
Progress: Parameterizing module clk_50
Progress: Adding clk_pciecore [clock_source 21.1]
Progress: Parameterizing module clk_pciecore
Progress: Adding ddr3 [altera_mem_if_ddr3_emif 21.1]
Progress: Parameterizing module ddr3
Progress: Adding mbox_msg [altera_avalon_mailbox_simple 21.1]
Progress: Parameterizing module mbox_msg
Progress: Adding mm_clock_crossing_bridge_0 [altera_avalon_mm_clock_crossing_bridge 21.1]
Progress: Parameterizing module mm_clock_crossing_bridge_0
Progress: Adding mm_clock_crossing_bridge_1 [altera_avalon_mm_clock_crossing_bridge 21.1]
Progress: Parameterizing module mm_clock_crossing_bridge_1
Progress: Adding mm_clock_crossing_bridge_2 [altera_avalon_mm_clock_crossing_bridge 21.1]
Progress: Parameterizing module mm_clock_crossing_bridge_2
Progress: Adding msgdma [altera_msgdma 21.1]
Progress: Parameterizing module msgdma
Progress: Adding onchip_mem [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module onchip_mem
Progress: Adding pcie [altera_pcie_cv_hip_avmm 21.1]
Progress: Parameterizing module pcie
Progress: Adding pio_calctrl [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calctrl
Progress: Adding pio_calword_00 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_00
Progress: Adding pio_calword_01 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_01
Progress: Adding pio_calword_02 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_02
Progress: Adding pio_calword_03 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_03
Progress: Adding pio_calword_04 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_04
Progress: Adding pio_calword_05 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_05
Progress: Adding pio_calword_06 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_06
Progress: Adding pio_calword_07 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_07
Progress: Adding pio_calword_08 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_08
Progress: Adding pio_calword_09 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_09
Progress: Adding pio_calword_10 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_10
Progress: Adding pio_calword_11 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_11
Progress: Adding pio_calword_12 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_12
Progress: Adding pio_calword_13 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_13
Progress: Adding pio_calword_14 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_14
Progress: Adding pio_calword_15 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_15
Progress: Adding pio_calword_16 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_16
Progress: Adding pio_calword_17 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_17
Progress: Adding pio_calword_18 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_18
Progress: Adding pio_calword_19 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_19
Progress: Adding pio_error [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_error
Progress: Adding pio_firmware_rev [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_firmware_rev
Progress: Adding pio_fram_status [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_fram_status
Progress: Adding pio_io_busy [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_io_busy
Progress: Adding pio_ioctrl [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_ioctrl
Progress: Adding xcvr_reconfig [alt_xcvr_reconfig 19.1]
Progress: Parameterizing module xcvr_reconfig
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: q_sys.ddr3: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Warning: q_sys.ddr3.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
Info: q_sys.msgdma: Response information port is disabled. Enable the response port if data transfer information is required by host
Info: q_sys.pcie: The application clock frequency (pld_clk) is 125 Mhz
Info: q_sys.pcie: 5 reconfiguration interfaces are required for connection to the external reconfiguration controller
Info: q_sys.pcie: Family: Cyclone V
Info: q_sys.pcie: Credit allocation in the 6K bytes receive buffer:
Info: q_sys.pcie: Posted    : header=1  data=16
Info: q_sys.pcie: Non posted: header=1  data=0
Info: q_sys.pcie: Completion: header=73 data=293
Info: q_sys.pcie: TXS ADDRESS WIDTH is 32
Info: q_sys.pio_calword_00: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_01: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_02: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_03: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_04: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_05: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_06: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_07: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_08: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_09: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_10: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_11: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_12: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_13: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_14: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_15: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_16: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_17: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_18: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_19: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_error: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_firmware_rev: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_fram_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_io_busy: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.xcvr_reconfig: reconfig_from_xcvr port width is 5*46 bits
Info: q_sys.xcvr_reconfig: reconfig_to_xcvr port width is 5*70 bits
Warning: q_sys.ddr3: ddr3.pll_sharing must be exported, or connected to a matching conduit.
Info: q_sys: Generating q_sys "q_sys" for SIM_VERILOG
Info: ddr3: "q_sys" instantiated altera_mem_if_ddr3_emif "ddr3"
Info: mbox_msg: "q_sys" instantiated altera_avalon_mailbox_simple "mbox_msg"
Info: mm_clock_crossing_bridge_0: "q_sys" instantiated altera_avalon_mm_clock_crossing_bridge "mm_clock_crossing_bridge_0"
Info: msgdma: "q_sys" instantiated altera_msgdma "msgdma"
Info: onchip_mem: Starting RTL generation for module 'q_sys_onchip_mem'
Info: onchip_mem:   Generation command is [exec E:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga/21.1/quartus/bin64/perl/lib -I E:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I E:/intelfpga/21.1/quartus/sopc_builder/bin -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_onchip_mem --dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0004_onchip_mem_gen/ --quartus_dir=E:/intelfpga/21.1/quartus --verilog --config=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0004_onchip_mem_gen//q_sys_onchip_mem_component_configuration.pl  --do_build_sim=1    --sim_dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0004_onchip_mem_gen/  ]
Info: onchip_mem: Done RTL generation for module 'q_sys_onchip_mem'
Info: onchip_mem: "q_sys" instantiated altera_avalon_onchip_memory2 "onchip_mem"
Info: pcie: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
Info: pcie: add_fileset_file ./sv_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_xcvr.sv
Info: pcie: add_fileset_file ./sv_reconfig_bundle_to_ip.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_ip.sv
Info: pcie: add_fileset_file ./sv_reconfig_bundle_merger.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_merger.sv
Info: pcie: add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv
Info: pcie: add_fileset_file ./av_xcvr_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm_csr.sv
Info: pcie: add_fileset_file ./av_tx_pma_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma_ch.sv
Info: pcie: add_fileset_file ./av_tx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma.sv
Info: pcie: add_fileset_file ./av_rx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_rx_pma.sv
Info: pcie: add_fileset_file ./av_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pma.sv
Info: pcie: add_fileset_file ./av_pcs_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs_ch.sv
Info: pcie: add_fileset_file ./av_pcs.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs.sv
Info: pcie: add_fileset_file ./av_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm.sv
Info: pcie: add_fileset_file ./av_xcvr_native.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_native.sv
Info: pcie: add_fileset_file ./av_xcvr_plls.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_plls.sv
Info: pcie: add_fileset_file ./av_xcvr_data_adapter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_data_adapter.sv
Info: pcie: add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv
Info: pcie: add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv
Info: pcie: add_fileset_file ./av_hssi_8g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_rx_pcs_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_8g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_tx_pcs_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_common_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pcs_pma_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_common_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pld_pcs_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_pipe_gen1_2_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_pipe_gen1_2_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_rx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pcs_pma_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_rx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pld_pcs_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_tx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pcs_pma_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_tx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pld_pcs_interface_rbc.sv
Info: pcie: add_fileset_file ./alt_reset_ctrl_lego.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_lego.sv
Info: pcie: add_fileset_file ./alt_reset_ctrl_tgx_cdrauto.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_tgx_cdrauto.sv
Info: pcie: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_common_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common_h.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_common.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_pcs8g_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g_h.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_pcs8g.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv
Info: pcie: add_fileset_file ./alt_xcvr_mgmt2dec.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_mgmt2dec.sv
Info: pcie: add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v
Info: pcie: add_fileset_file ./av_xcvr_emsip_adapter.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_emsip_adapter.sv
Info: pcie: add_fileset_file ./av_xcvr_pipe_native_hip.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_pipe_native_hip.sv
Info: pcie: "q_sys" instantiated altera_pcie_cv_hip_avmm "pcie"
Info: pio_calctrl: Starting RTL generation for module 'q_sys_pio_calctrl'
Info: pio_calctrl:   Generation command is [exec E:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga/21.1/quartus/bin64/perl/lib -I E:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I E:/intelfpga/21.1/quartus/sopc_builder/bin -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_pio_calctrl --dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0006_pio_calctrl_gen/ --quartus_dir=E:/intelfpga/21.1/quartus --verilog --config=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0006_pio_calctrl_gen//q_sys_pio_calctrl_component_configuration.pl  --do_build_sim=1    --sim_dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0006_pio_calctrl_gen/  ]
Info: pio_calctrl: Done RTL generation for module 'q_sys_pio_calctrl'
Info: pio_calctrl: "q_sys" instantiated altera_avalon_pio "pio_calctrl"
Info: pio_calword_00: Starting RTL generation for module 'q_sys_pio_calword_00'
Info: pio_calword_00:   Generation command is [exec E:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga/21.1/quartus/bin64/perl/lib -I E:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I E:/intelfpga/21.1/quartus/sopc_builder/bin -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_pio_calword_00 --dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0007_pio_calword_00_gen/ --quartus_dir=E:/intelfpga/21.1/quartus --verilog --config=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0007_pio_calword_00_gen//q_sys_pio_calword_00_component_configuration.pl  --do_build_sim=1    --sim_dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0007_pio_calword_00_gen/  ]
Info: pio_calword_00: Done RTL generation for module 'q_sys_pio_calword_00'
Info: pio_calword_00: "q_sys" instantiated altera_avalon_pio "pio_calword_00"
Info: pio_error: Starting RTL generation for module 'q_sys_pio_error'
Info: pio_error:   Generation command is [exec E:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga/21.1/quartus/bin64/perl/lib -I E:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I E:/intelfpga/21.1/quartus/sopc_builder/bin -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_pio_error --dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0008_pio_error_gen/ --quartus_dir=E:/intelfpga/21.1/quartus --verilog --config=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0008_pio_error_gen//q_sys_pio_error_component_configuration.pl  --do_build_sim=1    --sim_dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0008_pio_error_gen/  ]
Info: pio_error: Done RTL generation for module 'q_sys_pio_error'
Info: pio_error: "q_sys" instantiated altera_avalon_pio "pio_error"
Info: xcvr_reconfig: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/altera_xcvr_functions.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/altera_xcvr_functions.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xcvr_h.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/av/av_xcvr_h.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_resync.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/ctrl/alt_xcvr_resync.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_h.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_h.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_h.sv SYSTEM_VERILOG_ENCRYPT PATH ./mentor/alt_xcvr_reconfig_h.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig.sv SYSTEM_VERILOG_ENCRYPT PATH ./mentor/alt_xcvr_reconfig.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cal_seq.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_cal_seq.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_cal_seq.sv SYSTEM_VERILOG_ENCRYPT PATH ./mentor/alt_xcvr_reconfig_cal_seq.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_cif.sv SYSTEM_VERILOG PATH .//alt_xreconf_cif.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xreconf_cif.sv SYSTEM_VERILOG_ENCRYPT PATH ./mentor/alt_xreconf_cif.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_uif.sv SYSTEM_VERILOG PATH .//alt_xreconf_uif.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xreconf_uif.sv SYSTEM_VERILOG_ENCRYPT PATH ./mentor/alt_xreconf_uif.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_basic_acq.sv SYSTEM_VERILOG PATH .//alt_xreconf_basic_acq.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xreconf_basic_acq.sv SYSTEM_VERILOG_ENCRYPT PATH ./mentor/alt_xreconf_basic_acq.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_analog.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_analog.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_analog/mentor/alt_xcvr_reconfig_analog.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_analog_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog_av.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_analog_av.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_analog/mentor/alt_xcvr_reconfig_analog_av.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_analog_datactrl_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_datactrl_av.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xreconf_analog_datactrl_av.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_analog/mentor/alt_xreconf_analog_datactrl_av.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_analog_rmw_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_rmw_av.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xreconf_analog_rmw_av.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_analog/mentor/alt_xreconf_analog_rmw_av.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_analog_ctrlsm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_ctrlsm.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xreconf_analog_ctrlsm.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_analog/mentor/alt_xreconf_analog_ctrlsm.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_offset_cancellation.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_offset_cancellation.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_offset_cancellation/mentor/alt_xcvr_reconfig_offset_cancellation.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_offset_cancellation_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation_av.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_offset_cancellation_av.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_offset_cancellation/mentor/alt_xcvr_reconfig_offset_cancellation_av.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_eyemon.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_eyemon/alt_xcvr_reconfig_eyemon.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_eyemon.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_eyemon/mentor/alt_xcvr_reconfig_eyemon.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dfe.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dfe/alt_xcvr_reconfig_dfe.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_dfe.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_dfe/mentor/alt_xcvr_reconfig_dfe.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_adce.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_adce/alt_xcvr_reconfig_adce.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_adce.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_adce/mentor/alt_xcvr_reconfig_adce.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dcd.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_dcd.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_dcd/mentor/alt_xcvr_reconfig_dcd.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dcd_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dcd_cal_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_cal_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dcd_control_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_control_av.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_dcd_av.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_dcd/mentor/alt_xcvr_reconfig_dcd_av.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_dcd_cal_av.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_dcd/mentor/alt_xcvr_reconfig_dcd_cal_av.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_dcd_control_av.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_dcd/mentor/alt_xcvr_reconfig_dcd_control_av.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/alt_xcvr_reconfig_mif.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_mif.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_mif/mentor/alt_xcvr_reconfig_mif.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_mif_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_ctrl.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_mif_avmm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_avmm.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xcvr_reconfig_mif.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_mif/mentor/av_xcvr_reconfig_mif.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xcvr_reconfig_mif_ctrl.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_mif/mentor/av_xcvr_reconfig_mif_ctrl.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xcvr_reconfig_mif_avmm.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_mif/mentor/av_xcvr_reconfig_mif_avmm.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/alt_xcvr_reconfig_pll.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_pll.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_pll/mentor/alt_xcvr_reconfig_pll.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_pll_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll_ctrl.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xcvr_reconfig_pll.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_pll/mentor/av_xcvr_reconfig_pll.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xcvr_reconfig_pll_ctrl.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_pll/mentor/av_xcvr_reconfig_pll_ctrl.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_soc.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_soc/alt_xcvr_reconfig_soc.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_ram.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_soc/alt_xcvr_reconfig_cpu_ram.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_ram.hex OTHER PATH ../alt_xcvr_reconfig_soc/software/alt_xcvr_reconfig_av/mem_init/alt_xcvr_reconfig_cpu_ram.hex
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_direct.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_direct/alt_xcvr_reconfig_direct.sv
Info: xcvr_reconfig: add_fileset_file ./alt_arbiter_acq.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_arbiter_acq.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_xcvr_reconfig_basic.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_arbiter_acq.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_basic/mentor/alt_arbiter_acq.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_reconfig_basic.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_basic/mentor/alt_xcvr_reconfig_basic.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_l2p_addr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_addr.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_l2p_ch.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_ch.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_l2p_rom.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_rom.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_lif_csr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif_csr.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_lif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xcvr_reconfig_basic.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xrbasic_l2p_addr.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_basic/mentor/av_xrbasic_l2p_addr.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xrbasic_l2p_ch.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_basic/mentor/av_xrbasic_l2p_ch.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xrbasic_l2p_rom.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_basic/mentor/av_xrbasic_l2p_rom.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xrbasic_lif_csr.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_basic/mentor/av_xrbasic_lif_csr.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xrbasic_lif.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_basic/mentor/av_xrbasic_lif.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_xcvr_reconfig_basic.sv SYSTEM_VERILOG_ENCRYPT PATH ../alt_xcvr_reconfig_basic/mentor/av_xcvr_reconfig_basic.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_m2s.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_m2s.sv
Info: xcvr_reconfig: add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_arbiter.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/ctrl/alt_xcvr_arbiter.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_m2s.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/ctrl/alt_xcvr_m2s.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/altera_wait_generate.v VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/ctrl/altera_wait_generate.v MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/alt_xcvr_csr_selector.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/ctrl/alt_xcvr_csr_selector.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./sv_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_basic.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/sv_reconfig_bundle_to_basic.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/sv/sv_reconfig_bundle_to_basic.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv
Info: xcvr_reconfig: add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv
Info: xcvr_reconfig: add_fileset_file ./mentor/av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/av/av_reconfig_bundle_to_basic.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./mentor/av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG_ENCRYPT PATH ../../altera_xcvr_generic/mentor/av/av_reconfig_bundle_to_xcvr.sv MENTOR_SPECIFIC
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/alt_xcvr_reconfig_cpu.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_irq_mapper.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_irq_mapper.sv
Info: xcvr_reconfig: add_fileset_file ./altera_reset_controller.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_reset_controller.v
Info: xcvr_reconfig: add_fileset_file ./altera_reset_synchronizer.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_reset_synchronizer.v
Info: xcvr_reconfig: add_fileset_file ./altera_reset_controller.sdc OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_reset_controller.sdc
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu.sdc OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu.sdc
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_debug_slave_sysclk.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_debug_slave_sysclk.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_debug_slave_tck.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_debug_slave_tck.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_debug_slave_wrapper.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_debug_slave_wrapper.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_nios2_waves.do OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_nios2_waves.do
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_ociram_default_contents.dat OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_ociram_default_contents.dat
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_ociram_default_contents.hex OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_ociram_default_contents.hex
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_ociram_default_contents.mif OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_ociram_default_contents.mif
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_a.dat OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_a.dat
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_a.hex OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_a.hex
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_a.mif OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_a.mif
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_b.dat OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_b.dat
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_b.hex OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_b.hex
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_b.mif OTHER PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_rf_ram_b.mif
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_test_bench.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_reconfig_cpu_cpu_test_bench.v
Info: xcvr_reconfig: add_fileset_file ./altera_merlin_master_translator.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_merlin_master_translator.sv
Info: xcvr_reconfig: add_fileset_file ./altera_merlin_slave_translator.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_merlin_slave_translator.sv
Info: xcvr_reconfig: add_fileset_file ./altera_merlin_master_agent.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_merlin_master_agent.sv
Info: xcvr_reconfig: add_fileset_file ./altera_merlin_slave_agent.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_merlin_slave_agent.sv
Info: xcvr_reconfig: add_fileset_file ./altera_merlin_burst_uncompressor.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_merlin_burst_uncompressor.sv
Info: xcvr_reconfig: add_fileset_file ./altera_avalon_sc_fifo.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_avalon_sc_fifo.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv
Info: xcvr_reconfig: add_fileset_file ./altera_merlin_arbitrator.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/altera_merlin_arbitrator.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_demux.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_demux.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_avalon_st_adapter.v VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_avalon_st_adapter.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cpu_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv SYSTEM_VERILOG PATH C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0009_xcvr_reconfig_gen/SIM_VERILOG/submodules/alt_xcvr_reconfig_cpu_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
Info: xcvr_reconfig: "q_sys" instantiated alt_xcvr_reconfig "xcvr_reconfig"
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/altera_xcvr_functions.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/av_xcvr_h.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/alt_xcvr_resync.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/altera_wait_generate.v
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/alt_xcvr_csr_selector.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/av_reconfig_bundle_to_basic.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/av_reconfig_bundle_to_xcvr.sv
Warning: Overwriting different file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/plain_files.txt
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "q_sys" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_1: "q_sys" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_022: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_023: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_024: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_025: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_026: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_2: "q_sys" instantiated altera_mm_interconnect "mm_interconnect_2"
Info: irq_mapper: "q_sys" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "q_sys" instantiated altera_reset_controller "rst_controller"
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/altera_reset_controller.v
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/altera_reset_synchronizer.v
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/submodules/altera_reset_controller.sdc
Info: pll0: "ddr3" instantiated altera_mem_if_ddr3_pll "pll0"
Info: p0: Generating clock pair generator
Info: p0: Generating q_sys_ddr3_p0_altdqdqs
Info: p0: "ddr3" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: s0: Error during execution of "{E:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{E:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: /mnt/e/intelfpga/21.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../q_sys_ddr3_s0_AC_ROM.hex -inst_rom ../q_sys_ddr3_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000000000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000000100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 2021  Intel Corporation. All rights reserved.
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../q_sys_ddr3_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../q_sys_ddr3_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Makefile:27: recipe for target 'mc' failed
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred     while executing "error "An error occurred""     (procedure "_error" line 8)     invoked from within "_error "Cannot find $seq_file""     ("if" then script line 2)     invoked from within "if {[file exists $seq_file] == 0} { 		_error "Cannot find $seq_file" 	}"     (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)     invoked from within "alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""     invoked from within "set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"     ("if" then script line 2)     invoked from within "if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} { 		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."     (procedure "generate_qsys_sequencer_sw" line 943)     invoked from within "generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."     invoked from within "set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."     ("if" else script line 2)     invoked from within "if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} { 		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."     (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)     invoked from within "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"     invoked from within "set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"     (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)     invoked from within "alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG"     invoked from within "foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG] { 		set file_name [file tail $generate..."     (procedure "generate_verilog_sim" line 7)     invoked from within "generate_verilog_sim q_sys_ddr3_s0"
Info: s0: "ddr3" instantiated altera_mem_if_ddr3_qseq "s0"
Error: Generation stopped, 481 or more modules remaining
Info: q_sys: Done "q_sys" with 71 modules, 255 files
Error: qsys-generate failed with exit code 1: 15 Errors, 4 Warnings
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=E:\Projects\MK666_MOD3\CONTROLLED_FILES\4524000-MOD3_CWI_NTS\4524000_SUBRACK\4524320_DIGITIZER\4524320-10_DIGITIZER_PXIe\FPGA_v21\q_sys\q_sys.spd --output-directory=E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=E:\Projects\MK666_MOD3\CONTROLLED_FILES\4524000-MOD3_CWI_NTS\4524000_SUBRACK\4524320_DIGITIZER\4524320-10_DIGITIZER_PXIe\FPGA_v21\q_sys\q_sys.spd --output-directory=E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/ directory:
Info: 	mentor/msim_setup.tcl
Info: Generating the following file(s) for VCS simulator in E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/ directory:
Info: 	synopsys/vcs/vcs_setup.sh
Info: Generating the following file(s) for VCSMX simulator in E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/ directory:
Info: 	synopsys/vcsmx/synopsys_sim.setup
Info: 	synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/ directory:
Info: 	cadence/cds.lib
Info: 	cadence/hdl.var
Info: 	cadence/ncsim_setup.sh
Info: 	17 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/ directory:
Info: 	aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate E:\Projects\MK666_MOD3\CONTROLLED_FILES\4524000-MOD3_CWI_NTS\4524000_SUBRACK\4524320_DIGITIZER\4524320-10_DIGITIZER_PXIe\FPGA_v21\q_sys.qsys --synthesis=VERILOG --output-directory=E:\Projects\MK666_MOD3\CONTROLLED_FILES\4524000-MOD3_CWI_NTS\4524000_SUBRACK\4524320_DIGITIZER\4524320-10_DIGITIZER_PXIe\FPGA_v21\q_sys\synthesis --family="Cyclone V" --part=5CGTFD9E5F35C7
Progress: Loading FPGA_v21/q_sys.qsys
Progress: Reading input file
Progress: Adding clk_100 [clock_source 21.1]
Progress: Parameterizing module clk_100
Progress: Adding clk_50 [clock_source 21.1]
Progress: Parameterizing module clk_50
Progress: Adding clk_pciecore [clock_source 21.1]
Progress: Parameterizing module clk_pciecore
Progress: Adding ddr3 [altera_mem_if_ddr3_emif 21.1]
Progress: Parameterizing module ddr3
Progress: Adding mbox_msg [altera_avalon_mailbox_simple 21.1]
Progress: Parameterizing module mbox_msg
Progress: Adding mm_clock_crossing_bridge_0 [altera_avalon_mm_clock_crossing_bridge 21.1]
Progress: Parameterizing module mm_clock_crossing_bridge_0
Progress: Adding mm_clock_crossing_bridge_1 [altera_avalon_mm_clock_crossing_bridge 21.1]
Progress: Parameterizing module mm_clock_crossing_bridge_1
Progress: Adding mm_clock_crossing_bridge_2 [altera_avalon_mm_clock_crossing_bridge 21.1]
Progress: Parameterizing module mm_clock_crossing_bridge_2
Progress: Adding msgdma [altera_msgdma 21.1]
Progress: Parameterizing module msgdma
Progress: Adding onchip_mem [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module onchip_mem
Progress: Adding pcie [altera_pcie_cv_hip_avmm 21.1]
Progress: Parameterizing module pcie
Progress: Adding pio_calctrl [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calctrl
Progress: Adding pio_calword_00 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_00
Progress: Adding pio_calword_01 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_01
Progress: Adding pio_calword_02 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_02
Progress: Adding pio_calword_03 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_03
Progress: Adding pio_calword_04 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_04
Progress: Adding pio_calword_05 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_05
Progress: Adding pio_calword_06 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_06
Progress: Adding pio_calword_07 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_07
Progress: Adding pio_calword_08 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_08
Progress: Adding pio_calword_09 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_09
Progress: Adding pio_calword_10 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_10
Progress: Adding pio_calword_11 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_11
Progress: Adding pio_calword_12 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_12
Progress: Adding pio_calword_13 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_13
Progress: Adding pio_calword_14 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_14
Progress: Adding pio_calword_15 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_15
Progress: Adding pio_calword_16 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_16
Progress: Adding pio_calword_17 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_17
Progress: Adding pio_calword_18 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_18
Progress: Adding pio_calword_19 [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_calword_19
Progress: Adding pio_error [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_error
Progress: Adding pio_firmware_rev [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_firmware_rev
Progress: Adding pio_fram_status [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_fram_status
Progress: Adding pio_io_busy [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_io_busy
Progress: Adding pio_ioctrl [altera_avalon_pio 21.1]
Progress: Parameterizing module pio_ioctrl
Progress: Adding xcvr_reconfig [alt_xcvr_reconfig 19.1]
Progress: Parameterizing module xcvr_reconfig
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: q_sys.ddr3: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Warning: q_sys.ddr3.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
Info: q_sys.msgdma: Response information port is disabled. Enable the response port if data transfer information is required by host
Info: q_sys.pcie: The application clock frequency (pld_clk) is 125 Mhz
Info: q_sys.pcie: 5 reconfiguration interfaces are required for connection to the external reconfiguration controller
Info: q_sys.pcie: Family: Cyclone V
Info: q_sys.pcie: Credit allocation in the 6K bytes receive buffer:
Info: q_sys.pcie: Posted    : header=1  data=16
Info: q_sys.pcie: Non posted: header=1  data=0
Info: q_sys.pcie: Completion: header=73 data=293
Info: q_sys.pcie: TXS ADDRESS WIDTH is 32
Info: q_sys.pio_calword_00: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_01: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_02: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_03: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_04: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_05: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_06: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_07: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_08: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_09: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_10: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_11: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_12: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_13: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_14: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_15: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_16: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_17: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_18: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_calword_19: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_error: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_firmware_rev: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_fram_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.pio_io_busy: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: q_sys.xcvr_reconfig: reconfig_from_xcvr port width is 5*46 bits
Info: q_sys.xcvr_reconfig: reconfig_to_xcvr port width is 5*70 bits
Warning: q_sys.ddr3: ddr3.pll_sharing must be exported, or connected to a matching conduit.
Info: q_sys: Generating q_sys "q_sys" for QUARTUS_SYNTH
Info: ddr3: "q_sys" instantiated altera_mem_if_ddr3_emif "ddr3"
Info: mbox_msg: "q_sys" instantiated altera_avalon_mailbox_simple "mbox_msg"
Info: mm_clock_crossing_bridge_0: "q_sys" instantiated altera_avalon_mm_clock_crossing_bridge "mm_clock_crossing_bridge_0"
Info: msgdma: "q_sys" instantiated altera_msgdma "msgdma"
Info: onchip_mem: Starting RTL generation for module 'q_sys_onchip_mem'
Info: onchip_mem:   Generation command is [exec E:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga/21.1/quartus/bin64/perl/lib -I E:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I E:/intelfpga/21.1/quartus/sopc_builder/bin -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=q_sys_onchip_mem --dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0018_onchip_mem_gen/ --quartus_dir=E:/intelfpga/21.1/quartus --verilog --config=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0018_onchip_mem_gen//q_sys_onchip_mem_component_configuration.pl  --do_build_sim=0  ]
Info: onchip_mem: Done RTL generation for module 'q_sys_onchip_mem'
Info: onchip_mem: "q_sys" instantiated altera_avalon_onchip_memory2 "onchip_mem"
Info: pcie: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
Info: pcie: add_fileset_file ./sv_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_xcvr.sv
Info: pcie: add_fileset_file ./sv_reconfig_bundle_to_ip.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_ip.sv
Info: pcie: add_fileset_file ./sv_reconfig_bundle_merger.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_merger.sv
Info: pcie: add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv
Info: pcie: add_fileset_file ./av_xcvr_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm_csr.sv
Info: pcie: add_fileset_file ./av_tx_pma_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma_ch.sv
Info: pcie: add_fileset_file ./av_tx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_tx_pma.sv
Info: pcie: add_fileset_file ./av_rx_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_rx_pma.sv
Info: pcie: add_fileset_file ./av_pma.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pma.sv
Info: pcie: add_fileset_file ./av_pcs_ch.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs_ch.sv
Info: pcie: add_fileset_file ./av_pcs.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_pcs.sv
Info: pcie: add_fileset_file ./av_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_avmm.sv
Info: pcie: add_fileset_file ./av_xcvr_native.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_native.sv
Info: pcie: add_fileset_file ./av_xcvr_plls.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_plls.sv
Info: pcie: add_fileset_file ./av_xcvr_data_adapter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_data_adapter.sv
Info: pcie: add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv
Info: pcie: add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv
Info: pcie: add_fileset_file ./av_hssi_8g_rx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_rx_pcs_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_8g_tx_pcs_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_8g_tx_pcs_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_common_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pcs_pma_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_common_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_common_pld_pcs_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_pipe_gen1_2_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_pipe_gen1_2_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_rx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pcs_pma_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_rx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_rx_pld_pcs_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_tx_pcs_pma_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pcs_pma_interface_rbc.sv
Info: pcie: add_fileset_file ./av_hssi_tx_pld_pcs_interface_rbc.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/rbc/av_hssi_tx_pld_pcs_interface_rbc.sv
Info: pcie: add_fileset_file ./alt_reset_ctrl_lego.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_lego.sv
Info: pcie: add_fileset_file ./alt_reset_ctrl_tgx_cdrauto.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_reset_ctrl_tgx_cdrauto.sv
Info: pcie: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_common_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common_h.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_common.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_common.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_pcs8g_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g_h.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_pcs8g.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_pcs8g.sv
Info: pcie: add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv
Info: pcie: add_fileset_file ./alt_xcvr_mgmt2dec.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_mgmt2dec.sv
Info: pcie: add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v
Info: pcie: add_fileset_file ./av_xcvr_emsip_adapter.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_emsip_adapter.sv
Info: pcie: add_fileset_file ./av_xcvr_pipe_native_hip.sv SYSTEM_VERILOG PATH ../../altera_pcie_pipe/av/av_xcvr_pipe_native_hip.sv
Info: pcie: "q_sys" instantiated altera_pcie_cv_hip_avmm "pcie"
Info: pio_calctrl: Starting RTL generation for module 'q_sys_pio_calctrl'
Info: pio_calctrl:   Generation command is [exec E:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga/21.1/quartus/bin64/perl/lib -I E:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I E:/intelfpga/21.1/quartus/sopc_builder/bin -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_pio_calctrl --dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0020_pio_calctrl_gen/ --quartus_dir=E:/intelfpga/21.1/quartus --verilog --config=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0020_pio_calctrl_gen//q_sys_pio_calctrl_component_configuration.pl  --do_build_sim=0  ]
Info: pio_calctrl: Done RTL generation for module 'q_sys_pio_calctrl'
Info: pio_calctrl: "q_sys" instantiated altera_avalon_pio "pio_calctrl"
Info: pio_calword_00: Starting RTL generation for module 'q_sys_pio_calword_00'
Info: pio_calword_00:   Generation command is [exec E:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga/21.1/quartus/bin64/perl/lib -I E:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I E:/intelfpga/21.1/quartus/sopc_builder/bin -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_pio_calword_00 --dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0021_pio_calword_00_gen/ --quartus_dir=E:/intelfpga/21.1/quartus --verilog --config=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0021_pio_calword_00_gen//q_sys_pio_calword_00_component_configuration.pl  --do_build_sim=0  ]
Info: pio_calword_00: Done RTL generation for module 'q_sys_pio_calword_00'
Info: pio_calword_00: "q_sys" instantiated altera_avalon_pio "pio_calword_00"
Info: pio_error: Starting RTL generation for module 'q_sys_pio_error'
Info: pio_error:   Generation command is [exec E:/intelfpga/21.1/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga/21.1/quartus/bin64/perl/lib -I E:/intelfpga/21.1/quartus/sopc_builder/bin/europa -I E:/intelfpga/21.1/quartus/sopc_builder/bin -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- E:/intelfpga/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_pio_error --dir=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0022_pio_error_gen/ --quartus_dir=E:/intelfpga/21.1/quartus --verilog --config=C:/Users/IBUYPO~1/AppData/Local/Temp/alt8942_1067885789276101362.dir/0022_pio_error_gen//q_sys_pio_error_component_configuration.pl  --do_build_sim=0  ]
Info: pio_error: Done RTL generation for module 'q_sys_pio_error'
Info: pio_error: "q_sys" instantiated altera_avalon_pio "pio_error"
Info: xcvr_reconfig: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_h.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_h.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_cal_seq.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_cal_seq.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_cif.sv SYSTEM_VERILOG PATH .//alt_xreconf_cif.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_uif.sv SYSTEM_VERILOG PATH .//alt_xreconf_uif.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_basic_acq.sv SYSTEM_VERILOG PATH .//alt_xreconf_basic_acq.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_analog.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_analog_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_analog_datactrl_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_datactrl_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_analog_rmw_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_rmw_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xreconf_analog_ctrlsm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_ctrlsm.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_offset_cancellation.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_offset_cancellation_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_eyemon.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_eyemon/alt_xcvr_reconfig_eyemon.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dfe.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dfe/alt_xcvr_reconfig_dfe.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_adce.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_adce/alt_xcvr_reconfig_adce.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dcd.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dcd_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dcd_cal_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_cal_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_dcd_control_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_control_av.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/alt_xcvr_reconfig_mif.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_mif_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_ctrl.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_mif_avmm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_avmm.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/alt_xcvr_reconfig_pll.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_pll_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll_ctrl.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_direct.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_direct/alt_xcvr_reconfig_direct.sv
Info: xcvr_reconfig: add_fileset_file ./alt_arbiter_acq.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_arbiter_acq.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_xcvr_reconfig_basic.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_l2p_addr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_addr.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_l2p_ch.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_ch.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_l2p_rom.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_rom.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_lif_csr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif_csr.sv
Info: xcvr_reconfig: add_fileset_file ./av_xrbasic_lif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xcvr_reconfig_basic.sv
Info: xcvr_reconfig: add_fileset_file ./av_xcvr_reconfig.sdc OTHER PATH .//av_xcvr_reconfig.sdc
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_m2s.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_m2s.sv
Info: xcvr_reconfig: add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v
Info: xcvr_reconfig: add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv
Info: xcvr_reconfig: add_fileset_file ./sv_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_basic.sv
Info: xcvr_reconfig: add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv
Info: xcvr_reconfig: add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv
Info: xcvr_reconfig: "q_sys" instantiated alt_xcvr_reconfig "xcvr_reconfig"
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/synthesis/submodules/altera_xcvr_functions.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/synthesis/submodules/av_xcvr_h.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/synthesis/submodules/alt_xcvr_resync.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/synthesis/submodules/altera_wait_generate.v
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/synthesis/submodules/alt_xcvr_csr_selector.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/synthesis/submodules/av_reconfig_bundle_to_basic.sv
Info: Reusing file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/synthesis/submodules/av_reconfig_bundle_to_xcvr.sv
Warning: Overwriting different file E:/Projects/MK666_MOD3/CONTROLLED_FILES/4524000-MOD3_CWI_NTS/4524000_SUBRACK/4524320_DIGITIZER/4524320-10_DIGITIZER_PXIe/FPGA_v21/q_sys/synthesis/submodules/plain_files.txt
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "q_sys" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_1: "q_sys" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_022: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_023: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_024: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_025: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_026: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_2: "q_sys" instantiated altera_mm_interconnect "mm_interconnect_2"
Info: irq_mapper: "q_sys" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "q_sys" instantiated altera_reset_controller "rst_controller"
Info: pll0: "ddr3" instantiated altera_mem_if_ddr3_pll "pll0"
Info: p0: Generating clock pair generator
Info: p0: Generating q_sys_ddr3_p0_altdqdqs
Info: p0: 
Info: p0: *****************************
Info: p0: 
Info: p0: Remember to run the q_sys_ddr3_p0_pin_assignments.tcl
Info: p0: script after running Synthesis and before Fitting.
Info: p0: 
Info: p0: *****************************
Info: p0: 
Info: p0: "ddr3" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: s0: Error during execution of "{E:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{E:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: /mnt/e/intelfpga/21.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../q_sys_ddr3_s0_AC_ROM.hex -inst_rom ../q_sys_ddr3_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000000000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000000100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 2021  Intel Corporation. All rights reserved.
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../q_sys_ddr3_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../q_sys_ddr3_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Makefile:27: recipe for target 'mc' failed
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred     while executing "error "An error occurred""     (procedure "_error" line 8)     invoked from within "_error "Cannot find $seq_file""     ("if" then script line 2)     invoked from within "if {[file exists $seq_file] == 0} { 		_error "Cannot find $seq_file" 	}"     (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)     invoked from within "alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""     invoked from within "set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"     ("if" then script line 2)     invoked from within "if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} { 		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."     (procedure "generate_qsys_sequencer_sw" line 943)     invoked from within "generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."     invoked from within "set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."     ("if" else script line 2)     invoked from within "if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} { 		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."     (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)     invoked from within "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"     invoked from within "set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"     (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)     invoked from within "alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"     invoked from within "foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] { 		set file_name [file tail $genera..."     (procedure "generate_synth" line 8)     invoked from within "generate_synth q_sys_ddr3_s0"
Info: s0: "ddr3" instantiated altera_mem_if_ddr3_qseq "s0"
Error: Generation stopped, 481 or more modules remaining
Info: q_sys: Done "q_sys" with 71 modules, 175 files
Error: qsys-generate failed with exit code 1: 15 Errors, 4 Warnings
Info: Finished: Create HDL design files for synthesis