module PwmCtrl( input RST_N , input CLK , input PUSH0 , input PUSH1 , input DATA0 , output LED0 , output LED1 , output LED2 , output LED3 , output LED4 , output LED5 , output LED6 , output LED7 , output [0:6] HEX0 , output [0:6] HEX1 , output [0:6] HEX2 , output [0:6] HEX3 , output nCSO , output ASDO , output DCLK ); reg [27:0] counter0 ; reg [27:0] counter1 ; reg [27:0] counter2 ; reg [27:0] counter3 ; reg [27:0] counter4 ; reg [27:0] counter5 ; reg [27:0] counter6 ; reg [27:0] counter7 ; wire [27:0] Period0 ; wire [27:0] Decode0 ; wire [27:0] Period1 ; wire [27:0] Decode1 ; wire [27:0] Period2 ; wire [27:0] Decode2 ; wire [27:0] Period3 ; wire [27:0] Decode3 ; wire [27:0] Period4 ; wire [27:0] Decode4 ; wire [27:0] Period5 ; wire [27:0] Decode5 ; wire [27:0] Period6 ; wire [27:0] Decode6 ; wire [27:0] Period7 ; wire [27:0] Decode7 ; wire counter0_clr; wire counter0_dec; wire counter1_clr; wire counter1_dec; wire counter2_clr; wire counter2_dec; wire counter3_clr; wire counter3_dec; wire counter4_clr; wire counter4_dec; wire counter5_clr; wire counter5_dec; wire counter6_clr; wire counter6_dec; wire counter7_clr; wire counter7_dec; //CLK = 50Mhz, counter0 can regist 2^28-1 to 0; //For PWM0 always @(posedge CLK, negedge RST_N) begin if(RST_N == 1'b0) counter0 <= 1'b0; else begin if(counter0_clr == 1'b1) counter0 <= 1'b0; else counter0 <= counter0 + 1'b1; end end assign counter0_clr = (counter0 >= Period0) ? 1'b1 : 1'b0; assign counter0_dec = (counter0 < Decode0) ? 1'b1 : 1'b0; assign LED0 = counter0_dec ; //For PWM1 always @(posedge CLK, negedge RST_N) begin if(RST_N == 1'b0) counter1 <= 1'b0; else begin if(counter1_clr == 1'b1) counter1 <= 1'b0; else counter1 <= counter1 + 1'b1; end end assign counter1_clr = (counter1 >= Period1) ? 1'b1 : 1'b0; assign counter1_dec = (counter1 < Decode1) ? 1'b1 : 1'b0; assign LED1 = counter1_dec ; //For PWM2 always @(posedge CLK, negedge RST_N) begin if(RST_N == 1'b0) counter2 <= 1'b0; else begin if(counter2_clr == 1'b1) counter2 <= 1'b0; else counter2 <= counter2 + 1'b1; end end assign counter2_clr = (counter2 >= Period2) ? 1'b1 : 1'b0; assign counter2_dec = (counter2 < Decode2) ? 1'b1 : 1'b0; assign LED2 = counter2_dec ; //For PWM3 always @(posedge CLK, negedge RST_N) begin if(RST_N == 1'b0) counter3 <= 1'b0; else begin if(counter3_clr == 1'b1) counter3 <= 1'b0; else counter3 <= counter3 + 1'b1; end end assign counter3_clr = (counter3 >= Period3) ? 1'b1 : 1'b0; assign counter3_dec = (counter3 < Decode3) ? 1'b1 : 1'b0; assign LED3 = counter3_dec ; //For PWM4 always @(posedge CLK, negedge RST_N) begin if(RST_N == 1'b0) counter4 <= 1'b0; else begin if(counter4_clr == 1'b1) counter4 <= 1'b0; else counter4 <= counter4 + 1'b1; end end assign counter4_clr = (counter4 >= Period4) ? 1'b1 : 1'b0; assign counter4_dec = (counter4 < Decode4) ? 1'b1 : 1'b0; assign LED4 = counter4_dec ; //For PWM5 always @(posedge CLK, negedge RST_N) begin if(RST_N == 1'b0) counter5 <= 1'b0; else begin if(counter5_clr == 1'b1) counter5 <= 1'b0; else counter5 <= counter5 + 1'b1; end end assign counter5_clr = (counter5 >= Period5) ? 1'b1 : 1'b0; assign counter5_dec = (counter5 < Decode5) ? 1'b1 : 1'b0; assign LED5 = counter5_dec ; //For PWM6 always @(posedge CLK, negedge RST_N) begin if(RST_N == 1'b0) counter6 <= 1'b0; else begin if(counter6_clr == 1'b1) counter6 <= 1'b0; else counter6 <= counter6 + 1'b1; end end assign counter6_clr = (counter6 >= Period6) ? 1'b1 : 1'b0; assign counter6_dec = (counter6 < Decode6) ? 1'b1 : 1'b0; assign LED6 = counter6_dec ; //For PWM7 always @(posedge CLK, negedge RST_N) begin if(RST_N == 1'b0) counter7 <= 1'b0; else begin if(counter7_clr == 1'b1) counter7 <= 1'b0; else counter7 <= counter7 + 1'b1; end end assign counter7_clr = (counter7 >= Period7) ? 1'b1 : 1'b0; assign counter7_dec = (counter7 < Decode7) ? 1'b1 : 1'b0; assign LED7 = counter7_dec ; nios2e u0( .clk_clk (CLK), // clk.clk .reset_reset_n (RST_N), // reset.reset_n .period0_external_connection_export (Period0), // period0_external_connection.export .decode0_external_connection_export (Decode0), // decode0_external_connection.export .hex3_external_connection_export (HEX3), // hex0_external_connection.export .hex2_external_connection_export (HEX2), // hex0_external_connection.export .hex1_external_connection_export (HEX1), // hex0_external_connection.export .hex0_external_connection_export (HEX0), // hex0_external_connection.export .push_external_connection_export ({PUSH1,PUSH0}), // push_external_connection.export .decode7_external_connection_export (Decode7), // decode7_external_connection.export .period7_external_connection_export (Period7), // period7_external_connection.export .decode6_external_connection_export (Decode6), // decode6_external_connection.export .period6_external_connection_export (Period6), // period6_external_connection.export .decode5_external_connection_export (Decode5), // decode5_external_connection.export .period5_external_connection_export (Period5), // period5_external_connection.export .decode4_external_connection_export (Decode4), // decode4_external_connection.export .period4_external_connection_export (Period4), // period4_external_connection.export .decode3_external_connection_export (Decode3), // decode3_external_connection.export .period3_external_connection_export (Period3), // period3_external_connection.export .decode2_external_connection_export (Decode2), // decode2_external_connection.export .period2_external_connection_export (Period2), // period2_external_connection.export .decode1_external_connection_export (Decode1), // decode1_external_connection.export .period1_external_connection_export (Period1), // period1_external_connection.export .epcs_flash_controller_0_external_dclk (DLCK), // epcs_flash_controller_0_external.dclk .epcs_flash_controller_0_external_sce (nCSO), // .sce .epcs_flash_controller_0_external_sdo (ASDO), // .sdo .epcs_flash_controller_0_external_data0 (DATA0) // .data0 ); endmodule