Arria 10 Transceiver Register Map（UG-01143 ）にて 詳細機能をレジスタにて変更できると理解しています。 もし理解が正しい場合、いくつか設定したい項目があるのですが、 具体的な変更手順をご教示いただけないでしょうか。 例えば、a10_registermap.xlsxのExtended Register mapのAddress:C.0x120 vcm_sel を変更したいのです。 お手数をおかけいたしますが、宜しくお願い致します。

[Deshi_Intel]

hi,

I presume you are referring to Arria 10 NativePHY IP. In the IP, there is reconfiguration bus interface that user can use to access the register read/write of transceiver channel.

reconfiguration bus interface is build base on Altera Avalon Memory Map interface.

• You can learn more on how to access this interface via below Avalon Specification document
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
• The idea will be like you specify the Avalon address location, perform write command follow by sending the write data on the Avalon data bus.

Thanks.

Regards,

dlim

[章安部井0]

Dear dlim

this is abei.

thank you for your answer.

I will study control using the Avalon bus based on the information by your answer.

If it is difficult for us, please support.

BR

[Deshi_Intel]

HI Abei,

Sure, I will do my best to help you.

Thanks.

Regards,

Deshi

[Deshi_Intel]

HI Abei,

I have not hear back from you for some time.

For now, I am setting this case to closure first.

Feel free to file new forum thread if you have any enquiry in future.

Thanks.

Regards,

dlim

[章安部井0]

Dear dlim

this is abei.

I'm sorry , I delayed repry.

I tried changing the XCVR register settings.

I was able to adjust the offset voltage.

Thank you very much.

BR

[Deshi_Intel]

HI Abei,

No problem. It's good to know you are getting thing working in your project.

Alright, I am setting this case back to closure.

Feel free to file new forum thread if you have enquiry in future.

Thanks.

Regards,

dlim