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FPGA Agelix F-tile

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#**Error: (vsim-3043) Unresolved reference to 'eth_f_hw' in eth_f_hw.IP_INST[0.hw_ip_ top.dut.eth_f_0.sip_inst.rx_lane_desired_state.

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Hi,

Thanks for submitting the issue.

Would you mind to share your .qar file? So that I can try to debug the issue from my side.

Best regards,

Zi Ying

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