This was a huge week for the FPGA segment of the electronics industry, thanks to many of the announcements made at this week’s Intel Innovation event in San Jose, California. First, Intel is leveraging its manufacturing excellence with Intel 7 technology and its resilient, globe-spanning supply chain to extend the Intel® Agilex™ FPGA and SoC family in multiple directions simultaneously. Intel Agilex FPGAs already hold the industry’s leadership position for FPGA performance/watt. In addition, Intel announced a data converter-enabled FPGA portfolio that greatly extends the RF analog reach of FPGA technology to an industry-leading 64 gigasamples per second and 32 GHz of RF bandwidth. These new products support the strategic priorities that Intel has focused on for the FPGA industry: delivering leadership capabilities; a strong, resilient supply chain; and best-in-class user experience.
Since their introduction a few years ago, customers have used Intel Agilex FPGAs and SoCs in a growing number of applications with tremendous market acceptance of the original Intel Agilex FPGA and SoC families. Intel has expanded the Intel Agilex FPGA portfolio with an even wider selection of programmable-logic devices based on the Intel Agilex FPGA and SoC architecture, with additional new features and characteristics suited to an even wider range of applications.
This week, Intel met those application requirements with three major introductions including two new Intel Agilex device families and a data converter-enabled Direct RF FPGA portfolio that includes even more devices based on the Intel Agilex FPGA architecture. The two new Intel Agilex device families are the Intel® Agilex™ D-Series FPGAs and SoCs for midrange applications and a power-optimized, small footprint family of new Intel® Agilex™ FPGAs (code named Sundance Mesa). Both new Intel Agilex FPGA and SoC families share many of the successful architectural characteristics implemented in earlier Intel Agilex devices while introducing many new and unique features and capabilities.
Intel has taken advantage of the latest semiconductor process and packaging advances to create these new midrange and power-optimized Intel Agilex devices, which extend the Intel Agilex FPGA portfolio to lower logic densities, lower power consumption, and smaller form factors than previously offered. Intel is the only FPGA supplier that has access to its own manufacturing facilities. In addition to Intel’s own advanced semiconductor manufacturing and packaging technologies, the company also has access to a wide variety of other semiconductor process nodes from trusted partners. These global resources allow Intel to deliver best-in-class lead times of 12 to 16 weeks with predictable supplies of Intel Agilex FPGAs and Intel® Stratix® 10 FPGAs.
Today, Intel builds Intel Stratix 10 and Intel Agilex FPGAs and SoCs in the company’s own fabs, and will leverage these fabs for next-generation FPGA and SoC products as well. Intel knows that you need to have confidence in your suppliers’ reliability so we control the critical pieces of our Intel Agilex FPGA and Intel Stratix 10 FPGA supply chain, which gives us better flexibility and control to reliably deliver the products you need.
Previously introduced members of the Intel Agilex FPGA and SoC families are manufactured with the Intel 10 nm SuperFin technology, packaged with chiplets or “tiles” that add specialized I/O functions, all interconnected with Intel multi-die packaging technologies. The new Intel Agilex D-Series devices for midrange applications and the new power-optimized, small-footprint Intel Agilex devices are manufactured with advanced Intel 7 technology and cost-optimized, monolithic construction to deliver excellent performance with the low power consumption you need to meet the design requirements for an even wider range of applications.
Both new Intel Agilex device families inherit many strong and proven architectural features, including the second-generation Hyperflex clocking architecture and smartVID power-management technology, that led to the market success of earlier Intel Agilex FPGA families. These features significantly improve FPGA performance while reducing power consumption within the devices’ programmable-logic fabric.
The Intel FPGAs and SoCs introduced this week also incorporate architectural features that are new to the Intel Agilex device family, including hard intellectual property (IP) blocks such as:
- An upgraded Hard Processor System (HPS) that includes a dual-core Arm Cortex-A76 processor and a dual-core Arm Cortex-A55 processor
- Enhanced Digital Signal Processing (DSP) with AI Tensor Block with greater computational parallelism for AI workloads
- A Time-Sensitive Networking (TSN) block for precise control and synchronization of Ethernet traffic
- A MIPI D-PHY block that implements the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols
The Enhanced Digital Signal Processing (DSP) with AI Tensor Block within the FPGA fabric of these new Intel Agilex FPGAs and SoCs inherit the design of the variable-precision DSP blocks in the earlier Intel Agilex device families, which already offer AI capabilities. In addition, it adds features derived from the tensor block used in the Intel® Stratix® 10 NX FPGAs. The Enhanced DSP with AI Tensor Block introduces two new important operations: the tensor processing capability for AI and complex number support for signal processing applications such as FFTs and complex FIR filters.
The first mode enhances AI with the INT8 tensor mode, which provides twenty INT8 multiplications within one Enhanced DSP with AI Tensor Block, and increases INT8 compute density by 5x versus earlier Intel Agilex device families. The tensor mode uses a two-column tensor structure with both INT32 and FP32 cascade and accumulation capability, and also supports a block floating exponent for improved inference accuracy and low-precision training. In addition, the AI capability of the variable precision DSP functionality has also been enhanced. The vector mode has been upgraded from four INT9 multipliers to six INT9 multipliers. These modes are extremely useful for AI-centric tensor math and for various DSP applications.
The second new mode, the complex-number operation, doubles the performances of the tensor block when performing complex-number multiplication. Previously, two DSP blocks were needed for complex-number multiplication, but this new family of Intel Agilex FPGAs and SoCs can multiply 16-bit, fixed-point, complex numbers within one Enhanced DSP with AI Tensor Block.
The new Intel Direct RF FPGA portfolio provides RF designers with capabilities that are far beyond anything available in competing FPGAs. Like previous devices in the Intel Stratix 10 and Intel Agilex FPGA families, the Direct RF FPGA portfolio combines FPGA core die with function specific and general-purpose I/O tiles using Intel’s Embedded Multi-die Interconnect Bridge (EMIB), Advanced Interface Bus (AIB), and advanced heterogeneous multi-die packaging technologies. Different semiconductor tiles have provided these earlier Intel FPGAs with a variety of additional I/O functions including high-bandwidth memory (HBM) DRAM, PCIe 4.0 and 5.0, and 58/116 Gbps serial transceiver ports that allow these Intel FPGAs to interface with a wide variety of devices.
Devices in the new Direct RF FPGA portfolio now extend the I/O capabilities of the company’s FPGAs and SoCs into the analog/RF domain using RF analog-to-digital and digital-to-analog converter (ADC and DAC) chiplets, which have been co-developed with partner companies that are trusted members of the Intel supply chain. These ADC and DAC chiplets are capable of sample rates as fast as 64 gigasamples/second with up to 32 GHz of RF bandwidth. The RF ADC and DAC chiplets are assembled with FPGA die fabricated by Intel into packaged devices using Intel’s EMIB and AIB interconnect technologies. Tile-based design and the heterogeneous die-and-tile manufacturing approach to developing analog-enabled SoC FPGAs allow Intel to quickly address a broad array of analog signal processing applications in the RF domain.
Intel’s innovative use of chiplets enables another new capability that was announced this week: the first FPGAs supporting Compute Express Link, or CXL. Intel Agilex I-Series and M-Series FPGAs will offer this capability, with software support available now as part of the latest release of its FPGA development tools. CXL support is provided by the R-Tile chiplet in these FPGAs, which also delivers support for PCIe 5.0, the first such support in the industry as noted in the PCI-SIG integrator’s list. The CXL support provided by Intel Agilex FPGAs delivers 4X the bandwidth per port compared to competitive offerings, owing to the dedicated, optimized blocks supporting this feature in the R-Tile.
These new Intel FPGAs and SoCs all inherit one more very important element–Intel® Quartus® Prime Software–which delivers a best-in-class developer experience and a speed-grade advantage over competing products. In other words, the Intel Quartus software on average delivers faster mid-speed grade fabric performance compared to the highest-speed grade competing 7 nm FPGAs. This ability alone delivers a huge competitive advantage to Intel’s programmable logic customers.
However, the Intel Quartus Prime Software provides additional benefits that allow Intel customers to finish their designs more quickly and get to market faster. The Questa*-Intel® FPGA Edition, based on the Siemens EDA Questa Core simulator, delivers as much as 2.5X faster simulation for Verilog and 1.5X faster simulation for VHDL simulations when compared with previous Verilog/VHDL simulators. You can now employ different compilation strategies for different parts of your FPGA design and different stages in your design cycle. The Design Assistant in the Intel Quartus Prime Pro Edition Software runs 139 different design-rule checks to find issues and close timing quicker. Intel has taken care to give all the IP available in Intel Quartus Prime Software a similar look and feel so that all the IP presents as familiar and easy to use. This too speeds development by reducing the time needed to learn and understand the IP. Finally, Intel has incorporated the Ashling* RiscFree IDE for Intel® FPGAs for development and debug on both the Nios® V soft processors and the Arm-based hard processors in Intel SoC FPGAs at no additional cost.
The Arm* Development Studio for Intel® SoC FPGAs continues to be the industry standard embedded development tool offered by Intel at a value price point so code developers can use familiar tools to develop and debug software for the Arm processors incorporated in Intel SoCs.
In addition to these new FPGA and SoC introductions, Intel also announced the Intel® Tofino™ Expandable Architecture, which greatly enhances the capabilities of Intel® Tofino™ Intelligent Fabric Processors (IFPs) by enabling Intel® Xeon® CPUs and hardware accelerators–such as Intel® FPGAs and Intel® Infrastructure Processing Units (IPUs) – to increase the Intel® Tofino™ IFP’s switch and router table and packet buffer capacity by two orders of magnitude when compared to a data-center-focused ASIC switch chip.
As Intel CEO Pat Gelsinger stated:
“We are focused on four areas to deliver leadership products and digital innovations in the years ahead: one, be the leader in every category in which we compete; two, execute flawlessly to our commitments; three, passionately innovate with boldness and speed; and four, reignite our culture to attract and motivate the best engineers and technologists on the planet.”
Led by Gelsinger, Intel has been very clear that we intend to be the leader in semiconductor capacity by:
- Making significant capital and training investments all over the world
- Investing in additional substrate and chip-packaging capacity
- Investing in the development of leading-edge nodes
- Investing in older legacy nodes that are just as important for many of our customers
The FPGA and SoC advances announced this week at Intel Innovation provide multiple examples of Intel delivering on these commitments made to the company’s customers.
For more information on the Intel Agilex D-Series devices, read the blog.
For more information on the new power-efficient, small-footprint Intel Agilex devices, read the blog.
For more information on the analog-enabled Intel FPGAs, read the blog.
For more information on Intel FPGA support for CXL, watch the video.
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