Are you designing systems that need PCI Express (PCIe) 5.0 capability? If so, you’ll want to take a good look at the Intel® Agilex™ I- and M-series FPGAs and SoC FPGAs because these programmable-logic devices incorporate PCIe 5.0 capabilities and have just passed PCI-SIG compliance tests. They are now listed on the PCI-SIG integrators list as a PCIe 5.0 x16 Endpoint. If there are two things you should remember about Intel Agilex FPGAs with respect to PCIe5.0, it’s this: these devices offer you more and faster PCIe 5.0 lanes than competing programmable logic devices and they provide some extremely useful hard and soft IP for making PCIe 5.0 work smoothly in systems.
- 2X more bandwidth per port vs. Versal Premium FPGAs
- 50% more total bandwidth vs. Achronix FPGAs
All Intel Agilex FPGAs incorporate tiles (chiplets) to add advanced I/O capabilities. In particular, an R-tile provides PCIe 5.0 capabilities to certain Intel Agilex I- and M-series FPGAs and SoC FPGAs, which incorporate from one or more R-tiles. That translates into FPGAs that support one or more PCIe 5.0 x16 interface ports. Each of these Intel Agilex FPGA PCIe 5.0 x16 ports can be split into two PCIe 5.0 x8 ports or four PCIe 5.0 x4 ports, implemented internally with hardened PCIe 5.0 x16, x8, and x4 controllers. Intel Agilex FPGAs’ PCIe 5.0 capabilities exceed those available on competing programmable logic devices in both aggregate PCIe 5.0 transfer rates and in the number of available PCIe 5.0 lanes.
Intel Agilex FPGAs’ PCIe ports feature:
- A complete hard IP protocol stack that implements Transaction, Data Link, and Physical Layers
- Support for PHY Interface for the PCI Express* (PIPE) mode, which is direct pass-through access to the PCIe SerDes transceivers for PCIe implementations based on soft IP
- Native support for PCIe 3.0, 4.0, and 5.0 configurations and support for PCIe 1.0 and 2.0 configurations via link down-training
- Root Port (RP), Endpoint (EP), and TLP Bypass (BP) modes
- Support for various multilink EP and RP modes for narrower x8, x4 configurations
The hard IP incorporated into the R-tiles allows Intel Agilex FPGAs and SoC FPGAs to provide additional multifunction and virtualization features including:
- SR-IOV support with 8 physical functions (PFs) and 2048 virtual functions (VFs) per each Endpoint
- VirtIO support via a configuration intercept interface
- Scalable I/O and shared virtual memory (SVM) support (future)
For a complete list of features, visit the R-tile page on Intel.com.
Intel Agilex FPGA and SoC FPGA development tools also support PCIe IP debugging through a PCIe-specific toolkit that provides protocol and link status information, PMA register access, and eye-viewing capabilities.
Note: The R-tiles incorporated into Intel Agilex FPGAs also support the CXL coherent I/O protocol.
To see the recommended FPGA development kit with PCIe 5.0 capability, click here.
For more information about the Intel Agilex FPGA and SoC FPGA families, click here.