Address Mirroring of command-address lines in memory down configuration (dual rank)

[Raj_Kr]

Hi,

I am reposting the same un-answered query as I was re-directed to this support portal from embedded processor.

Query

We have used Intel Xeon Processor D-1746TER in our design and completed the schematic & layout design part.

We have connected 36 DDR4 (with ECC) devices on 2 channels in dual rank (x8) configuration.

In the reference document "576513_Idaville_LCC_PDG_Rev2_2"  page- 212, it is stated that "Address mirroring is allowed on second rank only for certain pins. SPD Bit 0 of Byte131
needs to be modified accordingly." 

Now we have a doubt related to this-

Which pins are allowed for address mirroring? we could not find any list of such address pins which can be address mirrored in Intel's reference design documents.

So, Please share us the details of those address pins.

Please try to answer asap.

Thank You 

Raj Kumar

[Raj_Kr]

Hi,

Gentle Reminder!

I am still awaiting for the response from Intel Support Side.

Please help me out with this ASAP.

Thank You 

Raj Kumar

[Diego_INTEL]

Hello @Raj_Kr,

Thank you for contacting Intel Embedded Community.

My apologies for the delay, busy weeks. I have been looking for this and you are right, the documentation doesn't state which pins are supported, but being related to memory, I think it can be found in one of the Jedec Standards.

From the EDS Vol1, document #595910, on section "11.7 - DDR4 SPD SMBus":

"For additional information about the SPD architecture and format, refer to the JEDEC Standard No. 21-C, SPD4.1.2.L, Annex L:
Serial Presence Detect (SPD) for DDR4 SDRAM Modules (https://www.jedec.org)."

https://www.jedec.org/category/technology-focus-area/memory-configurations-jesd21-c

Also, I can recommend following documents:

Document #773050 - Idaville RAS Features Introduction

Document #648564 - Idaville RAS Validation Guide

Document #551534 - Brickland Platform RAS – Memory Address Range Mirroring Integration and Validation Guide

Best regards,

@Diego_INTEL