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Hi there,
I am a hardware developer.
Our customer wanted us to show ATOM E3950 emmc AC timing interface in HS400 mode that the setup and hold time got margin in design.
We checked from spec Doc #557555 and JEDEC emmc spec v5.1.
We figured out the tDVW = 2.399nsec min., tISU requires 0.4nsec min.
Can Intel FAE give me some support on how to prove that the interface timing can fulfill the JEDEC requirement?
Our customer wanted to confirm the design is without timing error.
Please help to review and give us comment on our understanding.
Best Regards
Jackie Wong
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Hello @JackieWong
Thank you for posting on the Intel® communities.
We understand that you have some inquiries regarding Intel Atom® x7-E3950 Processor (Embedded CPU).
We have a forum for those specific products and questions so we are moving it to the Embedded Intel Atom® Processors Forum so it can get answered more quickly.
Best regards,
Andrew G.
Intel Customer Support Technician
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Hello, @JackieWong:
Thank you for contacting Intel Embedded Community.
We sent an email to the email address associated with this account with information that may help you.
Best regards,
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