Configuring PHY management registers

[Aidan4]

Looking for any drivers intel might provide for setting a 1000 BASE-T management register in the PHY to configure the device for specific IEEE test modes.

IEEE 802.3 Table 40-3 indicates that setting management register 9 bits 15:13 sets the test mode of a device.

I believe this can be accessed through the GMII interface. Does intel provide any guidance on accessing and configuring these registers?

Thanks, 

-Aidan

[Azeem_Intel]

Hi Aidan4,

Greetings for the day!

Hope you are doing well. We request that you please visit the link provided below. If you do not find any resolution, please contact us with a more detailed query.

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[Azeem_Intel]

Hi Aidan4,

Greetings for the day!

This is the first follow-up regarding the issue (Configuring PHY management registers) you reported to us.

We wanted to inquire whether you had the opportunity to review the plan of action (POA) we provided.

Please do not hesitate in contact us, we are more than glad to assist you.

Best Regards,

Azeem_Intel

[Azeem_Intel]

Hi Hi Aidan4,

Greetings for the day!

This is the second follow-up regarding the reported issue. We're eager to ensure a swift resolution and would appreciate any updates or additional information you can provide.

Please do not hesitate in contact us, we are more than glad to assist you.

Best Regards,

Azeem_Intel

[Azeem_Intel]

Hi Aidan4,

Hope you are doing well!

This is the third follow-up regarding the reported issue. We're committed to ensuring a swift resolution and would greatly appreciate any updates or additional information you can provide.

If we don't hear back from you soon, we'll assume the issue has been resolved and will proceed to close the case.

Best Regards,

Azeem_Intel