About dynamic reconfiguration of transceiver

[lambert_yu]

Hi all,

      I have one problem:

      1. If I switch one data rate to another data rate for transceiver directly, It can works normally.

      2. But, for another case , the result is not same:

      Operation :  For current data rate, if I re-download the .mif file of current data rate(it includes followed related reset and usr recalibration), when cal_busy is low and reset signals are all released, related plls are all locked and CDR are all locked to data, the transceiver can be used to read or write data. after some time, I switch one data rate to another data rate (more high compared to former) (it also includes followed related reset and usr recalibration),  after cal_busy is low and reset signals are all released, related plls are all locked and CDR are all locked to data, though that I monitor the lockedtodata is not  desserted (I think that CDR are work normally), but the  parallel data which RX  output is not normal, I found that the  position of data aligner (outside of transceiver) is continually to change,( The data aligner is verified correctly by case 1 at same data rate), so I think the problem is likely generated by transceiver, but I can not provide further evidence. I want to know that the above operation is right or not? If not, could you give me some advice?

      Just for the above operation, because I will use one reset signal outside of FPGA to reset whole system under the condition of not  power-down.

Brs,

Lambert

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquiries related to the XCVR dynamic reconfiguration. To ensure we are on the same page, just to check with you on the following:

1. What is the FPGA that you are using?

2. Which Quartus version are you using?

3. I understand that the RX parallel data seems to be having incorrect word boundary when you reconfigure to a specific data rate. To further narrow down the problem, just to check if you have had a chance to perform a Modelsim simulation with your design? This would be helpful to isolate any functional problem prior to hardware testing.

Please let me know if there is any concern. Thank you.

[lambert_yu]

Hi cheepin,

     1. arria 10 , 10ax115n2f45e1sg

     2. quartus 16.0

     3. from the simulation result, there's no error.

     Now, just through some delay between POR (default data rate stable) and next dynamic reconfig(same data rate),  it can work.

     But now I have another question, after dynamic reconfiguration of  RX simplex, refclk is okay, cal_busy is de-asserted,  ana_rst and dig_rst sequence is okay,  CDR can not lock sometime and locktoref is not asserted. And I manually  set ana_reset and dig_reset, CDR can not lock to refclk yet, I don't know what's wrong.

Brs,

Lambert

[CheePin_C_Intel]

Hi,

Thanks for your update.

When you refer to CDR cannot lock, just to clarify if you are referring to the not able to lock to data? 

Are you using the XCVR reset controller? If not, it is recommended to use the reset controller to correctly sequence the reset.

In addition, it would be great if you could check on the CLKUSR and CDR refclk to ensure that they are directly sourced from free-running oscillators on board. This is to ensure successful power up calibration and re-calibratioin.

By the way, are you using embedded streamer + multiprofiles to reconfigure? If not, you can try this where the embedded streamer will take care of all the reconfiguration with few registers writing.

I would recommend you to use the latest Quartus version to see if there is any difference.

Please let me know if there is any concern. Thank you.

[lambert_yu]

Hi CheePin,

   I have found the root cause, please ignore this problem.

Brs,

Lambert

[CheePin_C_Intel]

Hi,

Thanks lot for your update. Glad to hear that you have managed to resolved the problem. Thank you.