Accessing image stored in SDRAM sent through PCIex from Intel Atom host on DE2i-150

[Altera_Forum]

Hi all, i am currently working on hardware accelerator for a gesture recognition application on DE2i-150. 

Hope there is anyone can help me on my problems written below.  I have successfully sent webcam image(640x480x3bytes) to SDRAM in FPGA through PCI express (Avalon Memory mapping). I wish to do some image processing on the image stored in SDRAM. However, i have no idea how to access the data stored in SDRAM. I am using QSYS components now as the PCI ex has to be done there. Is there any Qsys component that can act as SDRAM controller which allows me to access the data ?? https://www.alteraforum.com/forum/attachment.php?attachmentid=8841

[Altera_Forum]

You can use the Frame Reader component, as you have already included in your system. 

 It will read the image data from SDRAM and supply it in Avalon-ST stream format to your (new) IP block which can then process it.

[Altera_Forum]

--- Quote Start ---  You can use the Frame Reader component, as you have already included in your system.  It will read the image data from SDRAM and supply it in Avalon-ST stream format to your (new) IP block which can then process it.  --- Quote End ---    Thanks for your reply=)  I will try on it. BTW, this is actually a demo given in the DE2i-150 CD. (...\de2i-150\Demonstrations\FPGA\PCIE_Display)  It seems like this demo can't read the data from SDram and write data to SDram at the same time.. Is there any way to do simultaneous read/write operation on SDram?  https://www.alteraforum.com/forum/attachment.php?attachmentid=8842

[Altera_Forum]

The Frame Buffer component shown in your system does "simultaneous" read/write operation on SDRAM. 

 It is not really "simultaneous" as the SDRAM chip itself can only process one transaction at a time, but the burst transactions are interleaved (e.g. write 128 words, read 128 words, .....)

[Altera_Forum]

`timescale 1 ps / 1 ps 

module test_use_manual_input_read_2(  //avalon master  avm_m0_address, // m0.address  avm_m0_byteenable_n,  avm_m0_chipselect,  avm_m0_read_n, // .read  avm_m0_waitrequest, // .waitrequest  avm_m0_readdata, // .readdata  avm_m0_readdatavalid,  //avm_m0_write_n, // .write  //avm_m0_writedata, // .writedata      clk, // clock.clk  reset, // reset.reset    seven_seg_out,  user_press_count_n,  user_press_start_n,  done,  avm_m0_state,  avalon_address,  seven_seg_out_2    );    //avalon master  output reg [31:0] avm_m0_address; // m0.address  output [3:0] avm_m0_byteenable_n;//4'b1111 means full 32bit  output avm_m0_chipselect;  output avm_m0_read_n; // .read  input avm_m0_waitrequest; // .waitrequest  input [31:0] avm_m0_readdata; // .readdata  input avm_m0_readdatavalid;  // output avm_m0_write_n; // .write  //output reg [31:0] avm_m0_writedata; // .writedata  output reg [31:0] seven_seg_out;  output [31:0] seven_seg_out_2;  input user_press_start_n;  input user_press_count_n;  output reg done;  reg [2:0] avm_m0_state;  output [2:0] avm_m0_state;  output [31:0] avalon_address;  input clk; // clock.clk  input reset; // reset.reset  parameter start_address = 32'h00000000;  parameter end_address = 32'h00000000+32'd1228800;     always@(posedge clk)  if(reset) begin   avm_m0_state<=0; done<=0;  end  else begin  case (avm_m0_state)  0: if(user_press_start_n)avm_m0_state <=0;  else begin avm_m0_state <=1;avm_m0_address<=start_address; end   1: if(avm_m0_waitrequest) avm_m0_state<=1;//request to read  else begin avm_m0_state<=2;end//start to read and flip  //2: if(avm_m0_readdatavalid) begin seven_seg_out<= avm_m0_readdata; avm_m0_state<=3;end  // else begin avm_m0_state<=2;end     2: begin seven_seg_out<= avm_m0_readdata; avm_m0_state<=3;end  3: if(user_press_count_n) avm_m0_state<=3;//request to write  else begin avm_m0_state<=4;end  4: if(!user_press_count_n) avm_m0_state<=4;//request to write  else begin avm_m0_state<=5; avm_m0_address<=avm_m0_address+32'h4;end   5: if(avm_m0_address==end_address) begin avm_m0_state<=0; done<=1; end  else avm_m0_state<=1;  endcase  end  assign avm_m0_byteenable_n = 4'b1111;  assign avm_m0_read_n = ~(avm_m0_state==1 || avm_m0_state==2);  assign avm_m0_chipselect = (avm_m0_state==1 || avm_m0_state==2);   assign avalon_address = avm_m0_address;  assign seven_seg_out_2= avm_m0_readdata; endmodule       i have re-written the code i use this code to make a custom qsys component (avalon master) i am trying to accessing the sdram which has address 0x0800_0000 until 0xffff_ffff  i store my image into sdram at starting address address 0x0800_0000 until 0x0812_c000  does all master reads value from slave according to this diagram?? https://www.alteraforum.com/forum/attachment.php?attachmentid=8887   do i need to read "readdatavalid' value from slave when i perform "read from slave to master"??? i need help urgently hope there is someone can help me thankss

[Altera_Forum]

Apology. This kit includ the 64GB mSATA SSD, does anyone know?

[Altera_Forum]

Hi, 

  I am working on same board (DE2i-150) with camera TRDB-D5M. I couldn't use PCIe for camera configuration as hardware in the Quartus II (12.1) software shows only USB Blaster and not PCIe. Though I have installed the PCIe successfully. I can capture the image using USB blaster. But not using PCIe. Can you please help me to use PCIe for this application?  Also I am planning to save the image in SD card and accessing SD card from CPU for further work of my project (Edge Detection). Can you guide me with this?

[Altera_Forum]

--- Quote Start ---  Hi all, i am currently working on hardware accelerator for a gesture recognition application on DE2i-150. Hope there is anyone can help me on my problems written below.  I have successfully sent webcam image(640x480x3bytes) to SDRAM in FPGA through PCI express (Avalon Memory mapping). I wish to do some image processing on the image stored in SDRAM. However, i have no idea how to access the data stored in SDRAM. I am using QSYS components now as the PCI ex has to be done there. Is there any Qsys component that can act as SDRAM controller which allows me to access the data ?? https://www.alteraforum.com/forum/attachment.php?attachmentid=8841   --- Quote End ---    Hello Sir, Do you have already a working example for what you planed to do? I am investigating the same issue and I do not have any clue what i should do. Thanks