Agilex EMIF DDR4 LRDIMM 4 rank Address/command placement?

[brian1211]

What is the required pin placement in the address/cmd subbank for a DDR4 LRDIMM with 4 ranks.  The table:

https://www.intel.com/content/www/us/en/content-details/655987/external-memory-interface-emif-pin-information-for-intel-agilex-devices-xls-format.html

does not cover this configuration.  

[AdzimZM_Intel]

Hi Brian,

You can use DDR4 Scheme 1A and DDR4 Scheme 1.

Regards,

Adzim

[brian1211]

Using Scheme 1A should the CS_N_2 and CS_N_3 be put in the same place as for Scheme 1?  Lane 3 index 0 and 1. 

[AdzimZM_Intel]

Yes put it in Lane 3 index 0 and 1.