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Agilex5 mipi phy IP configuration issue

PAA
Beginner
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We are attempting to test CSI IP on Agilex5 on AXE5-Eagle Arrow Development board, and find that the byte Location assignments on the mipi phy seems to have bug, as it does not allow us to use odd bytes. If we assign odd bytes and attempt to compile, it results into signal connection errors. No such error is seen for even byte assignment
We need to use byte 1 and byte 4 on Bank 2B, but byte 1 assignment fails.  
(Note: the label on support server request does not give an option to select mipi phy ip, hence selected Display Port|HDMI) 

Please see the attached images: ByteLocation0_as_Byte0.pngByteLocation4_as_Byte4.pngByteLocation5_as_Byte4.pngByteLocation6_as_Byte6.pngDevice NameDevice Name

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Wincent_Altera
Employee
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Hi,

 

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate and get back to you soon. Thanks for your patience.

 

Best regards,

Wincent_Intel


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Wincent_Altera
Employee
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Hi,

If we assign odd bytes and attempt to compile, it results into signal connection errors. No such error is seen for even byte assignment
>> if you refer to our user guide under 4.1. Identifying Pin Assignments Based on Byte Location
>> MIPI D-PHY design using 2 data lanes and 1 clock lane assigned to byte location 7
>> Hence, the scenario you seeing is expected.

wchiah_0-1728030257445.png


If we assign odd bytes and attempt to compile, it results into signal connection errors. No such error is seen for even byte assignment
>> you may need to assign the remaining unused pin to prevent the error
>> 4.4. Using the Remaining I/O Pin from Same Byte Location

Hope that clarified ,

Regards,
Wincent_Intel

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Wincent_Altera
Employee
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Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

 

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.


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PAA
Beginner
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Hi Wincent, 

Thanks for your reply. We have been following the guidelines already.
There has been a bit of an update, we are now using byte 6 and byte 1.
I was having trouble to map byte 1 to link 0, but was able to compile when I changed the byte-1 allocation to Link-0 and Byte-6 allocation to link-0.
Additionally the byte number in the GUI, even after compiling the project is seen to be incorrect. 
Please see attached screenshot for explanation. 
To re-iterate the original request, the GUI cannot display odd bytes in the 'link tabs'.
I am using Quartus 24.2 

BR,
Pushpraj Adhage


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Wincent_Altera
Employee
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Hi Pushpraj,

Thanks for your reply and clear picture clarification, Please allow me to have sometime to check on the error that you seeing.
To ensure that we are looking at the same picture, is it possible to attach the error design .qar in here ?
So that I am not looking at different setup.

Regards,
Wincent_Intel

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Wincent_Altera
Employee
410 Views

Hi Pushpraj,

Upon check with our internal development team.

  • The GUI display you see on Link x tab -> link x location,
  • it can only display even number. (if you put byte 0, 2, 4, 6 it is fine. If you put 1, 3, 5, 7 you will see it go to 0, 2, 4, 6).
  • Our team is fixing this issue, and the fix will be available in Quartus v24.3.1 in few month later (subject to change)
  • At the same time, we are filling a FPGA knowledge based article to inform other user about this behavior. Pending to be available within 1-2 weeks.

At the meantime, To ensure that the entered byte location is correctly assigned, please verify that in the table showed in DPHY IP / IP Configuration tab Enabled Links section shows the desired byte location for each enabled Link. 

Hope this is clarified and work for you. Let me know if you have any further question.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

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PAA
Beginner
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Hi Wincent, 

Thank you for accepting the bug report. I will evaluate it again when Quartus v24.3.1 is released in next couple of weeks. 

Best Regards,

Pushpraj 

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Wincent_Altera
Employee
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Hi Pushpraj,

Thanks for your reply, do you have any further question ?
Else , Can I have your permission to close this loop and transition to community support ?

Regards,
Wincent_Intel

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Wincent_Altera
Employee
318 Views

Hi,

I believe my previous reply had clarified all needed, I will transition this to community.

Nevertheless, you can still response to this forum case anytime within 20 days, and I will be available to assist you.

Rest assured, even after the ticket is closed, we will continue to keep you informed of any developments until the issue is resolved..

We appreciate your understanding and we are committed to assisting you with any further questions.


Regards,

Wincent_Intel


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PAA
Beginner
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