CXL IP DVSEC

[RicardoC]

Hi,

Is the PCIe DVSEC registers for CXL Device implemented either in the R-Tile CXL HIP or in the Soft Wrapper? If not, is there an Intel IP that can be attached to the CXL.IO port that can provide such functionality?

Thank you,

Ricardo.

[JohnT_Intel]

Hi Ricardo,

If you are refering to Figure 4 of CXL1.1 IP User Guide, yoyu will observed that the CXL.MEM and CXL.IO is implemented in soft logic. Only the PHY willbe on the Hard IP.

[RicardoC]

Hi John,

Thank you for the feedback.

We can use Figure 4 of the CXL IP User Guide as a reference, but I do not intend to use the Design Example in this project. I was wondering if the registers defined in the CXL spec and the appropriate surrounding logic is present when the CXL IP is generated in the platform designer. 

These are the PCIe DVSEC for CXL Device defined in the CXL spec:

Thank you,

Ricardo.

[JohnT_Intel]

Hi Ricardo,

If you are refering to CXL Type 3 implementation then the DVSEC will be fully soft-logic.

[RicardoC]

Hi John,

Thanks for the information, but it seems that you are still referring to the Design Example. We would like to use the CXL IP for our own project and I would like to know if the DVSEC is implemented in the IP provided by Intel or if this has to be developed by customers.

Thank you,

Ricardo.

[JohnT_Intel]

Hi,

I am refering to the IP (R-tile Intel FPGA IP For Compute Express Link) that you are planning to used. If you look at the Figure 4, the IP will have the connection till HDM interface where user will be designing their own iAFU.

If you are using Intel R-tile for Compute Express Link then you will need to write your own CXL wrapper design. As it will only exported out CXL.IO, CXL.MEM and CXL.CACHE interface.

[RicardoC]

Hi John,

Thank you for the confirmation.

Regards,

Ricardo.

[JohnT_Intel]

Hi,

Please let me know if you have any other queries.

[RicardoC]

Hi,

Instantiating the Intel R-Tile for Compute Express Link IP in Platform Designer gives me an option to choose the CXL Function Mode as:

-Full TLP Bypass

-Partial TLP Bypass

-Normal

If "Normal" is selected, a new tab appears with options to configure "CXL DVSEC Settings", "Device ID", "Vendor ID", capabilities, etc.

Can you clarify what the difference is between these 3 modes, and also if the above listed features under "Normal" are operational?

Thank you,

Ricardo.

[JohnT_Intel]

Hi,

Currently the IP you are using is not suitable and we are updating new IP in 23.1. For now, please use R-Tile Intel FPGA IP for Compute Express Link (CXL) IP.

[RicardoC]

Hi John,

Will the the new IP in 23.1 have support for the CXL configuration and DVSEC registers?

Thank you,

Ricardo.

[JohnT_Intel]

Hi,

Currently the information on it is still not available. It should be schedule to be available in WW15.

Thanks.

[RicardoC]

Thank you, John.

[JohnT_Intel]

Hi,

Please let me know if you have any queries. If not, you may wait for the updated IP released in Quartus 23.1 and documentation.

[JohnT_Intel]

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