I'm trying to build a very minimal PCIe device, so I've instantiated PCIe HIP through MegaWizard, the retrieval info in vhdl format is attached.
When I generate this through
mw-regenerate pcie.vhdI get various other files, including pcie.sdc, which defines the two input clocks. however both are listed as 100 MHz clocks, which is incorrect as the free-running fixedclk_serdes is 125 MHz.
Looking at the perl script responsible for generating this code, this line is dependent on the tl_selection setting -- if it's a value between 1 and 5 the generated clock definition is
create_clock -period "125 MHz" -name {fixedclk} {fixedclk_serdes_pcie}where "pcie" is the base name of the variation. This I could work with. If the tl_selection setting is not between those values, instead I get
create_clock -period "100 MHz" -name {fixedclk_serdes} {fixedclk_serdes}which does not work for me since the free running clock I have is 125 MHz. Manually fixing this to 125 gives me a working design that indeed enumerates fine, but regenerating the IP block will overwrite that file again.
The suggested setup on page 166 of the PCI Express User Guide would not work with either as the fixedclk_serdes would be driven by a PLL, so it wouldn't be a base clock anymore.
Currently it seems that my best bet would be to somehow set the tl_selection parameter for the instance to 1 (Full Avalon Interface), like Qsys does. Can I do this in a MegaWizard based design so that it is somewhat futureproof, or am I completely lost here?
