Can we generate EMIF DDR4 without mem_alert_n or not connect the emif_alert_n in the instantiation

[BKB]

Hi

Please refer the attached png/pdf of the pin map of two EMIF instantiations in our design. The initial board design shared a FPGA IO bank for some address/command  signals of the two instances, rendering that bank unusable.This limits the maximum memory size to 32GB across teh 3 banks of IOs of each EMIF instance.  

With one change of mem_address[17] moved back from the location in shared bank to the location of mem_alert_n in the png file (which is the recommended location in the recommended DDR command/address) the total addressable size can be increased to 64GB. but I am not able to find the right location for mem_alert_n.

I did not find an option to not generate mem_alert_n in teh ip generation .

When I don't connect the mem_alert_n input, or when I tie it off to 1'b1, the fitter fails with message that the message

Error(17045): Input port I of I/O input buffer ........."mem_alert_n.inst[0].b|no_oct.ibuf is not connected. It must be driven by a top-level pin"

So is there a way to either not generate mem_alert_n or not connect in the instantiation and still complete the implementation ?.

Best,

BB

[AdzimZM_Intel]

Hi BB,

The alert_n signal is required for DDR4 interface.

There is no other option. You need to move the DQ group from A/C IO Bank to place the alert_n pin in IO Lane 3.

Regards,

Adzim

[AdzimZM_Intel]

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[BKB]

Hi Adzim,

Thanks for the earlier response confirming that mem_alert_n signal is required for the implementation.

Again referring to the earlier attached pdf with the pin out for the two EMIF interfaces, I am trying to increase the accessible memory size from 32 GB to 64GB with the existing pinout with minimal changes i.e. use only 3 IO Banks per memory IO and ignore the 7th IO bank which has IOs from both EMIF. The mem_alert_n for both the interfaces (Bank 2M for MC0 and Bank 2H for MC1) is located at the pin for mem_a[17]. I moved the mem_a[17] to the mem_alert_n pin locations and moved the mem_alert_n to the rzq pin location for both EMIFs. This leaves 2 RZQ to be mapped and only 1 pin location available in bank 2K (PIN_AJ68).

As the RZQ pin is just a resistor grounded, is it possible for two EMIF to use teh same pin location for RZQ.
OR
Each IO bank has one pin for IO_RZQ_.......... Is it possible to use any other pin with the same bank for RZQ i.e. both EMIF interfaces have RZQ in the same bank? one can be at the designated pin location for RZQ and other at any of the other available pins within the bank.
OR
Can the RZQ pin be mapped to some other bank not adjacent to EMIF (BANK3d) but have a different IO standard spec as ther other pins in that bank are not 1.2 v standard.

In short is there any way to map the extra RZQ and get the 64 GB with minimal pin reroute (estimating 6).

the other idea of full size access with 4 IO banks per EMIF is no go as it requires complete boad reroute.

Best,
BB

[AdzimZM_Intel]

Hi BB,

"As the RZQ pin is just a resistor grounded, is it possible for two EMIF to use teh same pin location for RZQ"

• I haven't try to map 2 RZQ port to one pin location as it not a recommended way to place the RZQ pin but you can try it on Quartus and check if the Quartus can Fit the placement.
• I cannot guarantee the functionality of DDR to work well or verify on hardware and you need to take your own risk to have this placement.

"Each IO bank has one pin for IO_RZQ_.......... Is it possible to use any other pin with the same bank for RZQ i.e. both EMIF interfaces have RZQ in the same bank? one can be at the designated pin location for RZQ and other at any of the other available pins within the bank."

• Cannot, need to use the designate location.

"Can the RZQ pin be mapped to some other bank not adjacent to EMIF (BANK3d) but have a different IO standard spec as ther other pins in that bank are not 1.2 v standard."

• UG has stated that the RZQ pin can be placed in any I/O bank in same I/O column that has same voltage standard.
• https://www.intel.com/content/www/us/en/docs/programmable/683741/24-1-19-2-8/general-guidelines-39744-01.html

I'm have a doubt that the alert_n pin can place in RZQ pin location.

You should check this in Quartus Fitter compilation.

Regards,

Adzim

[BKB]

"I haven't try to map 2 RZQ port to one pin location as it not a recommended way to place the RZQ pin but you can try it on Quartus and check if the Quartus can Fit the placement."

Quartus completed the build with 2 RZQ ports to one pin location for our existing board and the proposed one.

"I cannot guarantee the functionality of DDR to work well or verify on hardware and you need to take your own risk to have this placement"

The build seems to be working in the initial tests. If you cannot guarantee functionality, could you please confirm with internal experts if this is a valid implementation and the design would work going forward

"I'm have a doubt that the alert_n pin can place in RZQ pin location. You should check this in Quartus Fitter compilation."

Quartus implemented the design with the alert_n pin in the rzq location. In fact that's quartus plan/fits preferred location when the address command pins are fully occupied or when we run the build without assigned pin locations. Look at the attached snapshot from the IP generation window where alert_n pin location can be selected. The tool gives error for selection "I/O lane with DQS group" but works for other options.

I ran an example build with memory configurations occupying the whole address/command bank. In this case the rzqin pin is placed in an bank other than with address/command IO.  In our current board, alert_n was at the location for addrress[17]. So with that occupied for increasing memory size, the rzq pin was the only available pin for alert_n.

I request that you please confirm internally that this option can work. i.e. alert_n at rzq location in address/command and one rzq driving two emif rzq input.

Best,

BB

[AdzimZM_Intel]

Hi BB,

There is no hardware validation can be done to verify that this configuration is working because the alert_n signal is not placed in RZQ pin location on the boards, and this placement is not a recommendation of RZQ pin.

If you find that the Quartus can compile the design with the pin placement and config, then most likely the design might be working.

But still, you need to take your own risk since this is not a recommended way.

Regards,

Adzim

[BKB]

Hi Adzim,

I understand that there is current hardware to validate the placement of alert_n pin on recommended rzq pin and also for two RZQ ports driven by one pin. Hence i request you to please reach out to the EMIF IP design team and share their insights.

Best,

BB

[BKB]

Hi Adzim,

I understand that there is  NO current hardware to validate the placement of alert_n pin on recommended RZQ pin and also for two RZQ ports driven by one pin. Hence I request that you please reach out to the EMIF IP design team and share their insights.

Best,

BB

[AdzimZM_Intel]

Hi BB,

You can share the RZQ pin with two RZQ ports but the VCCIO need to be the same.

If not, the calibration will fail.

For alert_n placement, there is not much restriction.

You may use your current plan to fix your problem.

Regards,

Adzim

[BKB · Accepted solution]

Thanks Adzim.

Best,

BB