DDRII SRAM is very similar to QDRII, except that QDRII uses DDR on the address as well as write data. Cypress released an app note on DDRII, see http://www.eetasia.com/art_8800376255_499486_22987e61200509.htm (http://www.eetasia.com/art_8800376255_499486_22987e61200509.htm)
or Google search for "How To Interface DDR-II SRAMs with Stratix II Devices". Cypress was willing to release the design code to me under NDA, so you may also be able to get it from them under NDA. I think I got a copy of the article as PDF from Cypress as well, but if so, I've misplaced it.
You have choices on resynchronizing return read data after it is reclocked by CQ/CQN:
1. return directly to your source clock
2. use 1 stage of intermediate resynch clock with some phase shift from your source clock
3. use a ring buffer and a state machine at powerup that determines the read offset in the ring buffer
4. wrap the LD_L and REN signals around externally (as bidirects) if they can be safely clocked by CQ or CQN and use them to form a write enable to a fifo.
The current (Quartus 6.0 and later) QDRII megacore uses# 3; the Cypress design used# 2, I think. At the frequencies I'm using in my DDR-II SRAM design, the timing works out clean for me to use# 1.
\chuck
