DDR4 EMIF IP Inquiry for Arria 10

[anonimcs]

Dear A10 DDR4 EMIF IP Owners,

I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP cores have their own timing constraints with their own .sdc files. But it seems that these constraints are not applied when I compiled my design. I had to maximize the Fitter settings for the whole project to overcome the timing violations caused by the IP itself. However, there must be a better way to fix the violations instead of tinkering around the Fitter settings. I have already shared quite a lot of detailed information to some support engineers in this community post, but they were unable to fix the issue. Could you give me a hand with this one ? I still keep the Quartus archives for the project (for Balanced Fitter settings), I can share those with you if necessary.

Thanks in advance

[WeiHanT_Intel]

Hi Anonimcs, 

Thanks for using Intel Community Forum. Please be informed that the support AE who handles EMIF is currently Out of Office. We will get back to you after 20-Jun'24. We apologies for any delay in response and appreciate your patience and understanding. 

Regards,

WH

[AdzimZM_Intel]

Hello,

May I know what is the timing violation of the design?

Can you provide the DDR4 timing report from the Timing Analyzer report?

Regards,

Adzim

[anonimcs]

Dear @AdzimZM_Intel , 

Please find the reports attached in the .zip file. Looking forward to your response.

Kind regards

[AdzimZM_Intel]

Hi

Based on the DDR timing report, the timing violation occurred in Core path.

Usually this timing violation is not inside the EMIF IP module, but it is within the EMIF IP module and other module in your design.

You may check the clock supply to the other module in this case.

The EMIF IP may need the user logic connected to it, to run at quarter rate of memory clock frequency.

You can change the clock supply to has a quarter rate frequency supplied to the user logic.

Regards,

Adzim

[anonimcs]

Hi,

I believe you mean this clock "fpga_emif_ddr4_core_usr_clk" in fpga_emif_ddr4 module. For this design, it's indeed less than a one fourth of the memory's clock, but I also have another design (with same modules, only with different generic values) where the fpga_emif_ddr4_core_usr_clk is exactly one fourth of the memory clock. But even in that design, I got similar timing violations (the place of the violation is the same, the negative slack is close to what I shared before). So I don't think the frequency of fpga_emif_ddr4_core_usr_clk is my issue here...

[AdzimZM_Intel]

Hi

Can you provide a design to replicate this issue?

Regards,

Adzim

[anonimcs]

Hi @AdzimZM_Intel ,

I can provide the project archive, but you'll need to send me a link via email to upload the archive files to Intel's portal as they exceed the file upload limit to the forums (which is 71 MB but the archive files are more than 100 MB)

Looking forward to hearing from you,

Kind regards,

[AdzimZM_Intel]

Hi

I already sent an email to you.

Please let me know in this forum once you have replied to the email.

Thank you.

[anonimcs]

Hi @AdzimZM_Intel ,

I've sent you the archive files. Looking forward to your response.

[AdzimZM_Intel]

Hi

The pin location for pll_ref_clk and oct_rzqin signals are not following the recommended location provided in the Arria 10 EMIF User Guide. Link: https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/general-guidelines-39744-01.html

Please place both pins in Address & Command group as it will affect the timing result.

If the timing violation still occur, you may need to reconstruct the pin location of the design or optimize the timing by reconfiguring the Synthesis and Fitter setting.

The link below shows some settings that might assist you in resolving core timing issue, but you may use your previous setting as well to resolve the issue.

Link: https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/optimizing-timing.html

Regards,

Adzim

[anonimcs]

Sorry for the late reply. Do you mean that I should change pll_ref_clk and oct_rzqin's pin constraints so that they need to be in IO Bank 2K for HPS and 3B for FPGA instead of 2J and 3A respectively ?

I'm attaching my current constraints (converted to txt) for HPS and FPGA here. Looking forward to your response.

Kind regards

[anonimcs]

@AdzimZM_Intel @WeiHanT_Intel any comments ?

[AdzimZM_Intel]

Hi @anonimcs 

According to the ddr4.txt, IO Bank 2K for HPS and IO Bank 3B for FPGA are the Address and Command group.

You should place the pll_ref_clk and oct pins in that IO Bank.

Regards,

Adzim