Direct interface Bus (DIB)

[ymiler]

Hi

I would like to generate a behavioral model of the DIB for simulation.

However, when I create a DIB IP and click on the 'Generate HDL' icon, part of the output files include gibberish instead of regular code.

Attach 1 file for example 

How can I fix this?

FPGA device : 1SM21BHU2F53E2VG (startix 10)

Quartis version : 22.3.0

Thank you 

Yishay 

[Kenny_Tan]

Kindly take note that there will be a delay in replying to the forum for this case. Because we have 5 consecutive public holidays but we will try our best to address your question as soon as possible.

Instead of sending us the .txt file, do you mind sending us your *.qar files for us to investigate?

[SyafieqS]

Hi,

That seem to me like an encrypted file generated from PD.

Does this affect you behavior simulation of the DIB?

Let me know any concern on this.

[SyafieqS]

Also,

DIB IP is only used for Intel® Stratix® 10 GX 1SG10M variant.

If you use that device, how can you access to the IP?

The IP is hidden to all devices accept s10 10m.

Let me know we can have a quick call.

[ymiler]

Hi

My FPGA belong to startix 10 GX family - as I wrote above my device is : 1SM21BHU2F53E2VG 

About the simulator ( simvision -cadence)  - I got error since a have encrypted files 

And , sure no probelm to a quick call  ( teams ? I'm Intel emploee )

Yishay 

[SyafieqS]

Yes sure,

But do you mind telling me how you instantiate DIB IP?

Is it directly from IP using the device mentioned?

As far as I am concern this IP is solely for 10M S10 device variant and I have double checked that using your device the IP is not available.

[ymiler]

Hi ,

Thank you for your answer

I solved the issue ,  I had to set my simulation tool in the  “generate hdl”  GUI , then Quartus creates all the simulation files

regardign your Q

But do you mind telling me how you instantiate DIB IP? 

Is it directly from IP using the device mentioned?

-I just opened it  from the Quartus IP catalog 

Thank you

Yishay

[SyafieqS]

Let me know if there is any other concern on this.

[ymiler]

Yes , I have other concern .

I have 2 Q about INTEL instructions regarding the DIB architecture :

Link : https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/reset-architecture.html

 1)Quote : "you must track all the dib_ready pins from both dies to determine that both intel Stratix 10GX variants are ready for data transactions"

How can I track all the dib_ready pins from both dies ? How DIE0 get the information about “ready” flag from DIE1 ?

2)Quote : " The reset of the PL (main reset of the design _ should be released only after all the dib_ready_n from all the used dib instances are low"

Why does it relevant the reset of the PL ?

Why DIB depends to the PL ?

[SyafieqS]

Hello Yishay,

I can see the concern have been addressed in the email loop. We can follow up from there.