E-Tile Transceiver Native PHY Intel Agilex FPGA IP refclk error

[kokodo]

Hello,

I would like to use PIN_CE18 for E-TILE transceiver 156.25M reference clock input,but these error messages appear.I have tried using a iopll fpga ip out clock as a reference clock,it made a similar error.

Only when I use the HPS CPU output clock as a reference clock is it OK.But that's not the clock frequency I need.

Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 HSSI_REFCLK_CLUSTER(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic HSSI_REFCLK_CLUSTER in region (390, 135) to (390, 141), to which it is constrained, because there are no valid locations in the region for logic of this type.
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)
Error(175020): The Fitter cannot place logic HSSI_REFCLK_CLUSTER in region (390, 139) to (390, 142), to which it is constrained, because there are no valid locations in the region for logic of this type.
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)
Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error(16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 9 errors, 2 warnings
Error: Peak virtual memory: 13808 megabytes
Error: Processing ended: Wed May 8 19:12:00 2024
Error: Elapsed time: 00:06:49
Error: System process ID: 75257
Error(21794): Quartus Prime Full Compilation was unsuccessful. 11 errors, 127633 warnings

How should I give this reference clock?

My Quartus version is 22.4.

Thank you!

[kokodo]

Error(175022): The HSSI_XCVR could not be placed in any location to satisfy its connectivity requirements
Error(175006): There is no routing connectivity between source HSSI_REFCLK_CLUSTER and the HSSI_XCVR
Error(175022): The HSSI_XCVR could not be placed in any location to satisfy its connectivity requirements
Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between source HSSI_REFCLK_CLUSTER and the HSSI_XCVR
Error(175022): The HSSI_XCVR could not be placed in any location to satisfy its connectivity requirements
Error(175001): The Fitter cannot place 1 HSSI_XCVR, which is within E-Tile Transceiver Native PHY Intel Agilex FPGA IP serdes_xcvrnphy_fme_410_yhezbna.
Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between source HSSI_REFCLK_CLUSTER and the HSSI_XCVR
Error(175022): The HSSI_XCVR could not be placed in any location to satisfy its connectivity requirements
Error(175001): The Fitter cannot place 1 HSSI_XCVR, which is within E-Tile Transceiver Native PHY Intel Agilex FPGA IP serdes_xcvrnphy_fme_410_yhezbna.
Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between source HSSI_REFCLK_CLUSTER and the HSSI_XCVR
Error(175022): The HSSI_XCVR could not be placed in any location to satisfy its connectivity requirements
Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 HSSI_XCVR(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 HSSI_XCVR, which is within E-Tile Transceiver Native PHY Intel Agilex FPGA IP serdes_xcvrnphy_fme_410_yhezbna.
Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between source HSSI_REFCLK_CLUSTER and the HSSI_XCVR
Error(175022): The HSSI_XCVR could not be placed in any location to satisfy its connectivity requirements
Error(175001): The Fitter cannot place 1 HSSI_XCVR, which is within E-Tile Transceiver Native PHY Intel Agilex FPGA IP serdes_xcvrnphy_fme_410_yhezbna.
Error(16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between source HSSI_REFCLK_CLUSTER and the HSSI_XCVR
Error(175022): The HSSI_XCVR could not be placed in any location to satisfy its connectivity requirements
Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error(16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 11 errors, 2 warnings
Error: Peak virtual memory: 13325 megabytes
Error: Processing ended: Thu May 9 17:18:59 2024
Error: Elapsed time: 00:05:46
Error: System process ID: 71646
Error(21794): Quartus Prime Full Compilation was unsuccessful. 13 errors, 127633 warnings

[Kshitij_Intel]

Hi,

Can you please share which Quartus version and device you are using?

Also, you can refer to the Error(175020): The Fitter cannot place logic pin that is part of... (intel.com)

Error (175020): Illegal constraint of PLL output counter to the... (intel.com)

Hope this helps.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel