F-Tile Serial Lite IV simulate 仿真

[yanghao1]

Hi,

My design includes a f-tile serial lite iv ip and a system pll ip for it. When I try to run simulation for the design. The system pll's output port lock is dash line, and no clk out from pll ip.

I know that the system pll ip cannot be simulated as standalone. But in my case, i connect it to the slite, but still dont work.

[Kshitij_Intel · Accepted solution]

Hi,

Try with the example design first.

1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User...

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel