FFT IP simulation : Warning: "sink_FIFO : scfifo" is not bound

Altera_Forum · ‎06-12-2018

Hello,

I am trying to simulate the Intel FFT IP in ModelSim Intel FPGA Starter Edition 10.5b, and I encounter a problem : the output "sink_ready" is X as soon as the reset is deasserted, and the fftpts_out is XXX... all the time.

Next, I explain first what I did, then I explain the problems observed. I put in attachment a screenshot of the simulation to show the problems described, the tcl files, and the entire folder with the quartus project and the ModelSim simulation under fft_example_tb.

Steps :

I create a Quartus project (Prime Standard Edition 16.1) targeting a Cyclone V FPGA, and generate an IP core FFT (variable streaming, 32K points, 16 bits resolution, natural input order, reversed output order) called fft.
I create a tcl script called create_library_for_fft.tcl, using as reference the one generated automatically under fft\simulation\mentor\msim_setup.tcl. In this script, I do all the vlog/vcom commands, except the last one regarding fft.vhd, which I do manually in ModelSim (steps 3.2 and 3.5 below).
In ModelSim
I create a project.
I add the fft file fft.vhd and the corresponding testbench fft_tb.vhd (the testbench is minimum to just show the problem).
I copy the hex files to the same directory and add them to the project.
I execute the command : source create_library_for_fft.tcl.
I compile my two files in the project.
I launch the simulation through Simulate > Start simulation

In my testbench, source_ready = 1, sink_error = 00, sink_valid/sop/eop = 0, inverse = 0, fftpts_in = 2048, sink_real/imag = 0 at the beginning.

Problems observed :

1. When starting the simulation, I see in the command window :

--- Quote Start ---

# Loading work.auk_dspip_avalon_streaming_block_sink(rtl)# ** Warning: (vsim-3473) Component instance "sink_FIFO : scfifo" is not bound.# Time: 0 ps Iteration: 0 Instance: /fft_tb/I_fft/fft_ii_0/auk_dspip_r22sdf_top_inst/sink_ctrl_inst File: ../fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_sink.vhd

--- Quote End ---

2. As said at the beginning, I have a problem with the following outputs :

"sink_ready" is X all the time except when the reset_n input is asserted to 0.
"fftpts_out" is XXX... all the time even when the reset_n is asserted to 0.
I also have "source_sop" = 1 while it should be 0, but maybe it's simply a consequence of the problem, so I didn't focus on this one for the moment.

When looking at the origin of the problem :

In the top file auk_dspip_r22sdf_top.vhd, the signal "fftpts_out" is UUU..., and :
"fftpts_out" get its value from "curr_fftpts",
"curr_fftpts" gets its value from curr_fftpts_s,
"curr_fftpts_s" is mapped to the output "curr_blk" of the block "auk_dspip_avalon_streaming_block_sink" instantiated as "sink_ctrl_inst",
In auk_dspip_avalon_streaming_block_sink.vhd :
"curr_blk" gets its value from "curr_blk_q",
"curr_blk_q" gets its value from "curr_blk_s",
"curr_blk_s" gets its value from "sink_fifo_q",
"sink_fifo_q" is an output of the block "scfifo" instantiated as "sink_FIFO", the block where there is a warning.

Since this block and these files are generated automatically, I never modified them.

I saw in this post (https://www.alteraforum.com/forum/showthread.php?t=51097) that someone had a similar problem where an output of the FFT was always X, and it has been pointed out that it could be due to library files missing, and it was advised to check the msim_setup.tcl file generated automatically. However, all the files mentioned in msim_setup.tcl are also in my tcl file.

Do you have any clue about the origin of the problem ?

I am not familiar with the libraries and tcl files, so maybe this is where I made a mistake.

Thanks in advance.

Jérôme

Altera_Forum · ‎06-20-2018

Hi Anand,

Thank you for your feedback. From your answer, I played a little bit with both tcl files, and now mine is working if I include the vsim command with all the parameters like in msim_setup.tcl :

vsim -t ps  -L work -L work_lib -L fft_ii_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev fft_tb

Before I was doing it with the GUI and only my testbench was included in the parameters of vsim.

Thanks,

Jérôme