Got stuck during establishing ethernet Communicaton using Quartus prime and Nios software.

[Prajwal_RJ146]

Dear Sir/Madam,

I am currently working on establishing Ethernet communication between a Cyclone V FPGA (5CEFA7F27I7) and a DP83867IR Ethernet Physical Transceiver IC using Quartus Prime 16.0.0 and Nios II - Eclipse software. I have attached several files for reference, including screenshots of the schematic, QSYS configuration, and the .bdf file.

Description:

1. Configuration:

   • QSYS Configuration: I am using a Nios II processor, Triple-speed Ethernet, and Scatter Gather DMA Controller IPs (one each for Tx and Rx).
   • HDL File Generation: After generating the HDL (.sopcinfo) file from QSYS, I converted it into a .bsf file and included it as blocks in the .BDF file (Top Module). Additionally, I am using a self-created gmii_mii_mux block for mode selection and an eth_phy_reset block.
   • Operating System: Micrium MicroC/OS-II is being used in nios ii software.

2. Testing and Code:

   • Initial Testing: I have verified the functionality of SDRAM and CFI_Flash, which are operating satisfactorily.
   • Network Initialization: I created a thread to run the InitNetwork function. The main file (hello_world1.c) has been attached for your review.
   • Manual Configuration: Since there are no existing libraries for the DP83867IR IC, I manually added the IC configuration and link_status_read functions in the Altera_Avalon_Tse.h and Altera_Avalon_Tse.c files.

3. Current Issue:

   • Detection and Configuration: The PHY is detected at address 0x00. However, it attempts to read the PHY ID from the remaining addresses, resulting in a warning: "Number of PHY connected is not equal to the number of channels; Number of PHY: 32, Channel: 1."
   • Error Messages: The console indicates that the link is established and displays the user IP address. However, when attempting to ping the unit from a PC, the following errors occur:
     • "Reply from 192.168.0.26: Destination host unreachable."
     • "Request timed out."

I would greatly appreciate your assistance in resolving these issues.

Thank you for your support.

[Prajwal_RJ146]

I have added a 2k ohm pull-up resistor to Pin No. 21 of the PHY IC (MDIO pin).

In the QSYS file, I have enabled the "Align Packet Headers to 32-bit Boundary" checkbox in the "Triple-Speed Ethernet" IP. After making these changes, the error previously appearing in the Nios II console output has been resolved. The current screenshots of the Nios II console window is attached.

However, when attempting to ping, I am still encountering the "Request Timed Out" error in the command prompt, and I have included a screenshot of this issue as well.

I would appreciate any guidance you can provide to resolve this remaining issue.

Thank you for your support.

[JingyangTeh]

Hi

Have you tried running the TSE example available in the link below:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-tse-sgdma.html

Regards

Jingyang, Teh

[Prajwal_RJ146]

Hello,

I downloaded the example projects you shared and began working on them. Since we are using a custom-designed board with a Cyclone V FPGA (5CEFA7F27I7), a DP83867IR, and an SDRAM IC, I modified the necessary IPs and removed the unnecessary ones in the QSYS. After compiling and running the program, I encountered Makefile and .elf errors while building in the Nios II software, but the exact errors were not displayed.

Observations from My Previous Project:

• There were no errors in the Nios II console output, but the ping between the PC and the board still could not be established.
• The board is receiving data but failing in transmission. When checked with the Signal Tap logic analyzer, I found that the pinging data transmitted from the PC is received through the FPGA's input pin via the PHY IC. However, the FPGA is neither transmitting data nor enabling the transmit enable signal.
• It appears that the PHY IC is not being programmed correctly, resulting in a clock rate mismatch. The Tx_clk frequency from the PHY IC is 2.5 MHz instead of the expected 25 MHz (screenshots are attached).

I would appreciate it if you could provide some guidelines on performing a loopback test. Additionally, it would be helpful if you could share any C programming code examples for executing a loopback operation.

Thank you for your time and assistance.

---

Best regards,
Prajwal RJ

[JingyangTeh]

Hi

Sorry that i missed out that the PHY you are using is different from the supported list.

In this case you would need to add in the PHY device into the driver so that the driver could interact with the PHY.

During the initialization you would need to add in the PHY device into the driver using the api "alt_tse_phy_add_profile()"

https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/phy-definition.html

I went through the datasheet and populated the PHY struct below

alt_tse_phy_profile TEXASDP83867= {"TEXAS DP83867",   /* Marvell 88E1512                 */

  00x80028h,     /* OUI                              */

  MV88E1512_MODEL,    /* Vender Model Number                      */

  0x23     /* Model Revision Number                     */

  0x11,          /* Location of Status Register                  */

  14,           /* Location of Speed Status                   */

  13,           /* Location of Duplex Status                   */

  10           /* Location of Link Status                    */

   /* Function pointer to configure Marvell PHY           */

  };

Regards

Jingyang, Teh

[Prajwal_RJ146]

Hi,

i observed the same outputs again, after adding the Details which you have gave.

Please find the attached Snapshots.

Thanks and Regards,

Prajwal RJ

[Prajwal_RJ146]

Hi,

I have an update regarding the loopback test:

Code Overview

In the Main_Code file, I implemented the loopback test as follows:

=====================================================================

void ethernet_loopback_test() {
// Initialize TSE and PHY
InitNetwork(); // Initialize the Triple-Speed Ethernet (TSE) IP
printf("TSE initialized.\n");
printf("PHY internal loopback mode configured.\n");

// Prepare Ethernet packet (64 bytes)
uint8_t tx_packet[64] = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // Destination MAC (broadcast)
0x00, 0x07, 0xAB, 0xF0, 0x0D, 0xBA, // Source MAC (example)
0x08, 0x00, // Ethertype (IPv4)
0x45, 0x00, 0x00, 0x2E, // IPv4 header (first bytes, rest as padding)
0x00, 0x00, 0x40, 0x00, 0x40, 0x11, // More IPv4 header
0xB8, 0x61, // Checksum (placeholder)
0xC0, 0xA8, 0x00, 0x19, // Source IP (192.168.0.25)
0xC0, 0xA8, 0x00, 0x1A, // Destination IP (192.168.0.26)
// Rest of the payload (padding for simplicity)
0xDE, 0xAD, 0xBE, 0xEF, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};

// Transmit packet
tse_mac_sTxWrite(tx_packet, sizeof(tx_packet));
printf("Packet transmitted.\n");

// Receive looped-back packet
uint8_t rx_packet[64] = {0}; // Initialize the receive buffer with zeros
tse_mac_aRxRead(rx_packet, sizeof(rx_packet));
printf("Packet received.\n");

// Compare transmitted and received packets
if (memcmp(tx_packet, rx_packet, sizeof(tx_packet)) == 0) {
printf("Loopback test successful! Packets match.\n");
} else {
printf("Loopback test failed. Packets do not match.\n");
}
}

=============================================================

Additionally, in the Altera_Avalon_tse.h file, I enabled the PHY loopback for debugging purposes by setting:

#ifndef ENABLE_PHY_LOOPBACK
#define ENABLE_PHY_LOOPBACK 1
#endif

Observations

After making these changes, the Nios II console output displays "Putting PHY in Loopback," followed by the warnings "WARNING: TX SGDMA Timeout."

I've attached a screenshot ("Nios II - Debug - Screenshot -1") for reference.

Further Analysis

I noticed that the Tx enable signal and the Tx data signal remain at "0" (both in and out of loopback mode). During debugging, I found that the Tx_clock from the PHY IC is fixed at 2.5 MHz, regardless of the speed configured in the Nios II software.

Interestingly, the Rx_clock changes correctly when I adjust the Ethernet speed settings on the PC (2.5 MHz, 25 MHz, 125 MHz, etc.). The data is also successfully captured in Signal Tap during a ping operation, indicating no issues on the receiving side or with the hardware design.

The problem seems to be on the transmitting side, where we are unable to configure the PHY IC correctly.

---

I would greatly appreciate your assistance in troubleshooting this Tx_clock issue. Please help me resolve this problem. I've also attached the project folder link for your reference.

Thank you for your support!

[JingyangTeh]

Hi

Going through your project.

Could you add in the line below in your main source:

alt_tse_system_info tse_mac_device[MAXNETS] = {

  TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(

    SYS_TSE,       // tse_name

    0,          // offset

    SYS_TSE_MSGDMA_TX,  // msgdma_tx_name

    SYS_TSE_MSGDMA_RX,  // msgdma_rx_name

    TSE_PHY_AUTO_ADDRESS, // phy_addr

    NULL,         // phy_cfg_fp

    SYS_DESC_MEM     // desc_mem_name

  )

};

It is to link the TSE with the msgdma. (Note the msgdma_tx_name could differ)

The msgma needed to be initialize properly so that the TSE could send and receive data.

Regards

Jingyang, Teh

[Prajwal_RJ146]

Hi Jingyang, Teh

Previously i was using the same tse_mac_device function at netwotk_utilities.c file and observed the same error. but as you requested to use that in main file, i've used that in main file and observed the different error in which the PHY detection itself is not happening. you can i find the attached code and output screenshots with this file.

Thank you

Regards

Prajwal RJ

[JingyangTeh]

Hi

Sorry that it made it worst. Going back to your screenshot the sgma error only happens when you enabled loopback. Could you try reverting back before the suggested change.

Is it possible if you share the full log in txt instead of screenshot.

Another thing, on the board are you selecting static IP or dynamic?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh